Patent application number | Description | Published |
20090090548 | CIRCUIT BOARD AND FABRICATION METHOD THEREOF - A circuit board is disclosed, including a core board, wherein at least one surface thereof has a core circuit layer with a plurality of conductive lands; a first dielectric layer disposed on the core board and disposed with a plurality of openings for exposing the conductive lands; a first coupling layer disposed on the first dielectric layer, the first coupling layer having a plurality of openings disposed corresponding to the openings of the first dielectric layer; and a first circuit layer disposed on the first coupling layer and a plurality of first conductive vias disposed in the openings of the first coupling layer for electrically connecting to the conductive lands of the core circuit layer. By the formation of the first coupling layer that connects the first circuit layer and the first dielectric layer, the bond strength between the first circuit layer and the first dielectric layer is enhanced, thereby preventing detachment and delamination as encountered in the prior art. The invention further provides a fabrication method of the circuit board described above. | 04-09-2009 |
20090146317 | PACKAGE SUBSTRATE HAVING ELECTRICALLY CONNECTING STRUCTURE - A package substrate having an electrically connecting structure are provided. The package substrate include: a package substrate substance with at least a surface having a plurality of electrically connecting pads formed thereon, allowing an insulating protective layer to be formed on the surface of the package substrate substance and the electrically connecting pads and formed with a plurality of openings corresponding in position to the electrically connecting pads so as to expose a portion of the electrically connecting pads, respectively; and a metal layer provided on an exposed portion of the electrically connecting pads, walls of the openings of the insulating protective layer, and a circular portion of the insulating protective layer encircling each of the openings thereof, and provided with a slope corresponding in position to a bottom rim of each of the openings. Accordingly, solder bleeding and short circuits are prevented. | 06-11-2009 |
20090308652 | PACKAGE SUBSTRATE HAVING DOUBLE-SIDED CIRCUITS AND FABRICATION METHOD THEREOF - A package substrate having double-sided circuits and a method of manufacturing the same are proposed. The package substrate includes a core board having a plated through hole, a plurality of first electrical contact pads, and a first solder mask layer formed on the core board. A first wiring layer and a second wiring layer are disposed on two opposite surfaces of the core board, respectively, and electrically connected to the plated through hole. A portion of the first wiring layer is exposed from a first opening formed in the first solder mask layer. The first electrical contact pads are disposed on the exposed portion of the first wiring layer. The top surface of the first electrical contact pads is higher than that of the first wiring layer to thereby allow a semiconductor chip to be mounted on the electrical contact pads for improving electrical connection. | 12-17-2009 |
Patent application number | Description | Published |
20140272681 | Extreme Ultraviolet Light (EUV) Photomasks, and Fabrication Methods Thereof - Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A planarized process is provided to remove the absorber layer above the top surface of the hard mask layer and form an absorber in the opening, wherein the absorber has a top portion wider than a bottom portion. | 09-18-2014 |
20150072519 | Metal and Via Definition Scheme - A method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is formed over the photoresist and the first dielectric layer. The spacer layer has an opening that has a via width. The opening is disposed directly above a via location. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer. | 03-12-2015 |
20150331307 | Extreme Ultraviolet Light (EUV) Photomasks and Fabrication Methods Thereof - Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A removing process is provided to form an absorber with a top surface lower than a top surface of the capping layer. | 11-19-2015 |
Patent application number | Description | Published |
20140147943 | Method for Determining Carrier Concentrations in Semiconductor Fins - A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance. | 05-29-2014 |
20140256105 | Self-Aligned Passivation of Active Regions - A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET). | 09-11-2014 |
20150021710 | Methods for Forming STI Regions in Integrated Circuits - A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface. | 01-22-2015 |
20150035017 | Contact Structure of Semiconductor Device - The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface; a fin structure extending upward from the substrate major surface, wherein the fin structure comprises a first fin, a second fin, and a third fin between the first fin and second fin; a first germanide over the first fin, wherein a first bottom surface of the first germanide has a first acute angle to the major surface; a second germanide over the second fin on a side of the third fin opposite to first germanide substantially mirror-symmetrical to each other; and a third germanide over the third fin, wherein a third bottom surface of the third germanide has a third acute angle to the major surface less than the first acute angle. | 02-05-2015 |
20150041918 | Self-Aligned Dual-Metal Silicide and Germanide Formation - A method includes growing an epitaxy semiconductor region at a major surface of a wafer. The epitaxy semiconductor region has an upward facing facet facing upwardly and a downward facing facet facing downwardly. The method further includes forming a first metal silicide layer contacting the upward facing facet, and forming a second metal silicide layer contacting the downward facing facet. The first metal silicide layer and the second metal silicide layer comprise different metals. | 02-12-2015 |
20150076499 | System and Method for Test Key Characterizing Wafer Processing State - Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group. | 03-19-2015 |
20150097239 | Passivation Structure of Fin Field Effect Transistor - A FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower fin portion comprising a first semiconductor material having a first lattice constant; an upper fin portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant; a middle fin portion comprising a third semiconductor material having a third lattice constant between the first lattice constant and the second lattice constant; and a passivation structure surrounding the fin structure comprising a lower passivation portion surrounding the lower fin portion comprising a first oxynitride of the first semiconductor material; an upper passivation portion surrounding the upper fin portion comprising a second oxynitride of the second semiconductor material; and a middle passivation portion surrounding the middle fin portion comprising a third oxynitride of the third semiconductor material. | 04-09-2015 |
20150102386 | Passivated and Faceted for Fin Field Effect Transistor - A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed. | 04-16-2015 |
20150179768 | Fin Structure of Semiconductor Device - The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising an upper portion comprising a first semiconductor material having a first lattice constant, wherein the upper portion comprises a first substantially vertical portion having a first width and a second substantially vertical portion having a second width less than the first width over the first substantially vertical portion; and a lower portion comprising a second semiconductor material having a second lattice constant less than the first lattice constant, wherein a top surface of the lower portion has a third width less than the first width; and a gate structure covering the second substantially vertical portion. | 06-25-2015 |
20150236016 | Contact Structure of Semiconductor Device - A method of fabricating a semiconductor device comprises forming a fin structure extending from a substrate, the fin structure comprising a first fin, a second fin, and a third fin between the first fin and the second fin. The method further comprises forming germanide over a first facet of the first fin, a second facet of the second fin, and a substantially planar surface of the third fin, wherein the first facet forms a first acute angle with a major surface of the substrate and is substantially mirror symmetric with the second facet, and wherein the substantially planar surface of the third fin forms a second acute angle smaller than the first acute angle with the major surface of the substrate. | 08-20-2015 |
20150287652 | Calculating Carrier Concentrations in Semiconductor Fins Using Probed Resistance - A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance. | 10-08-2015 |
20150340302 | Passivation Structure of Fin Field Effect Transistor - A FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower fin portion comprising a first semiconductor material having a first lattice constant; an upper fin portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant; a middle fin portion comprising a third semiconductor material having a third lattice constant between the first lattice constant and the second lattice constant; and a passivation structure surrounding the fin structure comprising a lower passivation portion surrounding the lower fin portion comprising a first oxynitride of the first semiconductor material; an upper passivation portion surrounding the upper fin portion comprising a second oxynitride of the second semiconductor material; and a middle passivation portion surrounding the middle fin portion comprising a third oxynitride of the third semiconductor material. | 11-26-2015 |
20160005825 | CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE - The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer. | 01-07-2016 |
Patent application number | Description | Published |
20130009319 | Apparatus and Methods for Forming Through Vias - Methods and apparatus for forming through vias in an integrated circuit package are disclosed. An apparatus is disclosed, having a substrate having one or more bond pad terminals for receiving electrical connections on at least one surface; an encapsulation layer covering the at least one surface of the substrate and having a first thickness; a plurality of through vias extending through the encapsulation layer and positioned in correspondence with at least one of the one or more bond pad terminals; conductor material disposed within the plurality of through vias to form electrical connectors within the plurality of through vias; and at least one external terminal disposed on a surface of the encapsulation layer, electrically coupled to one of the one or more bond pad terminals by an electrical connector in at least one of the plurality of through vias. Package arrangements and methods for the through vias are disclosed. | 01-10-2013 |
20130037950 | Multi-Chip Wafer Level Package - A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer. | 02-14-2013 |
20130040423 | Method of Multi-Chip Wafer Level Packaging - A method of multi-chip wafer level packaging comprises forming a reconfigured wafer using a plurality of photo-sensitive material layers. A plurality of semiconductor chips and wafers are embedded in the photo-sensitive material layers. Furthermore, a variety of through assembly vias are formed in the photo-sensitive material layers. Each semiconductor chip embedded in the photo-sensitive material layers is connected to input/output pads through connection paths formed by the through assembly vias. | 02-14-2013 |
20130207239 | Interconnect Crack Arrestor Structure and Methods - A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers. | 08-15-2013 |
20130241083 | Joint Structure for Substrates and Methods of Forming - Disclosed embodiments include wire joints and methods of forming wire joints that can enable realization of fine pitch joints and collapse control for various packages. A first embodiment is a structure comprising a first substrate, a second substrate, and a wire joint. The first substrate comprises a first bonding surface, and the second substrate comprises a second bonding surface. The first bonding surface is opposite and faces the second bonding surface. The wire joint is attached to and between the first bonding surface and the second bonding surface. | 09-19-2013 |
20130273698 | Methods for Forming Through Vias - Methods for forming through vias in an integrated circuit package are disclosed. A substrate having a first surface is covered with an encapsulation layer of uncured material; the method includes inserting an upper mold tool having a first plurality of pillars into the encapsulation layer to imprint through vias extending to the first surface of the substrate; curing the encapsulation layer and the through vias; removing the upper mold tool from the encapsulation layer; and disposing conductor material within the through vias to make electrical connectors within the through vias. In additional methods, a method for forming an encapsulation layer using an upper and lower mold tool to form through vias and a mold cavity is disclosed. | 10-17-2013 |
20140041918 | Looped Interconnect Structure - Disclosed herein is a system and method for mounting packages by forming one or more wire loop interconnects, optionally, with a wirebonder, and mounting the interconnects to a mounting pad on a first substrate. A first and second stud ball may each have at least one flat surface be disposed on a single mounting pad, and a wire having a bend region and forming a loop may be disposed between the stud balls. The stud balls may be formed from a deformed mouthing node formed on a wire. The loop may be mounted on a mounting pad on a first substrate and a second substrate may be mounted on the loop via a conductive material such as solder. | 02-13-2014 |
20140262470 | Metal Post Bonding Using Pre-Fabricated Metal Posts - A method includes forming a plurality of metal posts. The plurality of metal posts is interconnected to form a metal-post row by weak portions between neighboring ones of the plurality of metal posts. The weak portions include a same metal as the plurality of metal posts. A majority of each of the plurality of metal posts is separated from respective neighboring ones of the plurality of metal posts. An end portion of each of the plurality of metal posts is plated with a metal. The plurality of metal posts is disposed into a metal post-storage. The method further includes retrieving one of the metal posts from a metal-post storage, and bonding the one of the metal posts on a metal pad. | 09-18-2014 |
20140263583 | Two-Step Direct Bonding Processes and Tools for Performing the Same - A method includes placing a plurality of first package components over second package components, which are included in a third package component. First metal connectors in the first package components are aligned to respective second metal connectors of the second package components. After the plurality of first package components is placed, a metal-to-metal bonding is performed to bond the first metal connectors to the second metal connectors. | 09-18-2014 |
Patent application number | Description | Published |
20080258636 | LED DRIVER WITH CURRENT SINK CONTROL AND APPLICATIONS OF THE SAME G - A backlight system for use in an LCD display with a driver providing current sink control includes an LED array module, a current feedback circuit, and a current compensation circuit. The LED array module has N columns of LEDs and each LED column has M LEDs connected in serial, wherein the current feedback circuit includes N current feedback units and the current compensation circuit includes N current compensation units, both of the current feedback circuit and the current compensation circuit being electrically coupled to the LED array module. When the backlight system is in operation, a current passes through an LED column, a current feedback unit, and a current compensation unit to generate an output voltage that is used for comparison with a predetermined DC voltage, and the current is compensated based on the results of the comparison. | 10-23-2008 |
20090147029 | Multi-frame overdriving circuit and method and overdriving unit of liquid crystal display - A multi-frame overdriving circuit for use in a liquid crystal display including a counting unit and a multi-frame overdriving unit is provided. The counting unit counts a number m of frame periods for which a pixel data corresponding to a pixel keeps a first gray value, wherein m is a positive integer. When the pixel data changes to a second gray value from the first gray value in a first frame period, the multi-frame overdriving unit respectively outputs y multi-frame overdriving pixel data corresponding to the pixel within successive y frame periods starting from the first frame period. The y multi-frame overdriving pixel data are related to the first gray value, the second gray value and the number m of frame periods, wherein y is a positive integer. | 06-11-2009 |
20100045631 | MATRIX SENSING APPARATUS - A matrix sensing apparatus with architecture having reduced quantity of required sensing lines is disclosed. The matrix sensing apparatus includes a plurality of driving lines, a plurality of sensing lines and a matrix sensing region. The matrix sensing region includes a plurality of sensing areas. Each sensing area includes a first transistor, a second transistor, and a sensing unit for generating a sensing signal. The first transistor is coupled to the sensing unit and a corresponding sensing line. The second transistor is coupled to the first transistor, a first corresponding driving line and a second corresponding driving line. The first transistor together with the second transistor functions to control the signal connection between the sensing unit and the corresponding sensing line based on the driving signals of the first and second corresponding driving lines. | 02-25-2010 |
20140104260 | DRIVING DEVICE AND DISPLAY DEVICE AND METHOD FOR DRIVING DISPLAY PANEL - A driving device is configured for driving a display panel and includes a data driver, a plurality of switches, and an image determiner. The switch is electrically coupled between data lines of a first data line group. The data driver is configured to output data signals to the data lines of the first data line group. The data signals transferred by the data lines of the first data line group include a plurality of pulse transitions while the display panel displays an image. The image determiner is configured to determine the image displayed by the display panel and output a driving signal based on a determined result for activating a corresponding switch such that the data lines of the first data line group can perform charge sharing therebetween. Furthermore, a method for driving a display panel is disclosed herein. | 04-17-2014 |
20150109347 | CHARGE-SHARING CONTROLLING METHOD AND DISPLAY PANEL - A charge-sharing controlling method and a display panel are disclosed. The charge-sharing controlling method is suitable for the display panel including plural sub-pixels. The charge-sharing controlling method includes following steps: determining whether the display panel is displaying a primary color screen; if the display panel is displaying a primary color screen, prolonging an activated time of a charge-sharing circuit, which is coupled between any two of the sub-pixels displaying the same color, adjacent to each other and having opposite polarities. | 04-23-2015 |
Patent application number | Description | Published |
20100013016 | ESD Protection Structures on SOI Substrates - An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region. | 01-21-2010 |
20100097091 | Methodology for Bias Temperature Instability Test - A method for performing a bias temperature instability test on a device includes performing a first stress on the device. After the first stress, a first measurement is performed to determine a first parameter of the device. After the first measurement, a second stress is performed on the device, wherein only the first parameter is measured between the first stress and the second stress. The method further includes performing a second measurement to determine a second parameter of the device after the second stress. The second parameter is different from the first parameter. | 04-22-2010 |
20110254091 | ESD Protection Structures on SOI Substrates - An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region. | 10-20-2011 |
20130063175 | Semiconductor Device Components and Methods - Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end. | 03-14-2013 |
20140145194 | Semiconductor Device Components and Methods - Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end. | 05-29-2014 |
Patent application number | Description | Published |
20090046042 | Drive Method for Reducing the Power Consumption of a Flat Display - The present invention provides a method to reduce the power consumption. The method comprises these steps. First, the RGB gray levels of a pixel are decided. Then, the RGB gray level values are transformed to XYZ tristimulus values. The XYZ tristimulus values are transformed to L*a*b* values. Next, the L*′a*′b*′ values are determined based on an acceptable color difference range. The color difference between the L*′a*′b*′ and the L*a*b* is in the color difference range. Finally, the L*′a*′b*′ values are transformed to X′Y′Z′ values and the X′Y′Z′ values are transformed to R′G′B′ gray level values. | 02-19-2009 |
20100136221 | METHOD OF FABRICATING PIXEL STRUCTURE - A method of fabricating a pixel structure for use in an electroluminescent panel includes the following steps. A substrate is provided. Three shadow masks having a plurality of first, second, and third openings patterned in an array of T shaped are respectively provided, and three evaporation processes using the three shadow masks are subsequently performed to form a plurality of first subpixel units, second subpixel units and third subpixel units respectively. One first subpixel of the first subpixel unit, one second subpixel of the second subpixel unit adjacent to the first subpixel unit, and one third subpixel of the third subpixel unit adjacent to the first subpixel unit form a display pixel unit. | 06-03-2010 |
20130169170 | LIGHT EMITTING DIODE CIRCUITRY, METHOD FOR DRIVING LIGHT EMITTING DIODE CIRCUITRY AND DISPLAY - A light emitting diode circuitry includes a first transistor, a second transistor, a third transistor, a fourth transistor, a storage capacitor, a fifth transistor, a sixth transistor and light emitting diodes. The first transistor is used for receiving a first control signal. The second transistor is used for receiving a second control signal. The third transistor is electrically coupled to the second transistor and the first transistor. The fourth transistor is used for receiving a data signal and a third control signal. The storage capacitor is electrically coupled to the second transistor. The fifth transistor is used for receiving a fourth control signal. The sixth transistor is used for receiving a fifth control signal. The light emitting diodes are coupled to the sixth transistor and a power source. | 07-04-2013 |
20130328848 | PIXEL DRIVING CIRCUIT, DRIVING METHOD THEREOF AND DISPLAY PANEL - A pixel driving circuit includes a first switch, a capacitor, a second switch and at least one organic light emitting diode. The first switch includes a first end for receiving data voltage, a control end for receiving a first scan signal, and a second end for outputting the data voltage. The capacitor includes a first end coupled to the second end of the first switch, and a second end. The second switch includes a first end coupled to the second end of the first switch, a control end for receiving a second scan signal, and a second end. The at least one organic light emitting diode includes a first end coupled to the second end of the second switch, and a second end coupled to the second end of the capacitor. | 12-12-2013 |