Patent application number | Description | Published |
20090279655 | FAST LOCKING CLOCK AND DATA RECOVERY - A clock data recovery comprises a phase detector, a phase interpolator, an initial phase detector, and an initial phase decoder. The phase detector receives an incoming data stream and an interpolated clock signal and output an early/late value indicating timing relationship between the incoming data stream and the interpolated clock signal. The phase interpolator receives the early/late signal and at least one reference clock signal and generate an interpolated clock signal considering the early/late value and the at least one reference clock signal. The initial phase detector receives the incoming data stream and output a first data indicating a phase of the incoming data stream. The initial phase decoder receives data indicating a phase of the incoming data stream and select the at least one reference clock signal from a plurality of clock signals considering the data indicating a phase of the incoming data stream. | 11-12-2009 |
20100054385 | ADAPTIVE ELASTIC BUFFER FOR COMMUNICATIONS - Circuit and method for an adaptive elastic buffer for receiving data including timing signals. Received data is recovered and stored in the adaptive elastic buffer, and a recovery clock pointer is increased to identify the next buffer location for stuffing received data, responsive to a controller. When a data fetch enable condition occurs, the controller causes a receiver circuit to fetch the data stored at a location identified by a system clock pointer. Underflow and overflow conditions are detected and the controller adapts the effective elastic buffer depth to compensate for these conditions. A buffer of M/2 physical locations is adaptively operated to provide a data buffer of M virtual locations. A method of buffering received data with a buffer having M/2 physical locations so as to provide the benefit of a buffer with M virtual locations is disclosed. | 03-04-2010 |
20100098203 | DIGITAL PHASE INTERPOLATION CONTROL FOR CLOCK AND DATA RECOVERY CIRCUIT - This invention discloses a phase interpolation controller for a clock and data recovery circuit receiving an indication of a phase relationship between a first and a second signal, the phase interpolation controller comprises a plurality of serially coupled bi-directional shift-registers, wherein when the received indication indicates the first signal is ahead of the second signal in phase, the plurality of serially coupled bi-directional shift-registers shifts in one of the bi-directions, and when the received indication indicates the first signal is behind the second signal in phase, the plurality of serially coupled bi-directional shift-registers shifts in the other of the bi-directions. | 04-22-2010 |
20110199121 | SMART EDGE DETECTOR - In some embodiments related to a smart edge detector, the smart edge detector uses a second clock in a receiver domain (e.g., clock CLK_D | 08-18-2011 |
20120066559 | Built-in Bit Error Rate Test Circuit - System and method for testing jitter tolerance by using a built-in jitter modulation circuit is disclosed. An embodiment comprises a jitter modulation circuit, a transmitter, a receiver and a data comparison unit. The jitter modulation circuit includes a plurality of data latches, a phase-select block and a multi-phase clock generator. The multi-phase clock generator is capable of generating a plurality of signals having different phase shifts wherein one signal having a phase shift from the system clock signal is selected by the phase-select block. The selected signal alters the data by injecting jitter through a plurality of data latches. The jitter-contaminated data is transmitted to a data comparison unit through a transmitter and a receiver. The on-chip test circuit compares the jitter-contaminated data with the original data and calculates the bit error rate so as to determine whether the jitter tolerance of this semiconductor device satisfies the specification. | 03-15-2012 |
20120169361 | BUILT IN SELF TEST FOR TRANSCEIVER - An integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other. | 07-05-2012 |
20120212866 | OUTPUT DRIVER - An output driver having a power supply line, a control switch, at least one protection device and at least one voltage clamp device. The control switch disposed between the at least one protection device and the power supply line an output line. The at least one protection device disposed in a series arrangement between the output line and the control switch. The at least one voltage clamp device disposed across a corresponding protection device and adapted to clamp a voltage across the protection device below a predetermined threshold voltage. | 08-23-2012 |
20120229198 | POWER SUPPLY REGULATOR - Power supply regulators, integrated circuits including a power supply regulator, and methods of regulating a power supply are provided. In one embodiment, a power supply regulator includes a first self-bias circuit configured to receive a supply voltage from a power supply, a second self-bias circuit coupled to a reference voltage, and a clamping circuit coupled between the first and second self-bias circuits. The clamping circuit includes a NMOS transistor coupled to the first self-bias circuit and a PMOS transistor coupled to the second self-bias circuit. The clamping circuit is further configured to generate an output voltage less than the supply voltage at substantially the same time as when the supply voltage is received from the power supply. | 09-13-2012 |
20120280718 | SMART EDGE DETECTOR - This description relates to an edge detector including a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels. The edge detector further includes a first RC circuit configured to charge the first pulse and a second RC circuit configured to charge the second pulse. The edge detector further includes a circuitry that, based on a width of the first pulse or of the second pulse, is configured to provide a select signal to select an edge of the second clock for triggering. | 11-08-2012 |
20150054667 | Time-to-Digital Converter and Related Method - A device includes a delay line, a first readout circuit electrically connected to the delay line, a second readout circuit electrically connected to the delay line, and a phase interpolator electrically connected to the second readout circuit. | 02-26-2015 |