Patent application number | Description | Published |
20090000106 | METHOD OF FORMING VERTICAL COUPLING STRUCTURE FOR NON-ADJACENT RESONATORS - A method for forming a vertical coupling structure for non-adjacent resonators is provided to have a first and a second resonators, a dielectric material layer, a first and a second high-frequency transmission lines and at least one via pole. The first and the second resonators respectively have a first and a second opposite metal surfaces. The dielectric material layer is disposed between the opposite second metal surfaces of the first and the second resonators. The first and the second transmission lines are respectively arranged at sides of the first metal surfaces of the first resonator and the second resonator. The first high-frequency transmission line is vertically connected to the second high-frequency transmission line by the via pole. | 01-01-2009 |
20090002104 | VERTICAL COUPLING STRUCTURE FOR NON-ADJACENT RESONATORS - A vertical coupling structure for non-adjacent resonators is provided to have a first and a second resonators, a dielectric material layer, a first and a second high-frequency transmission lines and at least one via pole. The first and the second resonators respectively have a first and a second opposite metal surfaces. The dielectric material layer is disposed between the opposite second metal surfaces of the first and the second resonators. The first and the second transmission lines are respectively arranged at sides of the first metal surfaces of the first resonator and the second resonator. The first high-frequency transmission line is vertically connected to the second high-frequency transmission line by the via pole. | 01-01-2009 |
20090045890 | FILTERING CIRCUIT AND STRUCTURE THEREOF - A filtering circuit and a structure thereof are provided. The filtering circuit includes an input terminal, an output terminal, a resonant circuit, a first coupling portion, and a second coupling portion. The resonant circuit is coupled between the input terminal and the output terminal and includes M resonators which are arranged in sequence. A signal received by the input terminal can be transmitted to the output terminal by the resonant circuit through inter-coupling between adjacent resonators. The first coupling portion and the second coupling portion are respectively coupled to non-adjacent resonators. A part of the signal received by the input terminal is transmitted to the second coupling portion via the first coupling portion through cross-couple. Thereby, sideband interference can be further suppressed. | 02-19-2009 |
20100117768 | VERTICAL COUPLING STRUCTURE FOR NON-ADJACENT RESONATORS - A vertical coupling structure for non-adjacent resonators is provided. The vertical coupling structure has a first resonator and a second resonator. At least one side of the first resonator is formed as a first bent extension structure, and the first bent extension structure includes a slot. The second resonator is not adjacent to the first resonator, and the side of the second resonator opposite to the first bent extension structure of the first resonator further includes a slot, such that the two sides are electrically connected. | 05-13-2010 |
Patent application number | Description | Published |
20130103331 | ELECTRICITY CONSUMPTION MEASUREMENT APPARATUS, ELECTRICITY CONSUMPTION MEASUREMENT METHOD, AND NON-TRANSITORY TANGIBLE MACHINE-READABLE MEDIUM THEREOF - An electricity consumption measurement apparatus, an electricity consumption measurement method, and a non-transitory tangible machine-readable medium thereof are provided. The electricity consumption measurement apparatus comprises a detector and a processor electrically connected to the detector. The detector is configured to detect an electricity consumption value and a voltage value. The processor is configured to calculate a variation rate according to the voltage value and a base voltage value. The processor adjusts the electricity consumption value according to the variation rate. The electricity consumption measurement method is able to perform the same operations as those performed by the electricity consumption measurement apparatus. | 04-25-2013 |
20130158910 | ELECTRIC POWER MONITOR DEVICE - An electric power monitor device is provided. The electric power monitor device is electrically connected to an alternating current source which supplies electric power to a plurality of under-test current loops. The electric power monitor device comprises a voltage input interface, a voltage measuring unit, a plurality of current measuring components and a processing unit. The voltage input interface is configured to receive an input power source from the alternating current source. The voltage measuring unit is configured to generate voltage values based on the input power source. The current measuring components are capable of adjusting phase configuration based on different phases of the wires of the current loops, and are configured to determine current values of the current loops. The processing unit is configured to calculate an electric power monitor value according to the voltage values and the current values. | 06-20-2013 |
20140067290 | STREETLAMP FAULT DETECTION APPARATUS AND STREETLAMP FAULT DETECTION METHOD THEREOF - A streetlamp fault detection apparatus and a streetlamp fault detection method thereof are provided. The streetlamp fault detection apparatus is coupled to a streetlamp loop, and stores an impedance condition table defining a reference impedance range and a non-reference impedance range. The streetlamp fault detection apparatus measures a total impedance value of the streetlamp loop in a measurement period, determines that the streetlamp loop is in a normal operating state if the total impedance value stably falls within the reference impedance range in the measurement period, and determines that the streetlamp loop is in a fault state if the total impedance value falls into the non-reference impedance range in the measurement period. | 03-06-2014 |
20140145866 | DATA PROCESSING APPARATUS AND METHOD - A data processing apparatus and a data processing method thereof are provided. The data processing apparatus includes a register and a processor electrically connected to the register. The register is stored with a plurality of data. The plurality of data each includes a first sub-datum and a second sub-datum. The plurality of first sub-data corresponds to a first column and the plurality of second sub-data corresponds to a second column. The processor compresses the first sub-data by a first compression algorithm according to a first characteristic of the plurality of first sub-data and compresses the second sub-data by a second compression algorithm according to a second characteristic of the plurality of second sub-data. | 05-29-2014 |
20140164599 | WORKLOAD DISPATCH DEVICE AND WORKLOAD DISPATCH METHOD THEREOF - A workload dispatch device and a workload dispatch method thereof are provided. The workload dispatch device comprises a monitor, a processor and a dispatcher. The monitor is configured to monitor operating conditions of a plurality of servers. The processor is electrically connected to the monitor and configured to execute the following operations: creating an average performance index table for a plurality of algorithms according to the operating conditions of the servers; normalizing the average performance index table; calculating a benchmark for each of the algorithms according to the normalized performance index table and a corresponding weighting table; and choosing a candidate algorithm from the algorithms according to the benchmarks. The dispatcher is electrically connected to the processor and configured to dispatch a workload to the plurality of servers according to the candidate algorithm. | 06-12-2014 |
Patent application number | Description | Published |
20120199966 | Elongated Bump Structure for Semiconductor Devices - An elongated bump structure for semiconductor devices is provided. An uppermost protective layer has an opening formed therethrough. A pillar is formed within the opening and extending over at least a portion of the uppermost protective layer. The portion extending over the uppermost protective layer exhibits a generally elongated shape. In an embodiment, the position of the opening relative to the portion of the bump structure extending over the uppermost protective layer is such that a ratio of a distance from an edge of the opening to an edge of the bump is greater than or equal to about 0.2. In another embodiment, the position of the opening is offset relative to center of the bump. | 08-09-2012 |
20120329264 | Reflow System and Method for Conductive Connections - A system and method for forming conductive connections is disclosed. An embodiment comprises forming conductive material on to contacts of a semiconductor substrate. The semiconductor substrate is then inverter such that the conductive material is beneath the semiconductor substrate, and the conductive material is reflowed to form a conductive bump. The reflow is performed using gravity in order to form a more uniform shape for the conductive bump. | 12-27-2012 |
20130026622 | BUMP STRUCTURES IN SEMICONDUCTOR DEVICE AND PACKAGING ASSEMBLY - A bump structure in a semiconductor device or a packing assembly includes an under-bump metallization (UBM) layer formed on a conductive pad of a semiconductor substrate. The UBM layer has a width greater than a width of the conductive pad. | 01-31-2013 |
20130043583 | Dummy Flip Chip Bumps for Reducing Stress - A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. | 02-21-2013 |
20130056872 | Packaging and Function Tests for Package-on-Package and System-in-Package Structures - A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls. | 03-07-2013 |
20130062755 | ELONGATED BUMP STRUCTURE IN SEMICONDUCTOR DEVICE - A device includes a chip attached to a substrate. The chip includes a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a conductive trace and a mask layer overlying the conductive trace, wherein the mask layer has an opening exposing a portion of the conductive trace. An interconnection is formed between the conductive pillar and the exposed portion of the conductive trace. The opening has a first dimension (d | 03-14-2013 |
20130075872 | Metal Pad Structures in Dies - A die includes a substrate, a metal pad over the substrate, and a passivation layer that has a portion over the metal pad. A dummy pattern is disposed adjacent to the metal pad. The dummy pattern is level with, and is formed of a same material as, the metal pad. The dummy pattern forms at least a partial ring surrounding at least a third of the metal pad. | 03-28-2013 |
20130093075 | Semiconductor Device Package and Method - An embodiment is a structure. The structure comprises a substrate, a chip, and a reinforcement component. The substrate has a first surface, and the first surface comprises depressions. The chip is over and attached to the first surface of the substrate. The reinforcement component is over a first area of the first surface of the substrate. The first area is not under the chip. The reinforcement component has a portion disposed in at least some of the depressions in the first area. | 04-18-2013 |
20130320524 | Design Scheme for Connector Site Spacing and Resulting Structures - A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. | 12-05-2013 |
20140035148 | Bump on Pad (BOP) Bonding structure - The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints. | 02-06-2014 |
20140048929 | Bonded Structures for Package and Substrate - The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. | 02-20-2014 |
20140070402 | Stress Reduction Apparatus - A structure comprises a plurality of connectors formed on a top surface of a first semiconductor die, a second semiconductor die formed on the first semiconductor die and coupled to the first semiconductor die through the plurality of connectors and a first dummy conductive plane formed between an edge of the first semiconductor die and the plurality of connectors, wherein an edge of the first dummy conductive plane and a first distance to neutral point (DNP) direction form a first angle, and wherein the first angle is less than or equal to 45 degrees. | 03-13-2014 |
20140117532 | Bump Interconnection Ratio for Robust CPI Window - The disclosure is directed to a device and method for manufacture thereof. The device includes a first workpiece bonded to a second workpiece by a bump interconnection structure. The bump interconnection structure allows for optimized packaging assembly yield and bond integrity. | 05-01-2014 |
20140124947 | Methods and Apparatus for Flip Chip Substrate with Guard Rings Outside of a Die Attach Region - Methods and apparatus for flip chip substrates with guard rings. An embodiment comprises a substrate core with a die attach region for attaching an integrated circuit die; at least one dielectric layer overlying a die side surface of the substrate core; and at least one guard ring formed adjacent a corner of the substrate core, the at least one guard ring comprising: a first trace overlying the dielectric layer having rectangular portions extending in two directions from the corner of the substrate core and in parallel to the edges of the substrate core; a second trace underlying the dielectric layer; and at least one via extending through the dielectric layer and coupling the first and second traces; wherein the first trace, the at least one via, and the second trace form a vertical via stack. Methods for forming the flip chip substrates with the guard rings are disclosed. | 05-08-2014 |
20140159203 | Substrate Pad Structure - A structure comprises a first pad protruding over a top surface of a package substrate, wherein the first pad is of a first elongated shape, a second pad embedded in the package substrate, wherein the second pad is of a second elongated shape and a via coupled between the first pad and the second pad. | 06-12-2014 |
20140191390 | Metal Routing Architecture for Integrated Circuits - A device includes a substrate, a metal pad over the substrate, and a metal trace electrically disconnected from the metal pad. The metal pad and the metal trace are level with each other. A passivation layer includes a portion overlapping an edge portion of the metal pad. A metal pillar is overlying the metal pad, and is electrically connected to the metal pad. The metal trace has a portion overlapped by the metal pillar. | 07-10-2014 |
20140191391 | ELONGATED BUMP STRUCTURES IN PACKAGE STRUCTURE - A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2. | 07-10-2014 |
20140248722 | Packaging and Function Tests for Package-on-Package and System-in-Package Structures - A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls. | 09-04-2014 |
20140377946 | Bonded Structures for Package and Substrate - The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. | 12-25-2014 |
Patent application number | Description | Published |
20150018120 | TWO-PIECE TYPE GOLF CLUB HEAD - A two-piece type gold club head includes a body member including a top wall, a neck located at one end of the top wall, a peripheral wall extended from the ring-shaped border area of the top wall toward one lateral side and defining a planar ball-hitting surface, a bottom wall extended from the bottom side of the planar ball-hitting surface and terminating in a bottom flange and a top flange extended from the peripheral wall and integrally connected with the bottom flange to form an annular flange, and a bottom member mounted at the bottom side of the peripheral wall of the body member and having a mounting flange lap-connected with the top flange of the body member. | 01-15-2015 |
20150018121 | GOLF CLUB HEAD HAVING AN ELASTIC BALL-HITTING FACE - A gold club head includes a club head body having an opening defined in a front side thereof, a flange extending around the opening and a tubular neck located at one lateral side thereof, and a cover shell mounted in the opening of the club head body and having a peripheral wall extended around the border area of a face panel thereof and a substantially annular mounting flange extended from a distal end of the peripheral wall and connected to the flange of the club head body. | 01-15-2015 |
20150057098 | GOLF CLUB HEAD - A gold club head includes a club head body defining a mounting surface, a spacer member including a top surface, an opposing bottom surface fixedly connected to the mounting surface of the club head body, and a face panel including a ball-hitting surface, and opposing bottom bonding surface fixedly connected to the top surface of the spacer member and a plurality of upper grooves curved inwardly in direction from the ball-hitting surface toward bottom bonding surface. Thus, the golf club head has better elasticity capable of extending the staying time of the ball in the ball-hitting surface. | 02-26-2015 |
Patent application number | Description | Published |
20110207550 | Method for Surface Treating a Golf Club Head - A method for surface treating a golf club head, includes: (a) forming a depression unit in the golf club head, the depression unit being indented inwardly from an outer surface of the golf club head, the outer surface being divided into a working area and a non-working area, the depression unit being formed in the working area; (b) filling the depression unit with a shielding material and covering the non-working area with a covering material; and (c) sandblasting the golf club head after step (b) and removing subsequently the shielding material from the depression unit and the covering material from the non-working area so as to form the working area into sandblasted and non-sandblasted regions that differ in gloss intensity. | 08-25-2011 |
20120304451 | METHOD FOR SURFACE TREATING A GOLF CLUB HEAD - A method for surface treating a golf club head, includes: (a) forming a depression unit in the golf club head, the depression unit being indented inwardly from an outer surface of the golf club head, the outer surface being divided into a working area and a non-working area, the depression unit being formed in the working area; (b) filling the depression unit with a shielding material and covering the non-working area with a covering material; and (c) sandblasting the golf club head after step (b) and removing subsequently the shielding material from the depression unit and the covering material from the non-working area so as to form the working area into sandblasted and non-sandblasted regions that differ in gloss intensity. | 12-06-2012 |
20140053391 | METHOD FOR SURFACE TREATING A GOLF CLUB HEAD - A method for surface treating a golf club head, includes: (a) forming a depression unit in the golf club head, the depression unit being indented inwardly from an outer surface of the golf club head, the outer surface being divided into a working area and a non-working area, the depression unit being formed in the working area; (b) filling the depression unit with a shielding material and covering the non-working area with a covering material; and (c) sandblasting the golf club head after step (b) and removing subsequently the shielding material from the depression unit and the covering material from the non-working area so as to form the working area into sandblasted and non-sandblasted regions that differ in gloss intensity. | 02-27-2014 |
20140310946 | METHOD FOR SURFACE TREATING A GOLF CLUB HEAD - A method for surface treating a golf club head, includes: (a) forming a depression unit in the golf club head, the depression unit being indented inwardly from an outer surface of the golf club head, the outer surface being divided into a working area and a non-working area, the depression unit being formed in the working area; (b) filling the depression unit with a shielding material and covering the non-working area with a covering material; and (c) sandblasting the golf club head after step (b) and removing subsequently the shielding material from the depression unit and the covering material from the non-working area so as to form the working area into sandblasted and non-sandblasted regions that differ in gloss intensity. | 10-23-2014 |
Patent application number | Description | Published |
20080260085 | Method and device for estimating integer carrier frequency offset - The method disclosed in the invention comprises setting a plurality of subcarrier position hypotheses for a received preamble according to a plurality of ideal subcarrier positions and the maximum amount of integer carrier frequency offset (ICFO), generating a plurality of preamble pattern hypotheses by retrieving the received preamble according to the subcarrier position hypotheses, calculating the correlation between the preamble pattern hypotheses and a plurality of specified preamble patterns, determining to which sector the received preamble belongs according to a correct preamble pattern, the specified preamble pattern having the highest correlation with the preamble pattern hypotheses, obtaining a correct subcarrier position according to the sector to which the received preamble belongs; and estimating the ICFO by calculating the offset between the correct subcarrier position and the subcarrier position hypothesis of the preamble pattern hypothesis having the highest correlation with the correct preamble pattern. | 10-23-2008 |
20080310525 | FFT-size detector and FFT-size detection method and cell search apparatus and cell search method in cellular system - An apparatus and method for cell acquisition and downlink synchronization acquisition in an OFDMA wireless communication system are provided. In an SS apparatus in a broadband wireless communication system, a preamble subcarrier acquirer extracts subcarrier values having a preamble code from an FFT signal. A multiplier code-demodulates the subcarrier values by multiplying the subcarrier values by a preamble code. A correlator calculates a plurality of differential correlations in the code-demodulated signal. An IFFT processor IFFT-processes the differential correlations by mapping the differential correlations to subcarriers. A maximum value detector detects a maximum value from the IFFT signal and calculates a timing offset using an IFFT output index having the maximum value. | 12-18-2008 |
20100056082 | COMMUNICATION SYSTEM WITH FREQUENCY-ADAPTIVE PREDISTORTER DESIGN - A communication system comprises a predistorter for distorting an input signal according to at least one parameter to generate a distorted signal, an amplifier for amplifying the distorted signal according to an input-output characteristic to generate an output signal, and a frequency-domain adaptive calibration module for adaptively adjusting the parameter of the predistorter according to a frequency characteristic of the output signal. Because the calibration is performed in the frequency domain, there is no need to precisely estimate the group delay formed by the feedback path. The system complexity is therefore reduced without loss of performance. | 03-04-2010 |
20110164568 | FFT-SIZE DETECTOR AND FFT-SIZE DETECTION METHOD AND CELL SEARCH APPARATUS AND CELL SEARCH METHOD IN CELLULAR SYSTEM - An apparatus and method for cell acquisition and downlink synchronization acquisition in an OFDMA wireless communication system are provided. In an SS apparatus in a broadband wireless communication system, a preamble subcarrier acquirer extracts subcarrier values having a preamble code from an FFT signal. A multiplier code-demodulates the subcarrier values by multiplying the subcarrier values by a preamble code. A correlator calculates a plurality of differential correlations in the code-demodulated signal. An IFFT processor IFFT-processes the differential correlations by mapping the differential correlations to subcarriers. A maximum value detector detects a maximum value from the IFFT signal and calculates a timing offset using an IFFT output index having the maximum value. | 07-07-2011 |
20140010156 | Method and Wireless Device for Antenna Selection - A transmission method for a wireless device is disclosed. The wireless device has a plurality of antennas. The transmission method includes determining a first set of the plurality of antennas, determining a second set of the plurality of antennas, transmitting a packet to a first client using the first set of the plurality of antennas; and transmitting a packet to a second client using the second set of the plurality of antennas. | 01-09-2014 |
Patent application number | Description | Published |
20090267210 | INTEGRATED CIRCUIT PACKAGE AND MANUFACTURING METHOD THEREOF - An integrated circuit package and a manufacturing method thereof are provided. The package includes a die pad, a plurality of first and second contact pads, a first die, a second die and a molding compound. The contact pads adjacent to at least one side of the die pad are arranged along an inner row and an outer row with respect to the die pad. The first die is fixed on the first die and electrically connected to the first contact pads by wire-bonding. The second die is fixed on the first die and electrically connected to the second contact pads by wire-bonding. The molding compound covers the second die, the first die, the die pad, the first contact pads and the second contact pads. The bottoms of the die pad, the first contact pads and the second contact pads are exposed at the bottom surface of the molding compound. | 10-29-2009 |
20090278242 | STACKED TYPE CHIP PACKAGE STRUCTURE - A stacked type chip package structure including a lead frame, a chip package, a second chip, and a second molding compound is provided. The lead frame includes a plurality of first leads and second leads insulated from one another. The first leads have a first upper surface, and the second leads have a second upper surface which is not co-planar with the first upper surface. The chip package is disposed on the first leads and includes a substrate, a first chip, and a first molding compound. The second chip is stacked on the chip package and electrically connected to the second leads. The second molding compound is disposed on the lead frame and filled among the first leads and the second leads for encapsulating the chip package and the second chip. | 11-12-2009 |
20090278243 | STACKED TYPE CHIP PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A stacked type chip package structure including a chip carrier, a first chip, a second chip, a third chip, and an insulating material is provided. The chip carrier includes two die pads and a plurality of leads surrounding the die pads. The first chip and the second chip are disposed on the die pads respectively, and are electrically connected to the leads by wire bonding. The third chip traverses the first chip and the second chip, and is electrically connected to the first chip and the second chip respectively. The insulating material is disposed on the chip carrier for encapsulating the first chip, the second chip and the third chip, and fills among the die pads and the leads. | 11-12-2009 |
Patent application number | Description | Published |
20090279247 | HEAT DISSIPATION DEVICE OF NOTEBOOK COMPUTER - A heat dissipation device is provided for dissipating heat from a heat source inside a notebook computer, and includes a hood, a bottom board, a thermal insulation layer, and at least one fan. The hood and the bottom board together define a heat dissipation channel. The bottom board integrally forms a plurality of fins and pegs. The bottom board is set above the heat source. The fan is set above the bottom board to efficiently expel heat from the inside to the outside. With the plurality of fins and pegs, the heat dissipation surface area of the bottom board and the heat source is increased and the overall heat dissipation performance is enhanced. | 11-12-2009 |
20100091497 | LIGHT-EMITTING DIODE LIGHTING DEVICE WITH MULTIPLE-LAYERED SOURCE - A lighting device includes a cover, a cap, a central post having opposite ends coupled to the cover and the cap respectively, and a plurality of first and second frames. The cover and the cap both form a plurality of circumferentially distributed slots opposite to each other. The first and second frames have ends respectively fit into the slots of the cover and the cap and each frame carries at least one light-emitting diode. As such, a light-emitting diode lighting device that is hollow, light-weighted, and exhibiting excellent heat dissipation is formed. | 04-15-2010 |
20100157608 | STRUCTURE OF LIGHT-EMITTING DIODE LIGHTING TUBE - A light-emitting diode lighting tube includes a casing, an aluminum base board, which is fit into the casing and carries a plurality of light-emitting diodes, at least two reflective members respectively arranged on opposite sides of the light-emitting diodes, and first and second end caps respectively mounted to opposite ends of the casing. The casing has a radial cross-section forming an opening extending in an axial direction of the casing. The aluminum base board is fit to retention sections formed beside the opening. The two reflective members are arranged on opposite sides of the LEDs for reflecting lights emitting from the LEDs. | 06-24-2010 |
20110169392 | LED PROJECTION LAMP - A light emitting diode (LED) projection lamp includes a lamp body and a plurality of LEDs. The lamp body includes an inverted conical shaped external cover, an electric contact base formed at the tip of the external cover, and a plurality of protrusions arranged on an internal wall of the external cover with a circular distribution, and each protrusion has at least one fixing surface. The LEDs are installed separately on each fixing surface, and an inclination is formed between lights emitted by the LEDs and a projection plane for reducing reflective lights, and the LEDs are electrically coupled to the electric contact base, such that heat produced by using the LEDs is conducted directly to the external cover for its dissipation to improve the heat dissipating efficiency and lifespan of the lamp, and the angular arrangement of the LEDs also improves the saturation and reflection of the light. | 07-14-2011 |
20130215615 | LATERALLY INSTALLABLE ROTATING LAMP - A laterally installable rotating lamp includes a main body, a plurality of LED light sources, a transparent cover and an electric connector. The main body includes an air flow channel disposed on one side of the main body and the LED light sources disposed on the other side of the main body, and the transparent cover covers the LED light sources, and the electric connector is installed at an end of the main body through a connecting portion and electrically coupled to the LED light sources. The air flow channel is provided for quickly dissipating the heat produced by the LED light sources to prevent a light attenuation of the LED light sources caused by the thermal interference, and a reduced service life. In addition, the connecting portion can be rotated to adjust the illumination angle or the lamp. | 08-22-2013 |
20140071678 | LED LIGHT BULB STRUCTURE - A LED light bulb structure has a base body, a control circuit board, a housing, at least a LED light source and a cover body. The base body is connected to the housing to form a containing space for disposing the control circuit board. The housing is disposed with a mounting portion that is inclined toward the housing to dispose the LED light source. Since the mounting potion is inclined, the illumination range of light beam of the LED light source is increased to provide wider illumination range without affecting the brightness of the LED light bulb structure, wherein the housing is integrally formed and disposed with a plurality of gutters at its outer surface to enhance heat dissipation effect, and integrated formation can also simplify the manufacture process and save the assembly time. | 03-13-2014 |