Patent application number | Description | Published |
20090278132 | ARRAY SUBSTRATE OF LIQUID CRYSTAL DISPLAY DEVICE HAVING THIN FILM TRANSISTOR ON COLOR FILTER AND METHOD OF FABRICATING THE SAME - An array substrate of a liquid crystal display device having a color filter on a gate metal layer, and a data metal layer formed on the color filter. First a gate insulating layer is formed on the gate metal layer to protect and a second gate insulating layer is formed on the color filter layer. Gate lines and gate electrodes are formed in direct contact with the substrate, and color filters are formed on the gate electrodes. To protect gate lines in the patterning process of color filters, a first gate insulating layer is formed on the gate lines and electrodes. Therefore, a high aperture ratio may be enhanced, and the manufacturing yield may be increased. | 11-12-2009 |
20100032664 | THIN FILM TRANSISTOR SUBSTRATE AND A FABRICATING METHOD THEREOF - An oxide semiconductor thin film transistor substrate includes a gate line and a gate electrode disposed on an insulating substrate, an oxide semiconductor pattern disposed adjacent to the gate electrode, a data line electrically insulated from the gate line, the data line and the gate line defining a display region, a first opening exposing a surface of the data line, a second opening exposing a surface of the oxide semiconductor pattern, and a drain electrode disposed on the first opening and a drain electrode pad, the drain electrode extending from the first opening to the second opening and electrically connecting the drain electrode pad and the oxide semiconductor pattern. | 02-11-2010 |
20100053507 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME - After increasing the thickness of a gate line and forming a barrier rib that is made of an organic material, a gate insulating layer is formed and then a color filter is formed with an Inkjet method using the barrier rib. By increasing a thickness of the gate line, even if the size of a substrate increases, problems due to signal delay are reduced, and by forming a barrier rib with an organic material, the height of the barrier rib increases, and a taper angle increases and thus a color filter is stably formed. | 03-04-2010 |
20100140610 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other. | 06-10-2010 |
20100182068 | METHOD AND APPARATUS FOR ACCOUNTING FOR CHANGES IN TRANSISTOR CHARACTERISTICS - A device for accounting for changes in characteristics of a transistor is presented. The device includes a transistor and a comparator receiving a feedback signal from the transistor and a reference signal. The comparator provides an output to a bias voltage generator. The bias voltage generator includes an input connected to the output of the comparator and an output connected to the transistor. In some embodiments of the invention the transistor is a double gate transistor and the bias voltage generator is applied to a top gate of the double gate transistor in order to control characteristics of the transistor such as turn on voltage. | 07-22-2010 |
20110089421 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line. | 04-21-2011 |
20110108839 | Thin Film Transistor Substrate and Manufacturing Method Thereof - A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material. | 05-12-2011 |
20120193634 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other. | 08-02-2012 |
20130001567 | THIN FILM TRANSISTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material. | 01-03-2013 |
20130149814 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other. | 06-13-2013 |
Patent application number | Description | Published |
20110133193 | THIN FILM TRANSISTOR SUBSTRATE AND THE METHOD THEREOF - A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape. | 06-09-2011 |
20110140111 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor array panel is provided and includes a gate line, a gate insulating layer covering the gate line, a semiconductor layer disposed on the gate insulating layer, and a data line and a drain electrode disposed on the semiconductor layer. The data line and the drain electrode have a dual-layered structure including a lower layer and an upper layer with the lower layer having a first portion protruded outside the upper layer and the semiconductor layer having a second portion protruded outside the edge of the lower layer. | 06-16-2011 |
20110175088 | Thin-Film Transistor Substrate and Method of Fabricating the Same - A thin-film transistor (TFT) substrate having reduced defects is fabricated using a reduced number of masks. The TFT substrate includes gate wiring formed on a substrate. The gate wiring includes a gate electrode. A semiconductor pattern is formed on the gate wiring. An etch-stop pattern is formed on the semiconductor pattern. Data wiring includes a source electrode which is formed on the semiconductor pattern and the etch-stop pattern. Each of the gate wiring and the data wiring includes a copper-containing layer and a buffer layer formed on or under the copper-containing layer. | 07-21-2011 |
20110186843 | Manufacturing method of thin film and metal line for display using the same, thin film transistor array panel, and method for manufacturing the same - A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of approximately 1.5 to approximately 3 W/cm | 08-04-2011 |
20110226727 | ETCHANT FOR METAL WIRING AND METHOD FOR MANUFACTURING METAL WIRING USING THE SAME - Exemplary embodiments of the present invention provide a metal wiring etchant. A metal wiring etchant according to an exemplary embodiment of the present invention includes ammonium persulfate, an organic acid, an ammonium salt, a fluorine-containing compound, a glycol-based compound, and an azole-based compound. | 09-22-2011 |
20110269309 | PHOTORESIST COMPOSITION, METHOD OF FORMING PATTERN BY USING THE PHOTORESIST COMPOSITION, AND METHOD OF MANUFACTURING THIN-FILM TRANSISTOR SUBSTRATE - Provided are a photoresist composition having superior adhesion to an etch target film, a method of forming a pattern by using the photoresist composition, and a method of manufacturing a thin-film transistor (TFT) substrate. The photoresist composition includes an alkali-soluble resin; a photosensitive compound; a solvent; and 0.01 to 0.1 parts by weight of a compound represented by Formula 1: | 11-03-2011 |
20120028421 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL - A method for manufacturing a thin film transistor array panel includes forming a gate line; forming an insulating layer on the gate line; forming first and second silicon layers first and second metal layers; forming a photoresist pattern having first and second portions; forming first and second metal patterns by etching the first and second metal layers; processing the first metal pattern with SF | 02-02-2012 |
20120037913 | THIN-FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A thin-film transistor (TFT) and a method of manufacturing the same are disclosed herein. The TFT may include a gate electrode disposed on an insulating substrate, an insulating layer disposed on the insulating substrate and the gate electrode, an active layer pattern disposed on the insulating layer to overlap the gate electrode, a source electrode disposed on the insulating layer and at least part of which overlaps the active layer pattern, and a drain electrode which is separated from the source electrode and at least part of which overlaps the active layer pattern. A first ohmic contact layer pattern may be disposed between the active layer pattern and the source electrode and between the active layer pattern and the drain electrode. The first ohmic contact layer may have higher nitrogen content on its surface than in other portions of the first ohmic contact layer. | 02-16-2012 |
20120064678 | MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY PANEL - A method for manufacturing a TFT array panel includes forming a photosensitive film pattern with first and second parts in first and second sections on a metal layer, etching the metal layer of a third section using the film pattern as a mask to form first and second metal patterns, etching the film pattern to remove the first part, etching first and second amorphous silicon layers of the third section using the second part as a mask to form an amorphous silicon pattern and a semiconductor, etching the first and second metal patterns of the first section using the second part as a mask to form a source electrode and a drain electrode including an upper layer and a lower layer, and etching the amorphous silicon pattern of the region corresponding to the first section by using the second part as a mask to form an ohmic contact. | 03-15-2012 |
20120135555 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL - A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant. | 05-31-2012 |
20120273787 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - In a thin film transistor array panel according to an exemplary embodiment of the present invention, a plasma process using a mixed gas including hydrogen gas and nitrogen gas with a ratio of a predetermined value is undertaken before depositing a passivation layer. In this manner, performance deterioration of the thin film transistor may be prevented and simultaneously, haze in a transparent electrode may be prevented. Alternatively, a first passivation layer is depsoited, then removed. A passivation layer is again re-deposited, such that little or no haze is present in the resulting passivation layer. | 11-01-2012 |
20130270565 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor array panel is provided and includes a gate line, a gate insulating layer covering the gate line, a semiconductor layer disposed on the gate insulating layer, and a data line and a drain electrode disposed on the semiconductor layer. The data line and the drain electrode have a dual-layered structure including a lower layer and an upper layer with the lower layer having a first portion protruded outside the upper layer and the semiconductor layer having a second portion protruded outside the edge of the lower layer. | 10-17-2013 |
20140285744 | DISPLAY DEVICE - A display device includes a first substrate, a ground electrode disposed on the first substrate, a thin film transistor disposed on the first substrate, a first passivation layer disposed on the thin film transistor, a light blocking member, and a color filter disposed on the first passivation layer. A field generating electrode is disposed on the light blocking member and the color filter. The ground electrode is arranged on the first substrate in a matrix and is connected to a ground terminal. | 09-25-2014 |
20140292626 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes a first substrate, a gate line and a data line on the first substrate, a plurality of display pixels arranged in a row direction and a column direction of a matrix, on the first substrate, each display pixel including a pixel electrode and a common electrode on the first substrate and overlapping each other, and an insulating film between the pixel and common electrodes, a plurality of non-display dummy pixels at an edge of the matrix of display pixels; and a first common voltage line outside the matrix of display pixels and extending in the row direction. | 10-02-2014 |
20140313463 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes a first substrate, a gate line disposed on the first substrate, a data line disposed on the first substrate, a first passivation layer disposed on the gate line and the data line, a color filter disposed on the first passivation layer, a common electrode disposed on the color filter, a light blocking member disposed directly on or directly below the common electrode, a second passivation layer disposed on the common electrode and the light blocking member, and a pixel electrode disposed on the second passivation layer. | 10-23-2014 |
20140362322 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes a plurality of pixels including first, second and third pixels that display different colors and are sequentially disposed, a plurality of data lines including first, second and third data lines sequentially and repeatedly disposed where the first data line is disposed between the third pixel and the first pixel, the second data line is disposed between the first pixel and the second pixel, and the third data line is disposed between the second pixel and the third pixel, widths of the first, second and third data lines are substantially the same as each other, and a first interval between the first data line and the second data line is different from a second interval between the second data line and the third data line or a third interval between the third data line and the first data line. | 12-11-2014 |
20150022766 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes a first substrate and a second substrate which face opposite to each other, a thin film transistor disposed on the first substrate, a pixel electrode connected to the thin film transistor, a first light blocking member disposed on the pixel electrode, and a cover layer disposed on the first light blocking member and covering the first light blocking member. | 01-22-2015 |
20150053984 | THIN FILM TRANSISTOR SUBSTRATE AND THE METHOD THEREOF - A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape. | 02-26-2015 |
20150062521 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes an insulation substrate, a gate line and a data line disposed on the insulation substrate, a first passivation layer disposed on the gate line and the data line, a first common electrode which is disposed on the first passivation layer and overlaps with the data line, an insulating layer disposed on the first common electrode, a second common electrode disposed on the insulating layer, a second passivation layer disposed on the second common electrode, and a pixel electrode disposed on the second passivation layer. | 03-05-2015 |