Patent application number | Description | Published |
20080258233 | Semiconductor Device with Localized Stressor - A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors. | 10-23-2008 |
20100330755 | Semiconductor Device With Localized Stressor - A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors. | 12-30-2010 |
20110230002 | Local Oxidation of Silicon Processes with Reduced Lateral Oxidation - A method of forming an integrated circuit structure includes providing a silicon substrate, and implanting a p-type impurity into the silicon substrate to form a p-type region. After the step of implanting, performing an anneal to form a silicon oxide region, with a portion of the p-type region converted to the silicon oxide region. | 09-22-2011 |
20110241152 | SENSOR ELEMENT ISOLATION IN A BACKSIDE ILLUMINATED IMAGE SENSOR - The present disclosure provides methods and apparatus for sensor element isolation in a backside illuminated image sensor. In one embodiment, a method of fabricating a semiconductor device includes providing a sensor layer having a frontside surface and a backside surface, forming a plurality of frontside trenches in the frontside surface of the sensor layer, and implanting oxygen into the sensor layer through the plurality of frontside trenches. The method further includes annealing the implanted oxygen to form a plurality of first silicon oxide blocks in the sensor layer, wherein each first silicon oxide block is disposed substantially adjacent a respective frontside trench to form an isolation feature. A semiconductor device fabricated by such a method is also disclosed. | 10-06-2011 |
20110260223 | STRESS ENGINEERING TO REDUCE DARK CURRENT OF CMOS IMAGE SENSORS - The active pixel cell structures and methods of preparing such structures described above enable reduction of dark current and white cell counts for active pixel cells. The process of preparing active pixel cell structures introduces stress on the substrate, which could lead to increased dark current and white cell counts of active pixel cells. By depositing a stress layer as part of a pre-metal dielectric layer with a stress that counters the stress induced, both the dark current and the white cell counts can be reduced. If the transistors of the active pixel cells are NMOS, the carrier mobility can also be increased by a tensile stress layer. Raman Spectroscopy can be used to measure the stress exerted on the substrate prior to the deposition of the stress layer. | 10-27-2011 |
20120248515 | STRESS ENGINEERING TO REDUCE DARK CURRENT OF CMOS IMAGE SENSORS - This disclosure relates to an active pixel cell including a shallow trench isolation (STI) structure. The active pixel cell further includes a photodiode neighboring the STI structure, where a first stress resulted from substrate processing prior to deposition of a pre-metal dielectric layer increases dark current and white cell counts of a photodiode of the active pixel cell. The active pixel cell further includes a transistor, where the transistor controls the operation of the active pixel cell. The active pixel cell further includes a stress layer over the photodiode, the STI structure, and the transistor, and the stress layer has a second stress that counters the first stress exerted on the substrate, and the second stress reduces the dark current and the white cell counts caused by the first stress. | 10-04-2012 |
20140001523 | STRESS ENGINEERING TO REDUCE DARK CURRENT OF CMOS IMAGE SENSORS | 01-02-2014 |
Patent application number | Description | Published |
20110173381 | SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT - The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block. | 07-14-2011 |
20120198142 | SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT - The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block. | 08-02-2012 |
20130311713 | SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT - The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block. | 11-21-2013 |
20140317341 | SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT - The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block. | 10-23-2014 |
Patent application number | Description | Published |
20090276673 | METHODS AND SYSTEMS FOR OPTIMIZING HARQ COMMUNICATION - A method and apparatus for optimizing communication in a communication system is provided. The method includes transmitting a plurality of data packets including a first data packet, storing at least one of the plurality of data packets in a first buffer when the first data packet includes an error, determining a remaining storage capacity of the first buffer based on an initial storage capacity of the first buffer and a storage capacity used to store the at least one of the plurality of data packets, and retransmitting the first data packet with additional data, wherein an amount of the additional data is included in the retransmission based on the remaining storage capacity. | 11-05-2009 |
20100004001 | PAGING MECHANISM IN A WIRELESS COMMUNICATION SYSTEM - A communication system is disclosed which includes a communication network having a paging controller and a plurality of base stations to communicate with at least one mobile client device within the system. Also included in the communication system is a base station, between the plurality of base stations, receiving location updates from the at least one mobile client device; and a processor within the paging controller to accumulate the number of location updates relayed by the base station for each mobile client device, wherein the processor determines whether the accumulated number of location updates received exceeds a predetermined threshold number of location updates. The plurality of base stations each broadcast paging messages to the at least one mobile client device when the predetermined threshold number of location updates is not exceeded. The base station, among the plurality of base stations, solely broadcasts paging messages to the at least one mobile client device when the predetermined threshold number of location updates is exceeded. | 01-07-2010 |
20100008278 | METHOD AND APPARATUS FOR A DEVICE POWER SAVINGS CLASS - A method is provided for a device in a wireless communication network including a base station. The method includes sending a sleep mode request to the base station; and receiving a sleep mode response including negotiating parameters from the base station. The method also includes entering a sleep mode determined by a single power saving class applicable to all traffic conditions between the device and the base station; and communicating with the base station based on the sleep mode. Further, the single power saving class is used to define a frame structure for configuring frames to form alternating listening windows and sleep windows, to define an initial sleep window, and to define a default listening window. | 01-14-2010 |
20100115365 | SYSTEM AND METHOD FOR DATA TRANSMISSION - A method for a transmitter to transmit data represented by a plurality of service data units (SDUs). The method includes: generating, for a first transmission, a data block from one or more of the SDUs, or from one or more fragments of the SDUs; generating, based on a protocol, a protocol data unit (PDU) to include the data block; and transmitting the PDU. | 05-06-2010 |
20100120438 | COMMUNICATION NETWORK METHOD AND APPARATUS INCLUDING MACRO BASE STATION AND FEMTO BASE STATION - A communications network comprises a macro base station for providing service to a macrocell and a femto base station in a femtocell, wherein the femtocell overlies the macrocell, the femto base station is configured to perform self-configuration using resource profiles, and resource profiles include pre-configured profiles and frequency reuse information. | 05-13-2010 |
20100226268 | SLOT BASED PERSISTENT ALLOCATION SCHEME - There is provided a method for allocating a mobile station to an available resource slot of a plurality of resource slots within a stream of data frames, the stream of data frames broadcasted to the mobile station by a base station. The method includes scanning resource slots to identify an available resource slot, the available resource slot available for assignment to a resource, wherein the resource slots are included in all of the data frames in the stream of data frames, the scanning further including retrieving a data structure of the available resource slot, the data structure having nodes, the nodes associated with different periodicities and different offsets of the periodicities. The method also includes assigning the mobile station to one of the nodes of the available resource slot with an associated periodicity and an associated offset of the periodicity. | 09-09-2010 |