Patent application number | Description | Published |
20090276605 | Retaining an Association Between a Virtual Address Based Buffer and a User Space Application that Owns the Buffer - Registering memory space for an application is performed. One or more open calls are received from an application to access one or more input/output (I/O) devices. Responsive to receiving the one or more open calls, one or more I/O map and pin calls are sent in order to register memory space for the one or more I/O devices within at least one storage area that will be accessed by the application. A verification is made as to whether the memory space to be registered is associated with the application. Responsive to the memory space being associated with the application, at least one virtual I/O bus address is received for each registered memory space of the one or more I/O devices. At least one I/O command is executed using the at least one virtual I/O bus address without intervention by an operating system or operating system image. | 11-05-2009 |
20100268885 | SPECIFYING AN ACCESS HINT FOR PREFETCHING LIMITED USE DATA IN A CACHE HIERARCHY - A system and method for specifying an access hint for prefetching limited use data. A processing unit receives a data cache block touch (DCBT) instruction having an access hint indicating to the processing unit that a program executing on the data processing system may soon access a cache block addressed within the DCBT instruction. The access hint is contained in a code point stored in a subfield of the DCBT instruction. In response to detecting that the code point is set to a specific value, the data addressed in the DCBT instruction is prefetched into an entry in the lower level cache. The entry may then be updated as a least recently used entry of a plurality of entries in the lower level cache. In response to a new cache block being fetched to the cache, the prefetched cache block is cast out of the cache. | 10-21-2010 |
20110208949 | HARDWARE THREAD DISABLE WITH STATUS INDICATING SAFE SHARED RESOURCE CONDITION - A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled. | 08-25-2011 |
20110296148 | Transactional Memory System Supporting Unbroken Suspended Execution - Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued. | 12-01-2011 |
20120084477 | Transactional Memory Preemption Mechanism - Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction. | 04-05-2012 |
20120185678 | HARDWARE THREAD DISABLE WITH STATUS INDICATING SAFE SHARED RESOURCE CONDITION - A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled. | 07-19-2012 |
20120246658 | Transactional Memory Preemption Mechanism - Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction. | 09-27-2012 |
20130013899 | Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions - Mechanisms are provided for performing escape actions within transactions. These mechanisms execute a transaction comprising a transactional section and an escape action. The transactional section is comprised of one or more instructions that are to be executed in an atomic manner as part of the transaction. The escape action is comprised of one or more instructions to be executed in a non-transactional manner. These mechanisms further populate at least one actions list data structure, associated with a thread of the data processing system that is executing the transaction, with one or more actions associated with the escape action. Moreover, these mechanisms execute one or more actions in the actions list data structure based upon whether the transaction commits successfully or is aborted. | 01-10-2013 |
20130232320 | PERSISTENT PREFETCH DATA STREAM SETTINGS - A prefetch unit includes a transience register and a length register. The transience register hosts an indication of transient for data stream prefetching. The length register hosts an indication of a stream length for data stream prefetching. The prefetch unit monitors the transience register and the length register. The prefetch unit generates prefetch requests of data streams with a transient property up to the stream length limit when the transience register indicates transient and the length register indicates the stream length limit for data stream prefetching. A cache controller coupled with the prefetch unit implements a cache replacement policy and cache coherence protocols. The cache controller writes data supplied from memory responsive to the prefetch requests into cache with an indication of transient. The cache controller victimizes cache lines with an indication of transient independent of the cache replacement policy. | 09-05-2013 |
20140013055 | ENSURING CAUSALITY OF TRANSACTIONAL STORAGE ACCESSES INTERACTING WITH NON-TRANSACTIONAL STORAGE ACCESSES - A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction. | 01-09-2014 |
20140013060 | ENSURING CAUSALITY OF TRANSACTIONAL STORAGE ACCESSES INTERACTING WITH NON-TRANSACTIONAL STORAGE ACCESSES - A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction. | 01-09-2014 |
20140040551 | REWIND ONLY TRANSACTIONS IN A DATA PROCESSING SYSTEM SUPPORTING TRANSACTIONAL STORAGE ACCESSES - In a multiprocessor data processing system having a distributed shared memory system, a memory transaction that is a rewind-only transaction (ROT) and that includes one or more transactional memory access instructions and a transactional abort instruction is executed. In response to execution of the one or more transactional memory access instructions, one or more memory accesses to the distributed shared memory system indicated by the one or more transactional memory access instructions are performed. In response to execution of the transactional abort instruction, execution results of the one or more transaction memory access instructions are discarded and control is passed to a fail handler. | 02-06-2014 |
20140040557 | NESTED REWIND ONLY AND NON REWIND ONLY TRANSACTIONS IN A DATA PROCESSING SYSTEM SUPPORTING TRANSACTIONAL STORAGE ACCESSES - In a multiprocessor data processing system having a distributed shared memory system, first and second nested memory transactions are executed, where the first memory transaction is a rewind-only transaction (ROT) and the second memory transaction is a non-ROT memory transaction. The first memory transaction has a transaction body including the second memory transaction and an additional plurality of transactional memory access instructions. In response to execution of the transactional memory access instructions, memory accesses are performed to the distributed shared memory system. Conflicts between memory accesses not within the first memory transaction and at least a load footprint of any of the transactional memory access instructions preceding the second memory transaction are not tracked. However, conflicts between memory accesses not within the first memory transaction and store and load footprints of any of the transactional memory access instructions that follow initiation the second memory transaction are tracked. | 02-06-2014 |
20140047195 | TRANSACTION CHECK INSTRUCTION FOR MEMORY TRANSACTIONS - A processing unit of a data processing system having a shared memory system executes a memory transaction including a transactional store instruction that causes a processing unit of the data processing system to make a conditional update to a target memory block of the shared memory system conditioned on successful commitment of the memory transaction. The memory transaction further includes a transaction check instruction. In response to executing the transaction check instruction, the processing unit determines, prior to conclusion of the memory transaction, whether the target memory block of the shared memory system was modified after the conditional update caused by execution of the transactional store instruction. In response to determining that the target memory block has been modified, a condition register within the processing unit is set to indicate a conflict for the memory transaction. | 02-13-2014 |
20140047196 | TRANSACTION CHECK INSTRUCTION FOR MEMORY TRANSACTIONS - A processing unit of a data processing system having a shared memory system executes a memory transaction including a transactional store instruction that causes a processing unit of the data processing system to make a conditional update to a target memory block of the shared memory system conditioned on successful commitment of the memory transaction. The memory transaction further includes a transaction check instruction. In response to executing the transaction check instruction, the processing unit determines, prior to conclusion of the memory transaction, whether the target memory block of the shared memory system was modified after the conditional update caused by execution of the transactional store instruction. In response to determining that the target memory block has been modified, a condition register within the processing unit is set to indicate a conflict for the memory transaction. | 02-13-2014 |
20140047205 | INTERACTION OF TRANSACTIONAL STORAGE ACCESSES WITH OTHER ATOMIC SEMANTICS - In a processor, an instruction sequence including, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block is detected. In response to detecting the instruction sequence, the processor causes the conditional write access to the target memory block to fail. | 02-13-2014 |
20140075441 | METHOD AND APPARATUS FOR RECORDING AND PROFILING TRANSACTION FAILURE SOURCE ADDRESSES IN HARDWARE TRANSACTIONAL MEMORIES - A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction. | 03-13-2014 |
20140101359 | ASYMMETRIC CO-EXISTENT ADDRESS TRANSLATION STRUCTURE FORMATS - An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated. | 04-10-2014 |
20140101404 | SELECTABLE ADDRESS TRANSLATION MECHANISMS - An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration, and the use of a particular translation structure format in translating an address is selectable. | 04-10-2014 |
20140101407 | SELECTABLE ADDRESS TRANSLATION MECHANISMS - An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration, and the use of a particular translation structure format in translating an address is selectable. | 04-10-2014 |
20140101408 | ASYMMETRIC CO-EXISTENT ADDRESS TRANSLATION STRUCTURE FORMATS - An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated. | 04-10-2014 |
20140115590 | METHOD AND APPARATUS FOR CONDITIONAL TRANSACTION ABORT AND PRECISE ABORT HANDLING - A method for executing a transaction in a data processing system initiates the transaction by a transactional-memory system coupled to that memory component. The method includes initiating the transaction by a transactional-memory system that is part of a memory component of the data processing system. The transaction includes instructions for comparing multiple parameters, and aborting the transaction by the transactional-memory system based upon a comparison of the multiple parameters. | 04-24-2014 |
20140281209 | HARDWARE-BASED PRE-PAGE WALK VIRTUAL ADDRESS TRANSFORMATION - An indication of a virtual address is received. A current page size of a plurality of available page sizes is read from a register. A shift amount is determined based, at least in part, on the current page size. A bit shift of the virtual address is performed in which the virtual address is bit shifted by, at least, the determined shift amount. | 09-18-2014 |
20140281245 | VIRTUAL UNIFIED INSTRUCTION AND DATA CACHES - Execution of a store instruction to modify an instruction at a memory location identified by a memory address is requested. A cache controller stores the memory address and the modified data in an associative memory coupled to a data cache and an instruction cache. In addition, the modified data is stored in a second level cache without invalidating the memory location associated with the instruction cache. | 09-18-2014 |
20140281353 | HARDWARE-BASED PRE-PAGE WALK VIRTUAL ADDRESS TRANSFORMATION - An apparatus includes a processor and a virtual address transformation unit coupled with the processor. The virtual address transformation unit includes a register. The virtual address transformation unit is configured to receive an indication of a virtual address and read, from the register, a current page size of a plurality of available page sizes. The virtual address transformation unit is also configured to determine a shift amount based, at least in part, on the current page size and perform a bit shift of the virtual address, wherein the virtual address is bit shifted by, at least, the determined shift amount. | 09-18-2014 |
Patent application number | Description | Published |
20100110450 | METHOD AND SYSTEM FOR INSPECTING BLADE TIP CLEARANCE - A method for inspecting blade tip clearance between at least one rotor blade and a case spaced radially outward from the rotor blade is provided. The method includes inserting a probe into an aperture defined in the case and emitting electromagnetic energy into the case using the probe. The method also includes detecting electromagnetic energy reflected from a blade tip portion of the rotor blade and determining a blade tip clearance defined between the blade tip and the case based on the detected electromagnetic energy. | 05-06-2010 |
20110061298 | METHOD AND APPARATUS FOR DRYING SOLID FEEDSTOCK USING STEAM - Steam may be used to dry feedstock prior to delivery to a gasifier. A steam supply may be delivered to embodiments such as a feedstock dryer. Heat from the steam may then be transferred into the feedstock and used in drying the feedstock. Steam pressures may include pressures from 75 pounds per square inch up to and including 900 pounds per square inch. | 03-17-2011 |
20120067702 | SYSTEM FOR THERMALLY CONTROLLING A SOLID FEED PUMP - According to various embodiments, a system includes a solid feed pump. The solid feed pump includes a housing, a rotor disposed in the housing, a curved passage disposed between the rotor and the housing, an inlet coupled to the curved passage, an outlet coupled to the curved passage, a solid feed guide extending across the curved passage, and a thermal control path through a portion of the solid feed pump. | 03-22-2012 |
20120227442 | SYSTEM AND METHOD FOR COOLING A SOLVENT FOR GAS TREATMENT - The present embodiments are directed towards the cooling of a solvent of a gas treatment system using a fluid flow from an air separation unit. In one embodiment, a system is provided that includes an air separation unit. The air separation unit has an air inlet configured to receive an air flow, an oxygen outlet configured to output an oxygen flow, a nitrogen outlet configured to output a nitrogen flow and a cooling system configured to cool the air flow to enable separation of the air flow into the oxygen flow and the nitrogen flow, wherein the cooling system is configured to cool a first solvent of a first gas treatment system. | 09-13-2012 |
20130255143 | SYSTEM FOR DRYING A GASIFICATION FEED - Present embodiments include systems for reducing moisture in a solid feed provided to a gasifier. For example, in an embodiment, a feedstock preparation system includes an aspirator having a first inlet for receiving a flow of steam, a second inlet for receiving a flow of a moist gaseous phase from a grinding mechanism configured to grind a solid fuel in the presence of a conveyance gas. The moist gaseous phase includes the conveyance gas and moisture removed from the ground solid fuel. The aspirator also includes an outlet configured to output a reduced pressure flow having the steam and the moist gaseous phase. The aspirator is configured to enhance moisture removal from the ground solid fuel to produce a dry feed of the ground solid fuel. The aspirator discharge is recycled within the process to heat the incoming dry conveyance gas and improve system efficiency. | 10-03-2013 |
20140060325 | PROCESS STREAM DESULFURIZATION - A method of reducing the concentration of at least one sulfur compound in a process stream and for recovering at least one sulfur compound from a process stream are provided. A process stream is delivered to a vessel, wherein the vessel comprises an adsorbent material. At least one solvent is transferred into the vessel. One or more fluids are then removed from the vessel. At least one of the fluids removed from the vessel comprises a clean gas. The adsorbent material may be regenerated to yield a high concentration of the at least one sulfur compound. | 03-06-2014 |
20140116049 | SYSTEM AND METHOD FOR USING BOILER FEEDWATER - A system includes a first steam generator configured to generate a first boiler feedwater, a second steam generator configured to generate a second boiler feedwater, a common boiler feedwater configured to combine the first boiler feedwater and the second boiler feedwater to produce a common boiler feedwater, and a heater configured to receive the common boiler feedwater to heat a gas. | 05-01-2014 |
Patent application number | Description | Published |
20120136994 | INTERNET PROVIDER SUBSCRIBER COMMUNICATIONS SYSTEM - A system, method, and computer readable medium for communicating at least one real-time specially-composed bulletin message to at least one subscriber of a provider of Internet services, comprising a first device, and a second device communicably coupled to the first device, wherein the first device: accesses only subscriber upstream traffic to a destination web site requested by the subscriber, wherein the first device inter-connects between the at least one subscriber and the destination web site, identifies the at least one subscriber's identification based on the accessed subscriber upstream traffic automatically provided by the subscriber, and provides the unique subscriber identification to the second device located at the provider of Internet services providing data services and management control to the first device, wherein the second device determines the subscriber associated with the unique subscriber identification. | 05-31-2012 |
20120173716 | INTERNET CONNECTION USER COMMUNICATIONS SYSTEM - A method for communicating in real-time to users of a provider of Internet access service, without requiring any installation or set-up by the user, that utilizes the unique identification information automatically provided by the user during communications for identifying the user to provide a fixed identifier which is then communicated to a redirecting device. Messages may then be selectively transmitted to the user. The system is normally transparent to the user, with no modification of its content along the path. Content then may be modified or replaced along the path to the user. For the purposes of establishing a reliable delivery of bulletin messages from providers to their users, the system forces the delivery of specially-composed World Wide Web browser pages to the user, although it is not limited to that type of data. These may be displayed permanently, temporarily, or in separate pop-up browser windows, according to policies set by the provider irrespective of the user's intended browsing destination. | 07-05-2012 |
20120198526 | SYSTEM, METHOD AND COMPUTER READABLE MEDIUM FOR MESSAGE AUTHENTICATION TO SUBSCRIBERS OF AN INTERNET SERVICE PROVIDER - An internet service provider (ISP) is configured to provide notification messages such as service updates to subscribers via redirected web pages. In order for the web pages to be treated as originating from the ISP, the ISP provides a shared secret in the browser message. The shared secret may be a secret not derivable by viruses or trojans in the subscriber computer, such as a MAC address of the subscriber modem. | 08-02-2012 |
20130326598 | SYSTEM, METHOD AND COMPUTER READABLE MEDIUM FOR MESSAGE AUTHENTICATION TO SUBSCRIBERS OF AN INTERNET SERVICE PROVIDER - An internet service provider (ISP) is configured to provide notification messages such as service updates to subscribers via redirected web pages. In order for the web pages to be treated as originating from the ISP, the ISP provides a shared secret in the browser message. The shared secret may be a secret not derivable by viruses or trojans in the subscriber computer, such as a MAC address of the subscriber modem. | 12-05-2013 |
20140201297 | SYSTEM, METHOD AND COMPUTER READABLE MEDIUM FOR PROCESSING UNSOLICITED ELECTRONIC MAIL - An internet service provider (ISP) is configured to analyze a subscriber's sent e-mail packets to determine a subscriber identity associated with the e-mail packets. A database is then queried to determine a current sending rate of e-mails by the subscriber. A sending rate above an allowed threshold causes the upstream transmission of the e-mail packets to be blocked by injecting connection destroying packets. A subscriber remains blocked from upstream transmission of e-mails until the sending rate as determined by the ISP drops below a second, more stringent threshold. This automatic process is also accompanied by automated messaging to the subscriber with information as to the measures taken and remedial options. | 07-17-2014 |
20140330941 | INTERNET PROVIDER SUBSCRIBER COMMUNICATIONS SYSTEM - A system, method, and computer readable medium for communicating at least one real-time specially-composed bulletin message to at least one subscriber of a provider of Internet services, comprising a first device, and a second device communicably coupled to the first device, wherein the first device: accesses only subscriber upstream traffic to a destination web site requested by the subscriber, wherein the first device inter-connects between the at least one subscriber and the destination web site, identifies the at least one subscriber's identification based on the accessed subscriber upstream traffic automatically provided by the subscriber, and provides the unique subscriber identification to the second device located at the provider of Internet services providing data services and management control to the first device, wherein the second device determines the subscriber associated with the unique subscriber identification. | 11-06-2014 |
20140379918 | INTERNET CONNECTION USER COMMUNICATIONS SYSTEM - A method for communicating in real-time to users of a provider of Internet access service, without requiring any installation or set-up by the user, that utilizes the unique identification information automatically provided by the user during communications for identifying the user to provide a fixed identifier which is then communicated to a redirecting device. Messages may then be selectively transmitted to the user. The system is normally transparent to the user, with no modification of its content along the path. Content then may be modified or replaced along the path to the user. For the purposes of establishing a reliable delivery of bulletin messages from providers to their users, the system forces the delivery of specially-composed World Wide Web browser pages to the user, although it is not limited to that type of data. | 12-25-2014 |
20150026551 | SYSTEM, METHOD AND COMPUTER READABLE MEDIUM FOR DETERMINING USERS OF AN INTERNET SERVICE - An internet service provider (ISP) is configured to analyze data sent by a user to determine a subscriber account associated with the data and a user associated with the data. A database is then queried to determine the number of users of the subscriber account, with a number above a threshold indicating a likely theft of service. This automatic process is accompanied by automated messaging to the user with information as to the measures taken and remedial options. The messaging may be different dependent on whether the user is deemed to be an authorized user having subscriber account administration rights. | 01-22-2015 |