Sardesai, US
Ashish Sardesai, Rockville, MD US
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20110058544 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR VERIFYING THE AVAILABILITY OF AN INTERNET PROTOCOL (IP) MEDIA ROUTER DURING A CALL SETUP - Methods, systems, and computer readable media for verifying the availability of an IP media router during a call setup are described. In one embodiment, the method comprises receiving, from a first endpoint device, a call setup signaling message requesting to establish a call session with a second endpoint device. The method also includes selecting a first media router to establish a first call leg of the call session, performing a route query and MAC address resolution to determine if the first media router is available, and if the first media router is determined to be available, creating a first redirect stream to communicate media packets received from the second endpoint device to the first endpoint device via the first call leg. | 03-10-2011 |
20110231924 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR PROVIDING APPLICATION LAYER FIREWALL AND INTEGRATED DEEP PACKET INSPECTION FUNCTIONS FOR PROVIDING EARLY INTRUSION DETECTION AND INTRUSION PREVENTION AT AN EDGE NETWORKING DEVICE - Methods, systems, and computer readable media for an application layer firewall function including an integrated deep packet inspection function for providing early intrusion detection and intrusion prevention at an edge networking device are disclosed. According to one method, steps are performed at a session controller configured to operate at the border of a first network and a second network. The steps include receiving, at an intrusion protection system (IPS) module of the session controller interfacing with modules associated with layers 2 and above of a protocol stack of the session controller, information gathered by modules located at lower layers and associated with an intrusion attempt, vulnerability, or other security policy violation. In response to receiving the information, the IPS module provides at least one of a security policy and a rule to a module located at the most appropriate layer for securing the intrusion attempt, vulnerability, or other security policy violation. | 09-22-2011 |
Harshad Sardesai, Ellicott City, MD US
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20100111530 | POLARIZATION MODE DISPERSION COMPENSATION AND POLARIZATION DEMULTIPLEXING SYSTEMS AND METHODS FOR OPTICAL TRANSMISSION SYSTEMS - The present disclosure provides polarization mode dispersion compensation (PMDC) and polarization de-multiplexing systems and methods for polarization multiplexed (PolMux) optical transmission systems. The PMDC detects an error signal before a polarization splitter in PolMux systems for controlling polarization controllers (PC) and/or DGDs in the PMDC for return-to-zero (RZ) differential m-phase shift keying (DmPSK) signals. For bit-aligned PolMux systems, the error signal could be the level of clock frequency at one, two, or more times of the baud rate at one polarization. For bit-interleaved PolMux systems, the error signal could be the level of clock frequency at two times of the baud rate at one polarization. The PMDC can operate in PolMux systems with any arbitrary time offset between the two polarizations. The polarization de-multiplexer utilizes error detection at both output arms of a polarization splitter to mitigate PDL impact on any PolMux type of signal. | 05-06-2010 |
20100111534 | SYSTEMS AND METHODS FOR CHANNEL POWER OFFSETS FOR MULTI DATA RATE DWDM TRANSMISSION OVER OPTICAL ADD DROP MULTIPLEXERS - The present disclosure provides systems and methods for channel power offsets for multi-rate dense wave division multiplexed (DWDM) transmission over optical add-drop multiplexers (OADMs). The present invention includes algorithms to set power levels of each type of channel in different sections of a fiber system to optimize the performance of that type of channel at the receiver. For example, the present invention can optimize power levels based on different channel modulation formats, bit rates, channel spacings, and the like. Advantageously, the present invention improves the total capacity (bit rate) and reach that channels of a given bit rate can achieve, and maximizes the reach of channels without sacrificing capacity. | 05-06-2010 |
Harshad P. Sardesai, Ellicott City, MD US
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20090254317 | SYSTEMS AND METHODS FOR HIGHLY EFFICIENT BIT ERROR RATE MODELING IN QUASI-LINEAR COMMUNICATION NETWORKS - The present invention provides systems and methods for highly efficient bit error rate (BER) modeling in quasi-linear communication networks. In the present invention, nonlinear noise is treated within a linearization approach along with the amplified spontaneous emission (ASE) noise, and the nonlinear noise is considered as another source of noise in addition to the ASE noise. This enables a quasi-analytical approach to the BER calculation. First, a covariance matrix is analytically computed. An equation is derived for a noise component of a signal and an implicit analytical solution is found depending on the signal and system parameters. Second, probability distribution functions (pdfs) are computed for the signal. An analytical calculation is performed of the characteristic function for the noise statistics. Next, a numerical computation of the Fourier transform of the characteristic function is performed to yield the pdf, and numerical integration is performed on the pdfs to yield the BER. | 10-08-2009 |
Nagesh Sardesai, West Lafayette, IN US
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20130227746 | METHODS AND COMPOSITIONS TO REGULATE PLANT TRANSFORMATION SUSCEPTIBILITY - A genetic screen for | 08-29-2013 |
20150101083 | ZEA MAYS METALLOTHIONEIN-LIKE REGULATORY ELEMENTS AND USES THEREOF - Provided are constructs and methods for expressing a transgene in plant cells and/or plant tissues using | 04-09-2015 |
20160068851 | METHODS AND COMPOSITIONS FOR RECOMBINATION A GENE-DEFICIENT STRAINS OF AGROBACTERIUM TUMEFACIENS - The present disclosure provides novel compositions and methods for the production and use of | 03-10-2016 |
Neil Rajendra Sardesai, Arcadia, CA US
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20090275904 | SHEET ASSEMBLIES WITH RELEASABLE MEDICAMENTS - A sheet assembly comprises an insoluble layer disposed to define an inner reservoir and a medicament disposed in the inner reservoir. A garment is formed from said textile assembly. | 11-05-2009 |
20130304032 | Bone fixation system with structure to enhance tissue growth and/or administer medicament inside bone - A bone fastener or an orthopedic implant that resides within the bone after orthopedic surgery has a threaded and/or unthreaded shaft, said shaft has a hollow portion and a solid portion. The hollow portion may have a structure that enhances tissue growth and may also hold materials that enhance tissue growth. The hollow portion may also hold materials to treat diseases and/or promote bone fracture healing. | 11-14-2013 |
Niranjan Sardesai US
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20160022802 | Novel Vaccines Against Multiple Subtypes Of Dengue Virus - An aspect of the present invention is related to nucleic acid constructs capable of expressing a polypeptide, such as a consensus dengue prME that elicits an immune response in a mammal against more than one subtype of dengue virus, and methods of use thereof. Additionally, there are DNA plasmid vaccines capable of generating in a mammal an immune response against a plurality of dengue virus subtypes, comprising a DNA plasmid and a pharmaceutically acceptable excipient, and methods of use thereof. The DNA plasmid is capable of expressing a consensus dengue antigen in a cell of the mammal in a quantity effective to elicit an immune response in the mammal that is cross reactive against all 4 dengue subtypes. | 01-28-2016 |
Niranjan Sardesai, Blue Bell, PA US
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20140236070 | LINEAR EXPRESSION CASSETTES AND USES THEREOF - Provided herein are linear nucleic expression cassettes and methods of using same in a non-invasive method of vaccination. The method combines electroporation and linear DNA constructs encoding antigens to elicit antigen-specific immune responses. | 08-21-2014 |
20150284448 | DNA ANTIBODY CONSTRUCTS AND METHOD OF USING SAME - Disclosed herein is a composition including a recombinant nucleic acid sequence that encodes an antibody. Also disclosed herein is a method of generating a synthetic antibody in a subject by administering the composition to the subject. The disclosure also provides a method of preventing and/or treating disease in a subject using said composition and method of generation. | 10-08-2015 |
20160022802 | Novel Vaccines Against Multiple Subtypes Of Dengue Virus - An aspect of the present invention is related to nucleic acid constructs capable of expressing a polypeptide, such as a consensus dengue prME that elicits an immune response in a mammal against more than one subtype of dengue virus, and methods of use thereof. Additionally, there are DNA plasmid vaccines capable of generating in a mammal an immune response against a plurality of dengue virus subtypes, comprising a DNA plasmid and a pharmaceutically acceptable excipient, and methods of use thereof. The DNA plasmid is capable of expressing a consensus dengue antigen in a cell of the mammal in a quantity effective to elicit an immune response in the mammal that is cross reactive against all 4 dengue subtypes. | 01-28-2016 |
Niranjan Y Sardesai, Blue Bell, PA US
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20100291144 | NOVEL VACCINES AGAINST MULTIPLE SUBTYPES OF DENGUE VIRUS - An aspect of the present invention is related to nucleic acid constructs capable of expressing a polypeptide that elicits an immune response in a mammal against more than one subtype of dengue virus, and methods of use thereof. Additionally, there are DNA plasmid vaccines capable of generating in a mammal an immune response against a plurality of dengue virus subtypes, comprising a DNA plasmid and a pharmaceutically acceptable excipient, and methods of use thereof. The DNA plasmid is capable of expressing a consensus dengue antigen in a cell of the mammal in a quantity effective to elicit an immune response in the mammal. | 11-18-2010 |
20110262394 | DNA CONSTRUCTS ELICITING IMMUNE RESPONSE AGAINST FLAVIVIRUS AND EFFECTIVE ADJUVANTS - Aspects of the present invention relate to isolated nucleic acids that encode a consensus DIII domain of protein E and vaccines made using same, and also methods for using the aforementioned to generate in a host an immune response against multiple serotypes of flavivirus, particularly West Nile virus and Japanese encephalitis virus. | 10-27-2011 |
20120282217 | FOOT AND MOUTH DISEASE VIRUS (FMDV) CONSENSUS PROTEINS, CODING SEQUENCES THEREFOR AND VACCINES MADE THEREFROM - Provided herein is a nucleic acid comprising consensus amino acid sequence of foot-and-mouth disease FMDV VP1-4 coat proteins of FMDV subtypes A, Asia 1, C, O, SAT1, SAT2, and SAT3 as well as plasmids and vaccines expressing the sequences. Also provided herein is methods for generating an immune response against one or more FMDV subtypes using the vaccine as described above as well as methods for deciphering between vaccinated mammals with the vaccine and those that are infected with FMDV. | 11-08-2012 |
20130273112 | CONSENSUS ANTIGEN CONSTRUCTS AND VACCINES MADE THEREFROM, AND METHODS OF USING THE SAME TO TREAT MALARIA - Provided herein is consensus amino acid sequences of | 10-17-2013 |
20130302361 | CONSENSUS PROSTATE ANTIGENS, NUCLEIC ACID MOLECULE ENCODING THE SAME AND VACCINE AND USES COMPRISING THE SAME - Provided herein are consensus amino acid sequences of prostate antigens that are capable of breaking tolerance in a targeted species, including PSA, PSMA, STEAP and PSCA antigens. Also provided are nucleic acid sequences that encode one or more consensus amino acid sequences of prostate antigens PSA, PSMA, STEAP and PSCA, as well genetic constructs/vectors and vaccines expressing the sequences. Also provided herein are methods for generating an autoimmune response against prostate cancer cells by administering one or more of the vaccines, proteins, and/or nucleic acid sequences that are provided. | 11-14-2013 |
20140249467 | CROSS-PROTECTIVE ARENAVIRUS VACCINES AND THEIR METHOD OF USE - The invention relates to DNA vaccines that target multiple arenavirus agents singly or simultaneously. | 09-04-2014 |
20140341936 | Novel Clostridium Difficile DNA Vaccine - The invention relates to compositions and methods for treating | 11-20-2014 |
20150064221 | COMPOUNDS HAVING IMMUNOMUDULATOR ACTIVITY - The present invention is directed to methods of suppressing an immune response in a subject in need thereof comprising administering a therapeutically effective amount of a compound having the following formula: | 03-05-2015 |
20150150957 | Consensus Prostate Antigens, Nucleic Acid Molecule Encoding The Same And Vaccine And Uses Comprising The Same - Provided herein are consensus amino acid sequences of prostate antigens that are capable of breaking tolerance in a targeted species, including PSA, PSMA, STEAP and PSCA antigens. Also provided are nucleic acid sequences that encode one or more consensus amino acid sequences of prostate antigens PSA, PSMA, STEAP and PSCA, as well as genetic constructs/vectors and vaccines expressing the sequences. Also provided herein are methods for generating an autoimmune response against prostate cancer cells by administering one or more of the vaccines, proteins, and/or nucleic acid sequences that are provided. | 06-04-2015 |
20160039886 | Foot and Mouth Disease Virus (FMDV) Consensus Proteins, Coding Sequences Therefor and Vaccines Made Therefrom - Provided herein is a nucleic acid comprising consensus amino acid sequence of foot-and-mouth disease FMDV VP1-4 coat proteins of FMDV subtypes A, Asia 1, C, O, SAT1, SAT2, and SAT3 as well as plasmids and vaccines expressing the sequences. Also provided herein is methods for generating an immune response against one or more FMDV subtypes using the vaccine as described above as well as methods for deciphering between vaccinated mammals with the vaccine and those that are infected with FMDV. | 02-11-2016 |
20160045589 | Foot and Mouth Disease Virus (FMDV) Consensus Proteins, Coding Sequences Therefor and Vaccines Made Therefrom - The present invention relates to synthetic, consensus foot-and-mouth disease virus (FMDV) immunogenic proteins and nucleic acid molecule encoding such proteins, to vaccines against FMDV, to methods for inducing immune responses against FMVD, to methods for distinguishing between individuals infected with FMDV versus those vaccinated against FMDV, and methods of prophylactically and/or therapeutically immunizing individuals against FMDV. | 02-18-2016 |
Niranjan Y. Sardesai US
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20160045589 | Foot and Mouth Disease Virus (FMDV) Consensus Proteins, Coding Sequences Therefor and Vaccines Made Therefrom - The present invention relates to synthetic, consensus foot-and-mouth disease virus (FMDV) immunogenic proteins and nucleic acid molecule encoding such proteins, to vaccines against FMDV, to methods for inducing immune responses against FMVD, to methods for distinguishing between individuals infected with FMDV versus those vaccinated against FMDV, and methods of prophylactically and/or therapeutically immunizing individuals against FMDV. | 02-18-2016 |
Niranjan Y. Sardesai, North Wales, PA US
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20090304627 | SMALLPOX DNA VACCINE AND THE ANTIGENS THEREIN THAT ELICIT AN IMMUNE RESPONSE - The present invention relates to DNA vaccines that are capable of generating a protective immune response in mammals against a pox virus, and comprises at least one DNA plasmid capable of expressing a plurality of VACV MV antigens, and at least one DNA plasmid capable of expressing a plurality of VACV EV antigens. Also, the present invention relates to methods of inducing a protective immune response in a mammal to pox virus, including a neutralizing antibody response, comprising: injecting into tissue of said mammal said DNA vaccine. | 12-10-2009 |
20110105354 | Methods and Apparatus for Conducting Multiple Measurements on a Sample - Multiplexed test measurements are conducted using an assay module having a plurality of assay domains. In preferred embodiments, these measurements are conducted in assay modules having integrated electrodes with a reader apparatus adapted to receive assay modules, induce luminescence, preferably electrode induced luminescence, in the wells or assay regions of the assay modules and measure the induced luminescence. | 05-05-2011 |
Nolan Rajendra Sardesai, Arcadia, CA US
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20150335334 | APPARATUS AND METHOD TO STOP BLEEDING - A hemostatic device is disclosed to stop bleeding at a puncture site on the wrist of a patient, the device comprising a transparent flexible band to be wrapped at the site where the bleeding is to be stopped, a curved frame having an inner peripheral side and possessing a first curved portion in its first half and a second curved portion in its second half, a first balloon provided on the inner peripheral side in the first half of the curved frame and a second balloon provided on the inner peripheral side in the second half of the curved frame, the first balloon being larger than the second balloon. The bleeding from radial artery is stopped by compressing the radial artery at the puncture site using inflation of the first balloon and radial artery flow is increased by compression of ipsilateral ulnar artery using inflation of the second balloon. | 11-26-2015 |
Rajendra G. Sardesai, Pasadena, CA US
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20120308754 | Healthcare Form Assembly Having a Plurality of Removable Strips with Perforated Liner Portion - A healthcare form assembly is described which includes a carrier sheet, a release coating applied to the carrier sheet, one or more regions of pressure sensitive adhesive adjacent the release coating, and a printable facestock sheet in contact with the adhesive and being removably disposed on the carrier sheet. The printable facestock sheet includes a collection of cut lines to thereby form adhesive strips which can be readily removed from the carrier sheet. The carrier sheet includes one or more weakened separation lines that facilitate use of the healthcare assembly and in particular, removal of the adhesive strips. Particular features such as peel zones and fingerlifts are also described. | 12-06-2012 |
Rajendra Gurudas Sardesai, Arcadia, CA US
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20150059757 | APPARATUS AND METHOD TO PROVIDE BREATHING SUPPORT - A ventilator, or a breathing assistance apparatus, is disclosed to ventilate patients who may have breathing difficulties, said device comprising a inspiratory pressure control duct configured to be immersed in a first body of fluid; a positive end-expiratory pressure control duct configured to be immersed in a second body of fluid; at least one valve connected to the peak inspiratory pressure control duct and to the positive end-expiratory pressure control duct, and at least one controller communicably connected to the valve to control rate of cycling of the valve, thereby controlling number of breaths per minute, and to control the duration of peak inspiratory pressure also known as inspiratory time. | 03-05-2015 |
20150335334 | APPARATUS AND METHOD TO STOP BLEEDING - A hemostatic device is disclosed to stop bleeding at a puncture site on the wrist of a patient, the device comprising a transparent flexible band to be wrapped at the site where the bleeding is to be stopped, a curved frame having an inner peripheral side and possessing a first curved portion in its first half and a second curved portion in its second half, a first balloon provided on the inner peripheral side in the first half of the curved frame and a second balloon provided on the inner peripheral side in the second half of the curved frame, the first balloon being larger than the second balloon. The bleeding from radial artery is stopped by compressing the radial artery at the puncture site using inflation of the first balloon and radial artery flow is increased by compression of ipsilateral ulnar artery using inflation of the second balloon. | 11-26-2015 |
Shantanu Sardesai, Sammamish, WA US
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20090319766 | PROVISIONING AN UNKNOWN COMPUTER SYSTEM - A method of provisioning an unknown computer system is disclosed. The method includes detecting a computer system to be provisioned, determining that the computer system is unknown to a configuration management system, and identifying a global identifier and a digital certificate to be used to provision the computer system. The method further includes communicating the global identifier and the digital certificate from a network based boot strap server or from boot strap media to the computer system prior to loading an operating system onto the computer system. | 12-24-2009 |
20110138375 | AUTOMATED STATE MIGRATION WHILE DEPLOYING AN OPERATING SYSTEM - Migration of a user state from a source computing device to a destination computing device using a state migration point (SMP) is disclosed. The destination computing device may be the same as the source computing device but with a different operating system. The user state is securely stored by the SMP until the user state is restored on the destination computing device or a predetermined period of time has elapsed. Additional SMPs can be added without an architectural change. SMPs can be used to simultaneously migrate the states of multiple users of the source computing device to multiple destination computing devices. The SMPs can be restricted to migrate only the user states of computing devices with particular IP subnets. The SMPs can retain user states for a period of time after restoration in order to provide a backup, if necessary. | 06-09-2011 |
Swanand Sardesai, Irvine, CA US
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20140378848 | Method and Apparatus for Motion Artifact Reduction in ECG Harness - A motion artifact reduction apparatus and method | 12-25-2014 |
Vikram Sudhir Sardesai, San Jose, CA US
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20160065555 | ACCESSING A CLOUD-BASED SERVICE PLATFORM USING ENTERPRISE APPLICATION AUTHENTICATION - Systems for managing user-level security in a cloud-based service platform. A server in a cloud-based environment is configured to interface with storage devices that store objects that are accessible over a network by two or more users. An enterprise entity is identified using an enterprise identifier associated with the enterprise, and an application service is associated with an application identifier. An application service request comprising a user identifier and the application identifier is received, and authentication is determined based on the combination of the user identifier and a pre-authenticated application identifier. Once the application service request is authenticated, then specific aspects of the service request are authorized. The integrity of the application identifier is confirmed by locating a secure association of the given application identifier to a pre-shared enterprise identifier. Logging, auditing and other functions can be performed at the user level using the user identifier for user-level tracking. | 03-03-2016 |
Viraj Sardesai, Poughkeepsie, NY US
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20150243544 | FORMATION OF AIR-GAP SPACER IN TRANSISTOR - Embodiments of present invention provide a method of forming air spacers in a transistor structure. The method includes forming a gate structure of a transistor on top of a semiconductor substrate; forming a first and a second disposable spacers adjacent to a first and a second sidewall of the gate structure; forming a first and a second conductive studs next to the first and the second disposable spacer; removing the first and second disposable spacers to create empty spaces between the first and second conductive studs and the gate structure; and preserving the empty spaces by forming dielectric plugs at a top of the empty spaces. | 08-27-2015 |
20150325483 | FORMATION OF METAL RESISTOR AND E-FUSE - Embodiments of present invention provide a method of forming metal resistor. The method includes forming a first and a second structure on top of a semiconductor substrate in a replacement-metal-gate process to have, respectively, a sacrificial gate and spacers adjacent to sidewalls of the sacrificial gate; covering the second structure with an etch-stop mask; replacing the sacrificial gate of the first structure with a replacement metal gate; removing the etch-stop mask to expose the sacrificial gate of the second structure; forming a silicide in the second structure as a metal resistor; and forming contacts to the silicide. In one embodiment, forming the silicide includes siliciding a top portion of the sacrificial gate of the second structure to form the metal resistor. In another embodiment, forming the silicide includes removing the sacrificial gate of the second structure to expose and silicide a channel region underneath thereof. | 11-12-2015 |
20150364419 | FORMATION OF METAL RESISTOR AND E-FUSE - Embodiments of present disclosure provide methods of forming a resistor. One such method can include forming a first transistor structure and a second transistor structure on a semiconductor substrate, wherein the first transistor structure includes a dummy gate thereon; forming a mask on the first transistor structure; forming a metal gate on the second transistor structure; removing the mask, after the forming of the metal gate, to expose the first transistor structure; and siliciding a top portion of the dummy gate of the first transistor structure to yield a resistor. | 12-17-2015 |
Viraj V. Sardesai, Poughkeepsie, NY US
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20140113417 | CROSS-COUPLING OF GATE CONDUCTOR LINE AND ACTIVE REGION IN SEMICONDUCTOR DEVICES - Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme. | 04-24-2014 |
Viraj Y. Sardesai, Poughkeepsie, NY US
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20080272398 | CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING - A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide. | 11-06-2008 |
20090029549 | METHOD OF SILICIDE FORMATION FOR NANO STRUCTURES - A method forms a first layer over a second layer that comprises silicon. A mask is formed and patterned over the insulator layer. Then, a heavy inert gas such as Xenon (Xe) is implanted through the openings in the mask, through the insulator layer, and into the regions of the silicon layer that are below the opening in the mask. The portions of the insulator layer that are below the openings in the mask are etched away and the mask is removed. A metal or metal alloy layer is formed over the first layer and the exposed regions of the second layer. At least the second layer is heated in a silicide process such that the metal and the exposed regions of the second layer combine to form silicide regions. After this, any remaining metal material can be removed to remove to leave the silicide regions adjacent non-silicide regions of the second layer. | 01-29-2009 |
20120306093 | CONVERTING METAL MASK TO METAL-OXIDE ETCH STOP LAYER AND RELATED SEMICONDUCTOR STRUCTURE - A method includes providing a semiconductor structure including a plurality of devices; depositing a nitride cap over the semiconductor structure; forming an aluminum mask over the nitride cap, the aluminum mask including a plurality of first openings; converting the aluminum mask to an aluminum oxide etch stop layer; and performing middle-of-line fabrication processing, leaving the aluminum oxide etch stop layer in place. A semiconductor structure includes a plurality of devices on a substrate; a nitride cap over the plurality of devices; an aluminum oxide etch stop layer over the nitride cap; an inter-level dielectric (ILD) over the aluminum oxide etch stop layer; and a plurality of contacts extending through the ILD, the aluminum oxide etch stop layer and the nitride cap to the plurality of devices. | 12-06-2012 |
20130020705 | METHOD TO FORM UNIFORM SILICIDE BY SELECTIVE IMPLANTATION - Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material. | 01-24-2013 |
20130037864 | CROSS-COUPLING OF GATE CONDUCTOR LINE AND ACTIVE REGION IN SEMICONDUCTOR DEVICES - Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme. | 02-14-2013 |
20130119483 | SILICIDE CONTACTS HAVING DIFFERENT SHAPES ON REGIONS OF A SEMICONDUCTOR DEVICE - A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications. | 05-16-2013 |
20130137260 | MULTI-STAGE SILICIDATION PROCESS - A multi-stage silicidation process is described wherein a dielectric etch to expose contact regions is timed to be optimal for a highest of the contact regions. After exposing the highest of the contact regions, a silicide is formed on the exposed contact region and the dielectric is re-etched, selective to the formed silicide, to expose another contact region, lower than the highest of the contact regions, without recessing the highest of the contact regions. The process then forms a silicide on the lower contact region. The process may continue to varying depths. Each subsequent etch is performed without the use of additional masking steps. By manipulating diffusive properties of existing silicides and deposited metals, the silicides formed on contact regions with differing depths/height may comprise different compositions and be optimized for different polarity devices such as nFET and pFET devices. | 05-30-2013 |
20130181292 | LOCAL INTERCONNECTS COMPATIBLE WITH REPLACEMENT GATE STRUCTURES - After forming replacement gate structures that are embedded in a planarized dielectric layer on a semiconductor substrate, a contact-level dielectric layer is deposited over a planar surface of the planarized dielectric layer and the replacement gate structures. Substrate contact via holes are formed through the contact-level dielectric layer and the planarized dielectric layer, and metal semiconductor alloy portions are formed on exposed semiconductor materials. Gate contact via holes are subsequently formed through the contact-level dielectric layer. The substrate contact via holes and the gate contact via holes are simultaneously filled with a conductive material to form substrate contact structures and gate contact structures. The substrate contact structures and gate contact structures can be employed to provide local interconnect structures that provide electrical connections between two components that are laterally spaced on the semiconductor substrate. | 07-18-2013 |
20140154856 | Inducing Channel Strain via Encapsulated Silicide Formation - Methods of forming semiconductor structures having channel regions strained by encapsulated silicide formation. Embodiments include forming a transistor, depositing an interlevel dielectric (ILD) layer above the transistor, forming contact recesses exposing portions of source/drain regions of the transistor, forming metal-rich silicide layers on the exposed portions of the source/drain regions, forming metal contacts in the contact recesses above the metal-rich silicide layers, and converting the metal-rich silicide layer to a silicon-rich silicide layer. In other embodiments, the metal-rich silicide layers are formed on the source/drain regions prior to ILD layer deposition. Embodiments further include forming a transistor, depositing an ILD layer above the transistor, forming contact recesses exposing portions of source/drain regions of the transistor, forming metal liners in the contact recesses, forming metal fills in the contact recesses, and forming silicide layers on the source/drain regions by reacting portions of the metal liners with portions of the source/drain regions. | 06-05-2014 |
20140167176 | LOCAL INTERCONNECTS COMPATIBLE WITH REPLACEMENT GATE STRUCTURES - After forming replacement gate structures that are embedded in a planarized dielectric layer on a semiconductor substrate, a contact-level dielectric layer is deposited over a planar surface of the planarized dielectric layer and the replacement gate structures. Substrate contact via holes are formed through the contact-level dielectric layer and the planarized dielectric layer, and metal semiconductor alloy portions are formed on exposed semiconductor materials. Gate contact via holes are subsequently formed through the contact-level dielectric layer. The substrate contact via holes and the gate contact via holes are simultaneously filled with a conductive material to form substrate contact structures and gate contact structures. The substrate contact structures and gate contact structures can be employed to provide local interconnect structures that provide electrical connections between two components that are laterally spaced on the semiconductor substrate. | 06-19-2014 |
20140203371 | FINFET DEVICE FORMATION - A method includes patterning a fin on a semiconductor substrate, depositing a local trench isolation (LTI) layer on the semiconductor substrate, patterning a gate stack over a channel region of the fin and over a portion of the LTI layer, depositing a first capping layer over exposed portions of the LTI layer, performing an etching process to remove oxide material from exposed portions of the fin, and epitaxially growing a semiconductor material from exposed portions of the fin to define active regions. | 07-24-2014 |
20140284721 | FINFET DEVICE FORMATION - A method includes patterning a fin on a semiconductor substrate, depositing a local trench isolation (LTI) layer on the semiconductor substrate, patterning a gate stack over a channel region of the fin and over a portion of the LTI layer, depositing a first capping layer over exposed portions of the LTI layer, performing an etching process to remove oxide material from exposed portions of the fin, and epitaxially growing a semiconductor material from exposed portions of the fin to define active regions. | 09-25-2014 |
20150048455 | SELF-ALIGNED GATE CONTACT STRUCTURE - Embodiments of present invention provide a method of forming a semiconductor device. The method includes depositing a layer of metal over one or more channel regions of respective one or more transistors in a substrate, the layer of metal having a first region and a second region; lowering height of the first region of the layer of metal; forming an insulating layer over the first region of lowered height, the insulating layer being formed to have a top surface coplanar with the second region of the layer of metal; and forming at least one contact to a source/drain region of the one or more transistors. Structure of the semiconductor device formed thereby is also provided. | 02-19-2015 |
20150108499 | SEMICONDUCTOR DEVICES WITH GRAPHENE NANORIBBONS - Semiconductor devices with graphene nanoribbons and methods of manufacture are disclosed. The method includes forming at least one layer of Si material on a substrate. The method further includes forming at least one layer of carbon based material adjacent to the at least one layer of Si. The method further includes patterning at least one of the at least one layer of Si material and the at least one layer of carbon based material. The method further includes forming graphene on the patterned carbon based material. | 04-23-2015 |
20150200291 | FIN END SPACER FOR PREVENTING MERGER OF RAISED ACTIVE REGIONS - After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process. | 07-16-2015 |
20150249086 | THIRD TYPE OF METAL GATE STACK FOR CMOS DEVICES - A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack. | 09-03-2015 |
20150255393 | ELECTRICAL FUSE WITH BOTTOM CONTACTS - A method including forming a fuse link after a first fuse contact and a second fuse contact. The fuse link is in direct contact with both the first fuse contact and the second fuse contact. Embodiments of the invention provide an e-fuse that is capable of being connected to a device either through back end of line or by a long contact allowing for sufficient separation between the e-fuse and the device. | 09-10-2015 |
20150270179 | DIFFUSION-CONTROLLED OXYGEN DEPLETION OF SEMICONDUCTOR CONTACT INTERFACE - A device is created by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the layer of dielectric material, the opening having a bottom and exposing the silicon-containing region. A metal stack is formed within the opening. The metal stack includes at least a first metal film on the silicon-containing region and a second gettering metal film on the first metal film. The metal stack is annealed to cause oxygen to migrate from the substrate to the gettering metal film. A first liner is formed within the opening. A fill metal is deposited in the opening. | 09-24-2015 |
20150270365 | SELECTIVE DIELECTRIC SPACER DEPOSITION FOR EXPOSING SIDEWALLS OF A FINFET - Angled directional ion beams are directed to sidewalls of a gate structure that straddles at least one semiconductor fin. The directions of the angled directional ion beams are contained within a vertical plane that is parallel to the sidewalls of the at least one semiconductor. A pair of gate spacers are formed on sidewalls of the gate structure by accumulation of the deposited dielectric material from the angled directional ion beams and without use of an anisotropic etch, while the sidewalls of the semiconductor fins parallel to the directional ion beams remain physically exposed. A selective epitaxy process can be performed to form raised active regions by growing a semiconductor material from the sidewalls of the semiconductor fins. | 09-24-2015 |
20150318184 | DIRECTIONAL CHEMICAL OXIDE ETCH TECHNIQUE - A method of forming a trench in an oxide layer; where the oxide layer is formed on top of a nitride layer. The trench is formed using an iterative etching technique until the nitride layer is exposed, each iterative etching step includes; using an isotropic etching technique to remove a portion of the oxide layer, the isotropic etching technique produces a byproduct that remains along a sidewall and a bottom of the trench, then using an anisotropic etching technique to remove the salt from the bottom of the trench, leaving salt on the sidewalls of the trench. | 11-05-2015 |
20160027889 | DIFFUSION-CONTROLLED OXYGEN DEPLETION OF SEMICONDUCTOR CONTACT INTERFACE - A device is created by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the layer of dielectric material, the opening having a bottom and exposing the silicon-containing region. A metal stack is formed within the opening. The metal stack includes at least a first metal film on the silicon-containing region and a second gettering metal film on the first metal film. The metal stack is annealed to cause oxygen to migrate from the substrate to the gettering metal film. A first liner is formed within the opening. A fill metal is deposited in the opening. | 01-28-2016 |
20160035864 | FIN END SPACER FOR PREVENTING MERGER OF RAISED ACTIVE REGIONS - After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process. | 02-04-2016 |
20160035875 | FIN END SPACER FOR PREVENTING MERGER OF RAISED ACTIVE REGIONS - After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process. | 02-04-2016 |
20160035876 | FIN END SPACER FOR PREVENTING MERGER OF RAISED ACTIVE REGIONS - After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process. | 02-04-2016 |
Viraj Yashawant Sardesai, Hopewell Junction, NY US
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20120112290 | CONTROLLED CONTACT FORMATION PROCESS - A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a chemical mechanical polish (CMP) stopping layer during a CMP process used to expose the gates prior to replacement. Protective layers are then applied and etched in the formation of metal contacts. | 05-10-2012 |
20120302069 | METHOD OF PATTERNED IMAGE REVERSAL - A method of forming a reverse image pattern on a semiconductor base layer is disclosed. The method comprises depositing a transfer layer of amorphous carbon on the semiconductor base layer, depositing a resist layer on the transfer layer, creating a first pattern in the resist layer, creating the first pattern in the transfer layer, removing the resist layer, depositing a reverse mask layer, planarizing the reverse mask layer, and removing the transfer layer, thus forming a second pattern that is a reverse image of the first pattern. | 11-29-2012 |
Viraj Yashawant Sardesai, Poughkeepsie, NY US
Patent application number | Description | Published |
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20120273798 | METHOD OF FORMING SILICIDE CONTACTS OF DIFFERENT SHAPES SELECTIVELY ON REGIONS OF A SEMICONDUCTOR DEVICE - A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications. | 11-01-2012 |
20130273737 | Method for Cleaning Semiconductor Substrate - Embodiments of the invention include a method of cleaning a semiconductor substrate of a device structure and a method of forming a silicide layer on a semiconductor substrate of a device structure. Embodiments include steps of converting a top portion of the substrate into an oxide layer and removing the oxide layer to expose a contaminant-free surface of the substrate. | 10-17-2013 |
20140035045 | Method of Manufacturing Dummy Gates of a Different Material as Insulation between Adjacent Devices - Embodiments of the present invention include a semiconductor structure including two transistor structures separated by a dummy gate of a different material and methods for forming said structure. Embodiments including forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the third sacrificial gate with an insulating material. The insulating material replacing the third sacrificial gate may serve as a dummy gate to electrically isolate nearby source/drain regions. Embodiments further include forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the two sacrificial gates with metal gates while leaving the third sacrificial gate in place to serve as a dummy gate. | 02-06-2014 |
20150129939 | METHOD AND STRUCTURE FOR FORMING CONTACTS - Embodiments of the present invention provide an improved structure and method for forming high aspect ratio contacts. A horizontally formed contact etch stop layer is deposited in a narrow area where a contact is to be formed. A gas cluster ion beam (GCIB) process is used in the deposition of the horizontally formed contact etch stop layer. | 05-14-2015 |