Patent application number | Description | Published |
20090207850 | System and method for data packet transmission and reception - A system transmits a data packet from a transmitting apparatus to a receiving apparatus. The receiving apparatus includes a receive buffer, and a size specifying information transmitting unit that transmits size specifying information to the transmitting apparatus. The transmitting apparatus includes a transmit buffer, a credit storage unit that stores, as a credit, a value corresponding to a total size of all data packets stored in the receive buffer, a credit adding unit that adds a credit to the stored credit on transmitting a data packet, a credit subtracting unit that specifies a size of a read-out data packet on receiving the size specifying information, subtracts a credit corresponding to the specified size from a stored credit, and a transmission controlling unit that controls data packet transmission based on a credit stored in the credit storage unit. | 08-20-2009 |
20090249143 | SCAN CONTROL METHOD, SCAN CONTROL CIRCUIT AND APPARATUS - A scan control method for a circuit device connected with a first bus and having a test access port controller, including setting information indicating a register to be scanned in the circuit device, a number of scan shifts and a scan start via a second bus different from the first bus, and generating based on the information set, by using a sequencer, a signal replacing a test mode signal and a test reset signal transferred via the first bus during testing of the circuit device, and supplying the signal to the test access port controller. | 10-01-2009 |
20090249145 | SCAN CONTROL METHOD AND DEVICE - A scan control method of a circuit device including setting information indicating scan mode in a register is provided. The scan control method includes cutting an output of scan-out data to a test access port controller and an input of scan-in data from a data register based on information set in the register, and controlling a connection between a scan register and a data register. Each data/scan register includes data registers for the same number of chains to be scanned at the same time. Data set in one data register may be kept in all the data registers in parallel and scanned in all the scan chains in a scan-in process in the broadcast mode. The data set in the data register may be kept in the data register corresponding to the scan register and scanned in the corresponding scan chain, in a scan-in process in the parallel mode. | 10-01-2009 |
20100228869 | LINKUP STATE GENERATING METHOD, INFORMATION PROCESSING APPARATUS, AND LINKUP STATE GENERATING PROGRAM - A linkup state generating method for generating a state in which linkup is completed in first and second information processing apparatuses, the first and second information processing apparatuses each including a linkup function of, with parameter exchange, comparing parameters included in the first and second information processing apparatuses and adjusting specifications of the parameters so that the specifications of the parameters match each other, the linkup state generating method including setting, from the outside, a parameter in the first information processing apparatus so that a specification of the parameter included in the first information processing apparatus matches a specification of a parameter included in the second information processing apparatus, and sending, from the first information processing apparatus, a signal received from the second information processing apparatus to the second information processing apparatus in a manner that the second information processing apparatus recognizes that parameter exchange has been performed. | 09-09-2010 |
20110069717 | Data transfer device, information processing apparatus, and control method - A data transfer device includes a plurality of input queues, a plurality of arbitration control units provided for the respective input queues, and an input queue selecting unit that selects any one of the input queues based on a priority set for each input queue, and outputs data from the selected input queue. Each arbitration control unit includes a register that stores therein a predetermined upper limit, a counter that counts the amount of data output from a corresponding input queue, and a control circuit that, when a value of the counter becomes equal to or greater than the upper limit stored in the register, causes the input queue selecting unit to update the priority and resets the value of the counter. | 03-24-2011 |
20110283032 | ARBITRATION DEVICE - An arbitration device including: a first measuring circuit to measure a first period; a second measuring circuit to measure a second period; a second selection circuit to select and output the first period or the second period according to a first selection signal; a first control circuit to output the first selection signal according to the first period and the second period; a third selection circuit to select a third data or either the first data or the second data according to a second selection signal; a third measuring circuit to measure a third period; a fourth measuring circuit to measure a fourth period; and a second control circuit to output the second selection signal according to either the selected first period or the selected second period and the third period and the fourth period. | 11-17-2011 |
20110320900 | APPARATUS AND METHOD FOR ERROR CHECK OF TRANSMISSION DATA - An error check apparatus including, a packet protocol error check processing circuit configure to detect a protocol error of a packet, a retry control circuit configured to receive the protocol error of the packet from the packet protocol error check processing circuit, and to perform request for retry for data of the packet if the received protocol error has not been detected from a packet retransmitted by retry request, and an error notification circuit configured to notify of the protocol error of the packet to a processing unit in a higher-level layer if the protocol error is not a first protocol error for the packet. | 12-29-2011 |
20120239996 | MEMORY CONTROLLER, INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING MEMORY CONTROLLER - A memory controller which is connected to a memory module having an ECC (Error Check and Correction) function and which controls access to the memory module, the memory controller, has an error detection unit configured to detect an error bit and a position of the error bit by reading, from the memory module, information on codes of the ECCs corresponding to a plurality of read data read from the memory module, a buffer configured to temporarily store the plurality of read data, and a determination unit configured to determine, when the plurality of read data stored in the buffer include a number of data in which a correctable error is detected by the error detection unit and error detection positions of the detected data are the same as each other, that a correctable error is included in a group of the plurality of read data. | 09-20-2012 |
Patent application number | Description | Published |
20130159795 | INTEGRATED CIRCUIT, FAULT INFORMATION PROCESSING METHOD AND FAULT INFORMATION COLLECTION APPARATUS - An integrated circuit includes a fault collection section, and a plurality of modules. Each of the modules includes a fault detection section that detects a fault in the modules, a fault information generation section that generates fault information about the detected fault, a notification section that issues a fault detection notification indicating that a fault is detected to the fault collection section, and a first transmission section that transmits the fault information to the fault collection section. The fault collection section includes a specification section that specifies, based on the fault detection notification, the module from which the fault detection notification has been received first from among the modules, and an acquisition section that acquires the fault information from the module specified by the specification section. | 06-20-2013 |
20130179602 | PROCESSING SYSTEM, COMMUNICATION APPARATUS, AND PROCESSING APPARATUS - In a processing system including a processing apparatus, an input/output apparatus and communication apparatuses, the communication apparatus includes: a first instructing unit that issues a configuration change instruction in accordance with set configuration information to the processing apparatus and the input/output apparatus; and a first setting unit that, when an operation change completion notification corresponding to the configuration change instruction is received, sets the configuration information in accordance with a state established after a configuration change, and each of the processing apparatus and the input/output apparatus includes: a second setting unit that sets the configuration information in accordance with the configuration change instruction received from the communication apparatus; a second instructing unit that issues an operation change instruction in accordance with the set configuration information; and a notifying unit that, when the operation change is completed, issues an operation change completion notification to the communication apparatus. | 07-11-2013 |
20130275484 | DIVISION CIRCUIT AND MEMORY CONTROLLER - A separation circuit separates a 32-bit dividend, (e.g., 1695) into 4-bit segments and outputs 9 separated dividends. The position of each dividend counted from the dividend having the lowest bit is i. A first output circuit concatenates at the end of a dividend, 0s of number equal to an integer multiple of 4 bits. Each calculation circuit outputs an 8-bit quotient, a numerical value created by the first output circuit divided by 3(=2 | 10-17-2013 |
20130297895 | MEMORY CONTROLLER AND INFORMATION PROCESSING APPARATUS - A memory controller includes: a determination part configured to determine a type of a DIMM having a different address line topology based on SPD; a slew rate setting part configured to set a slew rate of an address signal based on the type of the DIMM determined by the determination part; and a delay setting part configured to set a data delay amount when reading/writing data. | 11-07-2013 |
20140040680 | MEMORY CONTROL DEVICE AND CONTROL METHOD - A memory controller receives a read request and also issues a patrol request at a predetermined time interval so as to determine whether any error occurs in data stored in a DIMM. Furthermore, the memory controller generates a patrol address that is the subject of the subsequently issued patrol request. When the memory controller receives a read request, the memory controller compares the patrol address with the read address that is the subject of the received read request. When the read address matches the patrol address, the memory controller cancels the issuance of the subsequent patrol request. | 02-06-2014 |