Gosset, FR
Christophe Gosset, Sainte Genevieve Des Bois FR
Patent application number | Description | Published |
---|---|---|
20090324246 | Method of Limiting the Non-Linear Phase Noise of a Phase-Modulated Optical Signal of Constant Amplitude, and an Associated Device - A non-linear phase noise limiter device limits the non-linear phase noise that affects a phase-modulated input optical signal of constant mean amplitude conveyed over a transmission line. The device is placed at a zero dispersion point of the transmission line, and it is suitable for suppressing amplitude fluctuations about a mean value in said optical signal. | 12-31-2009 |
Christophe Gosset, Perros Guirec FR
Patent application number | Description | Published |
---|---|---|
20110170104 | METHOD FOR MEASURING THE SPECTRAL PHASE OF A PERIODIC SIGNAL - The invention relates to a self-referenced device ( | 07-14-2011 |
Francois Gosset, Beuvillers FR
Patent application number | Description | Published |
---|---|---|
20130333337 | Installation for Grouping Containers Which Have a Circular or Ovoid Cross-Section and are in the Form of Packs - The invention relates to an installation for grouping containers ( | 12-19-2013 |
20140284237 | METHOD FOR ARRANGING PACKS OF CONTAINERS OF CIRCULAR OR OVAL CROSS SECTION, AND SET OF SUCH PACKS - The invention relates to a method of arranging a pack ( | 09-25-2014 |
Francois Gosset, Octeville S/mer FR
Patent application number | Description | Published |
---|---|---|
20080264818 | Pack Including a Flange Which Partially Covers a Group of Articles - The invention relates to a packet ( | 10-30-2008 |
Francois Gosset, Octeville-Sur-Mer FR
Patent application number | Description | Published |
---|---|---|
20080302692 | Article Package Comprising Partially Covering Flange and a Film Wrapping the Entire Package - A package ( | 12-11-2008 |
Irene Gosset, Le Touvet FR
Patent application number | Description | Published |
---|---|---|
20110166661 | APPARATUS FOR FITTING A SHOULDER PROSTHESIS - Method and set of surgical instruments for fitting a shoulder prosthesis, and the shoulder prosthesis. The proposed method seeks to interpose a bone graft between the previously prepared glenoid surface of a scapula of a patient's shoulder and the face of a glenoid prosthetic component opposite the articular surface. The set of instruments permit the bone graft to be taken from the upper epiphysis of the humerus, either in situ or ex vivo. | 07-07-2011 |
20120209390 | IMPLANT FOR BONE AND CARTILAGE RECONSTRUCTION - The aim of the invention is to restore the mobility of an articular end ( | 08-16-2012 |
Laurant Georges Gosset, Grenoble FR
Patent application number | Description | Published |
---|---|---|
20090273085 | CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES - The present invention relates to an integrated-circuit device that has at least one Copper-containing feature in a dielectric layer, and a diffusion-barrier layer stack arranged between the feature and the dielectric layer. The integrated-circuit device of the invention has a diffusion-barrier layer stack, which comprises, in a direction from the Copper-containing feature to the dielectric layer, a CuSiN layer and a SiN layer. This layer combination provides an efficient barrier for suppressing Copper diffusion from the feature into the dielectric layer. Furthermore, a CuSiN/SiN layer sequence provides an improved adhesion between the layers of the diffusion-barrier layer stack and the dielectric layer, and thus improves the electromigration performance of the integrated-circuit device during operation. Therefore, the reliability of device operation and the lifetime of the integrate-circuit device are improved in comparison with prior-art devices. The invention further relates to a method for fabricating such an integrated-circuit device. | 11-05-2009 |
Laurent Gosset, Toulouse FR
Patent application number | Description | Published |
---|---|---|
20100001368 | Microelectromechanical device packaging with an anchored cap and its manufacture - Integrated circuit ( | 01-07-2010 |
Laurent Gosset, Grenoble FR
Patent application number | Description | Published |
---|---|---|
20090243108 | CONTROL OF LOCALIZED AIR GAP FORMATION IN AN INTERCONNECT STACK - The present invention relates to a method for fabricating an interconnect stack of an integrated-circuit device. Air gaps are fabricated in the interconnect stack on one or more interconnect levels. The method comprises forming local etch vias ( | 10-01-2009 |
20090272565 | CONTROL OF CARBON NANOSTRUCTURE GROWTH IN AN INTERCONNECT STRUCTURE - An interconnect structure on a substrate is provided. The interconnect structure comprises electrically conductive interconnect elements on at least two interconnect levels on or above a substrate level. In the interconnect structure of the invention, at least one electrically conductive via connects a first interconnect element on one interconnect level or on the substrate level to a second interconnect element on a different interconnect level. The via extends in a via opening of a first dielectric layer and comprises an electrically conductive via material that contains electrically conductive cylindrical carbon nanostructures. At least one cover-layer segment reaches into a lateral extension of the via opening and defines a via aperture that is small enough to prevent a penetration of the carbon nanostructures through the via aperture. This structure enhances control of carbon nanostructure growth in a height direction during fabrication of the interconnect structure. | 11-05-2009 |
20100044865 | FABRICATION OF A DIFFUSION BARRIER CAP ON COPPER CONTAINING CONDUCTIVE ELEMENTS - A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:—providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;—depositing a metal layer on the exposed surface of conductive element;—inducing diffusion of metal from the metal layer into a top section of the conductive element;—removing the remaining metal layer;—letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved. | 02-25-2010 |
20100120243 | FORMATION OF A RELIABLE DIFFUSION-BARRIER CAP ON A CU-CONTAINING INTERCONNECT ELEMENT HAVING GRAINS WITH DIFFERENT CRYSTAL ORIENTATIONS - The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element. The processing improves the properties of the diffusion-barrier cap and secures a continuous formation of a diffusion-barrier layer on the interconnect element. | 05-13-2010 |
Laurent G. Gosset, Grenoble FR
Patent application number | Description | Published |
---|---|---|
20090321946 | PROCESS FOR FABRICATING AN INTEGRATED ELECTRONIC CIRCUIT INCORPORATING A PROCESS REQUIRING A VOLTAGE THRESHOLD BETWEEN A METAL LAYER AND A SUBSTRATE - A process for fabricating an electronic integrated circuit comprising a multi-layer interconnect stack. A structure ( | 12-31-2009 |
Laurent Georges Gosset, Grenoble FR
Patent application number | Description | Published |
---|---|---|
20100059889 | ADHESION OF DIFFUSION BARRIER ON COPPER-CONTAINING INTERCONNECT ELEMENT - The present invention relates to a method for fabricating a semiconductor device. For improving the adhesion between a copper-containing interconnect element and a diffusion barrier on top of it, a first dielectric layer ( | 03-11-2010 |
Laurent-Georges Gosset, Toulouse FR
Patent application number | Description | Published |
---|---|---|
20100090346 | INTEGRATION OF SELF-ALIGNED TRENCHES IN-BETWEEN METAL LINES - The present invention provides an improved method of forming air cavities to overcome IC via-misalignment issues. The method of forming air cavity trenches in-between metal lines of an integrated circuit includes the steps of partially removing ( | 04-15-2010 |
20110080686 | MIM CAPACITOR - A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface. | 04-07-2011 |
20130286540 | MIM CAPACITOR - A method of forming a metal- insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface. | 10-31-2013 |
Laurent-Georges Gosset, Crolles FR
Patent application number | Description | Published |
---|---|---|
20090218699 | METAL INTERCONNECTS IN A DIELECTRIC MATERIAL - A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material. | 09-03-2009 |
20100038797 | CONTROLLING LATERAL DISTRIBUTION OF AIR GAPS IN INTERCONNECTS - Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect stack as being specific to air cavity introduction, with the defined portion being smaller than the surface of the substrate. At least one metal track is produced within the interconnect stack, and there is deposited at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack. There is defined at least one trench area surrounding the defined portion and forming at least one trench, and a hard mask layer is deposited to coat the trench. At least one air cavity is formed below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant. | 02-18-2010 |
Philippe Gosset, Magny-Les-Hameaux FR
Patent application number | Description | Published |
---|---|---|
20150239473 | Vehicle guidance system and corresponding method - The guidance system ( | 08-27-2015 |