Shi-Bai
Shi-Bai Chen, Hsinchu County TW
Patent application number | Description | Published |
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20090294944 | SEMICONDUCTOR DEVICE ASSEMBLY AND METHOD THEREOF - A semiconductor device assembly includes a first semiconductor die, a second semiconductor die, at least one semiconductor package component or another semiconductor die, a first conductive element and a second conductive element. The first semiconductor die includes at least one bonding pad. The second semiconductor die includes a bonding pad module. The first conductive element is coupled between the bonding pad module of the second semiconductor die and the bonding pad of the first semiconductor die, and the second conductive element is coupled between the bonding pad module of the second semiconductor die and the semiconductor package component or the another semiconductor die, wherein the first semiconductor die is coupled to the semiconductor package component or the another semiconductor die via the bonding pad and the bonding pad module and the first and second conductive elements. | 12-03-2009 |
20100059867 | INTEGRATED CIRCUIT CHIP WITH SEAL RING STRUCTURE - An integrated circuit chip includes an analog and/or RF circuit block, a digital circuit, and a seal ring structure surrounding and protecting the analog and/or RF circuit block. The seal ring structure comprises a continuous outer seal ring, and a discontinuous inner seal ring divided into at least a first portion and a second portion. The second portion is situated in front of the analog and/or RF circuit block for shielding a noise from interfering the analog and/or RF circuit block. | 03-11-2010 |
20100102421 | INTEGRATED CIRCUIT CHIP WITH SEAL RING STRUCTURE - An integrated circuit chip includes an analog and/or RF circuit block and a seal ring structure surrounding the analog and/or RF circuit block. The seal ring structure comprises a continuous outer seal ring and an inner seal ring, wherein the inner seal ring comprises a gap that is situated in front of the analog and/or RF circuit block. | 04-29-2010 |
20120009734 | SEMICONDUCTOR DEVICE ASSEMBLY AND METHOD THEREOF - A semiconductor device assembly includes a first semiconductor die, a second semiconductor die, at least one semiconductor package component or another semiconductor die, a first conductive element and a second conductive element. The first semiconductor die includes at least one bonding pad. The second semiconductor die includes a bonding pad module. The first conductive element is coupled between the bonding pad module of the second semiconductor die and the bonding pad of the first semiconductor die, and the second conductive element is coupled between the bonding pad module of the second semiconductor die and the semiconductor package component or the another semiconductor die, wherein the first semiconductor die is coupled to the semiconductor package component or the another semiconductor die via the bonding pad and the bonding pad module and the first and second conductive elements. | 01-12-2012 |
20120154102 | ELECTRICAL FUSE STRUCTURE - An electrical fuse structure includes a first metal strip having a first width W | 06-21-2012 |
Shi-Bai Chen, Tai-Chung TW
Patent application number | Description | Published |
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20090273055 | Fuse Structure - An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer. | 11-05-2009 |
20120196434 | E-fuse Structure Design in Electrical Programmable Redundancy for Embedded Memory Circuit - An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer. | 08-02-2012 |
20140218100 | A New E-fuse Structure Design in Electrical Programmable Redundancy for Embedded Memory Circuit - An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer. | 08-07-2014 |
Shi-Bai Chen, Taichung City TW
Patent application number | Description | Published |
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20090243032 | ELECTRICAL FUSE STRUCTURE - An e-fuse structure includes a cathode block; a plurality of cathode contact plugs on the cathode block; an anode block; a plurality of anode contact plugs on the cathode block; and a fuse link connecting the cathode block with the anode block, wherein a front row of the cathode contact plugs is disposed in close proximity to the fuse link thereby inducing a high thermal gradient at an interface between the cathode block and the fuse link. | 10-01-2009 |
20110108974 | POWER AND SIGNAL DISTRIBUTION OF INTEGRATED CIRCUITS - A packaged integrated circuit is provided comprising a first semiconductor die, a second semiconductor die, and a bonding wire. The first semiconductor die has a first internal bonding pad electrically connected to the package. The second semiconductor die has a second internal bonding pad located in an internal portion of the second semiconductor die. The second internal bonding pad is electrically connected to the first internal bonding pad through the first bonding wire. | 05-12-2011 |