Patent application number | Description | Published |
20090273030 | Semiconductor Device with a Trench Isolation and Method of Manufacturing Trenches in a Semiconductor Body - A low cost integration method for a plurality of deep isolation trenches on the same chip is provided. The trenches have an additional n-type or p-type doped region surrounding the trench—silicon interface. Providing such variations of doping the trench interface is achieved by using implantation masking layers or doped glass films structured by a simple resist mask. By simple layout variation of the top dimension of the trench various trench depths at the same time can be ensured. Using this method, wider trenches will be deeper and smaller trenches will be shallower. | 11-05-2009 |
20090321822 | HIGH-VOLTAGE TRANSISTOR WITH IMPROVED HIGH STRIDE PERFORMANCE - A high voltage NMOS transistor is disclosed where the p-doped body is isolated against the p-doped substrate by a DN well having a pinch-off region where the depth of the DN-well is at minimum. By the forming space charge region at raising drain potentials a shielding of the drain potential results because the space charge region touches the field oxide between source and drain at the pinch-off region. An operation at the high side at enhanced voltage levels is possible. | 12-31-2009 |
20100308404 | Field-Effect Transistor and Method for Producing a Field-Effect Transistor - A semiconductor body ( | 12-09-2010 |
20110117714 | Integration of Multiple Gate Oxides with Shallow Trench Isolation Methods to Minimize Divot Formation - A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer. | 05-19-2011 |
20130168769 | P-CHANNEL LDMOS TRANSISTOR AND METHOD OF PRODUCING A P-CHANNEL LDMOS TRANSISTOR - The p-channel LDMOS transistor comprises a semiconductor substrate ( | 07-04-2013 |
20130207180 | SYMMETRIC LDMOS TRANSISTOR AND METHOD OF PRODUCTION - The symmetric LDMOS transistor comprises a semiconductor substrate ( | 08-15-2013 |