Patent application number | Description | Published |
20130070973 | FACE RECOGNIZING APPARATUS AND FACE RECOGNIZING METHOD - According to one embodiment, a face recognizing apparatus includes: a storage unit; an input unit; a face detector; an extractor; and a recognizing unit. The storage unit stores face feature information on a face feature of each person. The input unit receives image information including at least a face of a person. The face detector detects a face region of the face of the person from the image information received by the input unit. The extractor extracts face feature information on a face feature from the face region detected by the face detector. The recognizing unit recognizes the person in the image information received by the input unit based on the feature information extracted by the extracting unit and the face feature information stored in the storage unit. | 03-21-2013 |
20130243278 | BIOLOGICAL INFORMATION PROCESSOR - According to one embodiment, a biological information processor includes: an area detection unit configured to detect an area in which a person is displayed from image information; a feature extraction unit configured to extract feature information based on a characteristic portion of a person from the area detected by the area detection unit from the image information; and a determination unit configured to determine an extraction precision indicating whether or not the characteristic portion of the person can be extracted, with respect to the feature information extracted by the feature extraction unit based on a position of the characteristic portion. | 09-19-2013 |
20140079299 | PERSON RECOGNITION APPARATUS AND METHOD THEREOF - According to one embodiment, an apparatus includes input unit, detecting unit, extraction unit, storage, selection unit, determination unit, output unit, and setting unit. The selection unit selects operation or setting modes. In operation mode, it is determined whether captured person is preregistered person. In setting mode, threshold for the determination is set. The determination unit determines, as registered person and when operation mode is selected, person with degree of similarity between extracted facial feature information and stored facial feature information of greater than or equal to threshold. The setting unit sets, when setting mode is selected, threshold based on first and second degrees of similarity. First degree of similarity is degree of similarity between facial feature information of the registered person and the stored facial feature information. Second degree of similarity is degree of similarity between facial feature information of person other than registered person and stored facial feature information. | 03-20-2014 |
Patent application number | Description | Published |
20090060292 | IMAGE INPUT APPARATUS, AND IMAGE INPUT METHOD - The image input apparatus performs detection of a facial area of a person based on an input image. The image input apparatus compiles information of a position where the facial area is detected within a specified time and manages as a map. From the map, the image input apparatus specifies the area where the instability of the person facial area detection occurs, namely, the area where there is a case that the facial area is not detected among the areas where a facial area is normally to be detected. The image input apparatus controls adjustment factors of a camera so that accurate detection of the facial area is performed at the specified area. | 03-05-2009 |
20090087041 | PERSON AUTHENTICATION APPARATUS AND PERSON AUTHENTICATION METHOD - A face authentication apparatus includes a high tone image acquiring section, a tone converting section, a face characteristic extracting section and a face collation section. The high tone image acquiring section acquires a high tone image containing the face of a walker. The tone converting section converts the acquired high tone image to a low tone image by tone conversion processing which optimizes the brightness of a face area in the high tone image acquired by the high tone image acquiring section. The face characteristic extracting section executes an extraction processing for the face characteristic information based on the low tone image whose brightness is optimized by the tone converting section. Further, the face collation section executes face collation processing based on the low tone image whose brightness is optimized by the tone converting section. | 04-02-2009 |
20090324020 | PERSON RETRIEVAL APPARATUS - In a person retrieval apparatus, a plurality of extraction processing sections each extract personal biometric information from images taken by a plurality of cameras. A quality determination section determines a quality of each piece of biometric information extracted by the extraction processing sections. A reliability level setting section sets a reliability level to each piece of biometric information on the basis of the quality determined by the quality determination section. The biometric information extracted by the extraction processing sections and the reliability level set by the reliability level setting section are stored in a memory. In this state, in the person retrieval apparatus, the face retrieval section performs person retrieval processing on each piece of biometric information stored in the memory in descending order of the reliability level corresponding to each piece of biometric information. | 12-31-2009 |
20110074970 | IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD - According to one embodiment, an image processing apparatus comprises a plurality of image input modules configured to input images, a detection module configured to detect object regions from an image input by any image input module, a feature extracting module configured to extract feature values from any object regions detected by the detecting module, and a control module configured to control processes the detection module and feature extracting module perform on the images input by the plurality of image input modules, in accordance with the result of detection performed by the detection module. | 03-31-2011 |
20120140982 | IMAGE SEARCH APPARATUS AND IMAGE SEARCH METHOD - According to one embodiment, an image search apparatus includes, an image input module which is input with an image, an event detection module which detects events from the input image input by the image input module, and determines levels, depending on types of the detected events, an event controlling module which retains the events detected by the event detection module, for each of the levels, and an output module which outputs the events retained by the event controlling module, for each of the levels. | 06-07-2012 |
20120308090 | FACIAL IMAGE SEARCH SYSTEM AND FACIAL IMAGE SEARCH METHOD - According to one embodiment, a facial image search system including attribute discrimination module configured to discriminate attribute based on facial feature extracted, a plurality of search modules configured to store facial feature as database in advance, add facial feature extracted to database, calculate degree of similarity between facial feature extracted and facial feature contained in database, setting module configured to generate setting information by associating with any attribute with information indicating search module, and control module configured to identify one or a plurality of search modules based on setting information and attribute and transmit facial feature extracted by feature extraction module to identified search modules. | 12-06-2012 |
20120321145 | FACIAL IMAGE SEARCH SYSTEM AND FACIAL IMAGE SEARCH METHOD - According to one embodiment, a facial image search system including, search module configured to calculate degree of similarity between facial features extracted by feature extraction module and facial features contained in database and output search result based on calculated degree of similarity, measuring module configured to measure amount of search result output by search module, and selection module configured to sort out search result output by search module if amount of search result measured by measuring module is equal to or more than preset threshold. | 12-20-2012 |
20130050502 | MOVING OBJECT TRACKING SYSTEM AND MOVING OBJECT TRACKING METHOD - A moving object tracking system includes an input unit, a detection unit, a creating unit, a weight calculating unit, a calculating unit, and an output unit. The detection unit detects all tracking target moving objects from each of input images input. The creating unit creates a combination of a path that links each moving object detected in a first image to each moving object detected in a second image, a path that links each moving object detected in the first image to an unsuccessful detection in the second image, and a path that links an unsuccessful detection in the first image to each moving object detected in the second image. The calculating unit calculates a value for the combination of the paths to which weights are allocated. The output unit outputs a tracking result. | 02-28-2013 |
Patent application number | Description | Published |
20150206590 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile semiconductor memory device and a controller. The system includes the nonvolatile semiconductor memory device including a plurality of memory cells; and the controller configured to control one of read operation, write operation, and a use frequency of the read operation or the write operation on the nonvolatile semiconductor memory device, and configured to change controlling for a memory cell belonging to a first group of the memory cells and to change controlling for a memory cell belonging to a second group located on an upper side or a lower side of the memory cell belonging to the first group. | 07-23-2015 |
20160049204 | MEMORY SYSTEM AND METHOD OF CONTROLLING NON-VOLATILE MEMORY - According to one embodiment, a controller groups a plurality of memory cells in each of the pages into a plurality of groups. The plurality of groups includes a first group and a second group. In a case of reading data from a first page, The controller performs first reading. The first reading includes reading data from the first page by using a first operation parameter for the first group. The controller performs second reading. The second reading includes reading data from the first page by using a second operation parameter for the second group. The controller merges first read data and second read data, and return the merged data as read data read from the first page. The first read data is acquired by the first reading. The second read data is acquired by the second reading. | 02-18-2016 |
20160077913 | METHOD OF CONTROLLING NONVOLATILE MEMORY - According to an embodiment, The control method includes reading a plurality of first pages in parallel on the basis of respectively different operation parameters. each of the first pages is respectively included in a plurality of first blocks. Each of the operation parameters includes a read voltage. The control method includes performing error correction on each of read data, and selecting one operation parameter out of the plurality of different operation parameters based on a result of the error correction. | 03-17-2016 |
Patent application number | Description | Published |
20140270370 | PERSON RECOGNITION APPARATUS AND PERSON RECOGNITION METHOD - A person recognition apparatus is disclosed that includes an image input unit, a face detection unit in which a face is expressed from the inputted image data, as a score which takes a value in accordance with facial likeness, a facial feature point detection unit, a feature extraction unit, a feature data administrative unit, a person identification unit to calculate similarity between the amount calculated by the feature extraction unit and the amount stored in the feature data administrative unit, a number of candidates calculation unit which displays the images stored in descending order of the similarity, and calculates a score from the face detection unit and the facial feature point detection unit, a candidate confirmation unit in which images displayed in descending order of the similarity are subjected to visual inspection. | 09-18-2014 |
20150113632 | IDENTITY AUTHENTICATION SYSTEM - According to one embodiment, an identity authentication system includes a detecting unit that detects an identity theft by determining whether a photographing target is a living body or a non-living body, a collating unit that performs identity collation based on a photographed image, and a control unit that controls execution timing of a detection process performed by the detecting unit and an identity collating processing performed by the collating unit and, in a case where the detection performed by the detecting unit is performed for a first number of times, performs the collation process performed by the collating unit, wherein the first number of times is set in consideration of a tradeoff between a required intensity of security and convenience of a user using the identity authentication system. | 04-23-2015 |
Patent application number | Description | Published |
20100241795 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 09-23-2010 |
20110055466 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 03-03-2011 |
20110082968 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 04-07-2011 |
20120072649 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 03-22-2012 |
20120179865 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 07-12-2012 |
20120250420 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit performs a read operation of reading data held in a memory-cell by supplying a selected word-line with a read voltage that is a voltage between the lower limit and the upper limit of a plurality of threshold-voltage distributions provided to the memory-cell. The control circuit also performs a verify operation of determining whether a write operation is completed by supplying a selected word-line with a verify voltage higher than the read voltage to read the memory cell. The control circuit then performs a data variation determination operation of determining whether the memory-cells connected to a selected word-line each have a threshold voltage equal to or less than a certain value to determine, from among the plurality of memory cells connected to the selected word-line, whether the number of memory cells where data variation has occurred is not less than a certain number. | 10-04-2012 |
20150248322 | MEMORY CONTROLLER AND MEMORY SYSTEM - According to one embodiment, a memory controller includes a controller that is configured to, when notified of an error by one of memory chips at a time of power supply startup, transmit a first command including an address to the memory chip by which the error was notified, when notified of a normal end by the memory chip in which the first command was received, transmit a second command including an address to the memory chip by which the normal end was notified. | 09-03-2015 |
Patent application number | Description | Published |
20090144484 | MEMORY SYSTEM AND MEMORY CHIP - A memory system includes a memory which asserts a high-power-consumption operation output when an amount of the power consumption is high in internal operations in respective operations, and a controller which has an interface function between a host and the memory and receives the high-power-consumption operation output. The controller switches an operation mode thereof to a low power consumption mode when the high-power-consumption operation output is asserted. | 06-04-2009 |
20120320682 | Semiconductor Memory System Including A Plurality Of Semiconductor Memory Devices - A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current. | 12-20-2012 |
20140063973 | SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES - A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current. | 03-06-2014 |
20150039921 | MEMORY SYSTEM AND MEMORY CHIP - A memory system includes a memory which asserts a high-power-consumption operation output when an amount of the power consumption is high in internal operations in respective operations, and a controller which has an interface function between a host and the memory and receives the high-power-consumption operation output. The controller switches an operation mode thereof to a low power consumption mode when the high-power-consumption operation output is asserted. | 02-05-2015 |
20150071004 | SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES - A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current. | 03-12-2015 |
Patent application number | Description | Published |
20090127666 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND PHASE SHIFT MASK - A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance. | 05-21-2009 |
20100240211 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND PHASE SHIFT MASK - A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device. | 09-23-2010 |
Patent application number | Description | Published |
20080199699 | PTFE POWDER AND METHOD OF PRODUCING PTFE MOLDING POWDERS - This invention provides a polytetrafluoroethylene powder capable of giving moldings which are improved in surface roughness Ra tensile strength and/or tensile elongation as compared with the prior art ones and can be excellent in dielectric breakdown strength and, further, can be excellent, if desired, in apparent density and/or powder flowability as well, and a method of producing a polytetrafluoroethylene molding powder. | 08-21-2008 |
20100087599 | FLUORORESIN COMPOSITION, FLUORORESIN MOLDED ARTICLE AND METHOD FOR PRODUCING THE SAME - The invention provides a fluororesin composition capable of providing a molded article having low relative dielectric constant, excellent in a temperature stability and causing only small transmission losses. The invention is a fluororesin composition wherein a rate of change in relative dielectric constant between 25° C. and 80° C. of a molded article produced therefrom under a standard condition is not greater than 0.2%. | 04-08-2010 |
20120227999 | CABLE, CABLE DUCT AND METHODS FOR MANUFACTURING CABLE AND CABLE DUCT - The present invention provides an electric wire having excellent weather resistance and durability. The present invention relates to: an electric wire, comprising: a conductor; an insulating layer formed around the periphery of the conductor; and an outer layer formed around the periphery of the insulating layer, wherein the outer layer is formed by application of a weatherproof coating material; and a production method thereof. | 09-13-2012 |
20150158988 | MODIFIED FLUORINE-CONTAINING COPOLYMER, FLUORINE RESIN MOLDED ARTICLE, AND METHOD FOR MANUFACTURING FLUORINE RESIN MOLDED ARTICLE - The present invention aims to provide a modified fluorine-containing copolymer excellent in crack resistance, a fluororesin molded article, and a method of producing a fluororesin molded article. The present invention includes a modified fluorine-containing copolymer consisting only of tetrafluoroethylene units and perfluoro(alkyl vinyl ether) units. The copolymer is modified by irradiation with radiation at an irradiation temperature not higher than the melting point of the copolymer but not lower than 200° C. | 06-11-2015 |
Patent application number | Description | Published |
20080222434 | Method of power-aware job management and computer system - Provided is a method used in a computer system which includes at least one host computer, the method including managing a job to be executed by the host computer and a power supply of the host computer, the method including the procedures of: receiving the job; storing the received job; scheduling an execution plan for the stored job; determining, based on the execution plan of the job, a timing to execute power control of the host computer; determining a host computer to execute the power control when the determined timing to execute the power control is reached; controlling the power supply of the determined host computer; and executing the scheduled job. | 09-11-2008 |
20090106499 | Processor with prefetch function - Non-speculatively prefetched data is prevented from being discarded from a cache memory before being accessed. In a cache memory including a cache control unit for reading data from a main memory into the cache memory and registering the data in the cache memory upon reception of a fill request from a processor and for accessing the data in the cache memory upon reception of a memory instruction from the processor, a cache line of the cache memory includes a registration information storage unit for storing information indicating whether the registered data is written into the cache line in response to the fill request and whether the registered data is accessed by the memory instruction. The cache control unit sets information in the registration information storage unit for performing a prefetch based on the fill request and resets the information for accessing the cache line based on the memory instruction. | 04-23-2009 |
20090113404 | Optimum code generation method and compiler device for multiprocessor - A method of generating optimum parallel codes from a source code for a computer system configured of plural processors that share a cache memory or a main memory is provided. A preset code is read and operation amounts and process contents are analyzed while distinguishing dependence and independence among processes from the code. Then, the amount of data to be reused among processes is analyzed, and the amount of data that accesses the main memory is analyzed. Further, upon the reception of a parallel code generation policy inputted by a user, the processes of the code are divided, and while estimating an execution cycle from the operation amount and process contents thereof, the cache use of the reuse data, and the main memory access data amount, a parallelization method with which the execution cycle becomes shortest is executed. | 04-30-2009 |
20090172288 | Processor having a cache memory which is comprised of a plurality of large scale integration - To provide an easy way to constitute a processor from a plurality of LSIs, the processor includes: a first LSI containing a processor; a second LSI having a cache memory; and information transmission paths connecting the first LSI to a plurality of the second LSIs, in which the first LSI contains an address information issuing unit which broadcasts, to the second LSIs, via the information transmission paths, address information of data, the second LSI includes: a partial address information storing unit which stores a part of address information; a partial data storing unit which stores data that is associated with the address information; and a comparison unit which compares the address information broadcast with the address information stored in the partial address information storing unit to judge whether a cache hit occurs, and the comparison units of the plurality of the second LSIs are connected to the information transmission paths. | 07-02-2009 |
20100064070 | DATA TRANSFER UNIT FOR COMPUTER - In order to improve throughput by suppressing contention of hardware resources in a computer to which a data transfer unit is coupled, a control unit for transferring data between a first interface coupled to the computer and a second interface coupled to a memory transaction issuing unit for issuing, when one of the first interface and the second interface receives an access request to a memory of the computer, a memory transaction for the main memory to the first interface, the first interface includes a plurality of interfaces coupled in parallel to the computer, and the control unit further includes a memory transaction distribution unit for extracting an address of the main memory, which is contained in the memory transaction issued by the memory transaction issuing unit, and selecting an interface having address designation information set therein, which corresponds to the extracted address to transmit the memory transaction. | 03-11-2010 |
Patent application number | Description | Published |
20080284004 | SEMICONDUCTOR DEVICE, SUBSTRATE, EQUIPMENT BOARD, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR CHIP FOR COMMUNICATION - A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting and receiving signals to and from a second substrate, input-output circuits disposed on the first region or the second region, the input-out circuits corresponding to the first communication units, and a control circuit for controlling input to and output from the input-output circuits disposed on the first region or the second region of the first substrate. Each of the input-output circuits includes an output circuit for outputting a signal to a second communication unit of the second substrate corresponding to the first communication unit and an input unit for receiving a signal sent from the corresponding second communication unit. | 11-20-2008 |
20080290508 | SEMICONDUCTOR DEVICE, SUBSTRATE, EQUIPMENT BOARD, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR CHIP FOR COMMUNICATION - A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting and receiving signals to and from a second substrate, input-output circuits disposed on the first region or the second region, the input-out circuits corresponding to the first communication units, and a control circuit for controlling input to and output from the input-output circuits disposed on the first region or the second region of the first substrate. Each of the input-output circuits includes an output circuit for outputting a signal to a second communication unit of the second substrate corresponding to the first communication unit and an input unit for receiving a signal sent from the corresponding second communication unit. | 11-27-2008 |
20080315386 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor package, a second semiconductor package. The first semiconductor package includes a first semiconductor package base having a first cavity formed therein, a first mount component mounted in the first cavity, and a first magnet disposed on the first semiconductor package base. The second semiconductor package includes a second semiconductor package base having a second cavity formed therein, a second mount component mounted in the second cavity, and a second magnet disposed on the second semiconductor package base so as to adsorb the first magnet. The first semiconductor package and the second semiconductor package are stacked by an adsorption of magnetic force between the first magnet and the second magnet. | 12-25-2008 |
20110233702 | SEMICONDUCTOR APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, METHOD OF DESIGNING SEMICONDUCTOR APPARATUS, AND ELECTRONIC APPARATUS - A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via. | 09-29-2011 |
20120293698 | SEMICONDUCTOR DEVICE, SOLID-STATE IMAGE SENSOR AND CAMERA SYSTEM - The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip | 11-22-2012 |
20130062504 | SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND CAMERA SYSTEM - Disclosed herein is a solid state imaging device including a support substrate; an imaging semiconductor chip having a pixel array disposed on the support substrate; and an image processing semiconductor chip disposed on the support substrate, wherein the imaging semiconductor chip and the image processing semiconductor chip are connected by through-vias, and interconnects formed on the support substrate. | 03-14-2013 |
20150312500 | SEMICONDUCTOR DEVICE, SOLID-STATE IMAGE SENSOR AND CAMERA SYSTEM - The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip | 10-29-2015 |
Patent application number | Description | Published |
20130320475 | SEMICONDUCTOR APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, METHOD OF DESIGNING SEMICONDUCTOR APPARATUS, AND ELECTRONIC APPARATUS - A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via. | 12-05-2013 |
20150108599 | SEMICONDUCTOR APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, METHOD OF DESIGNING SEMICONDUCTOR APPARATUS, AND ELECTRONIC APPARATUS - A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via. | 04-23-2015 |
20160133665 | SEMICONDUCTOR APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, METHOD OF DESIGNING SEMICONDUCTOR APPARATUS, AND ELECTRONIC APPARATUS - A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via. | 05-12-2016 |
Patent application number | Description | Published |
20110033997 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a gate insulating film over a semiconductor substrate, forming a silicon film over the gate insulating film, forming a resist pattern over the silicon film, etching the silicon film to form a protrusion portion of the silicon film, forming a dummy film over the silicon film, etching the dummy film so that the dummy film is partially remained on sidewalls of the protrusion portion, etching the silicon film using the remaining dummy film to form a gate electrode, and performing ion implantation into the semiconductor substrate to form source/drain regions. | 02-10-2011 |
20120161230 | MOS TRANSISTOR AND FABRICATION METHOD THEREOF - A disclosed MOS transistor has a drain region offset from a gate electrode structure, wherein the gate electrode structure includes at least a first gate electrode and a second gate electrode such that the second gate electrode is located at the drain side of the first gate electrode and the second gate electrode is isolated from the first gate electrode by an insulation film, and wherein the first and second gate electrodes are formed respectively on a first gate insulation film and a second gate insulation film having an increased thickness as compared with the first gate insulation film. | 06-28-2012 |
20120193709 | MOS TRANSISTOR AND FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A high-voltage MOS transistor has a semiconductor substrate formed with a first well of a first conductivity type in which a drain region and a drift region are formed and a second well of a second, opposite conductivity type in which a source region and a channel region are formed, a gate electrode extends over the substrate from the second well to the first well via a gate insulation film, wherein there is formed a buried insulation film in the drift region underneath the gate insulation film at a drain edge of the gate electrode, there being formed an offset region in the semiconductor substrate between the channel region and the buried insulation film, wherein the resistance of the offset region is reduced in a surface part thereof by being introduced with an impurity element of the first conductivity type with a concentration exceeding the first well. | 08-02-2012 |
Patent application number | Description | Published |
20120319182 | SEMICONDUCTOR DEVICE PRODUCTION METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device production method includes: forming in a silicon substrate first and second region of first and second conductivity type in contact with each other; forming a gate electrode above the first and the second region; forming an insulation film covering part of the gate electrode and part of the second region; forming a source region and a drain region of the second conductivity type; forming interlayer insulation film covering the gate electrode and the insulation film; and forming in the interlayer insulation film first, second and third contact hole reaching the source region, the drain region, and the gate electrode, respectively, and at least one additional hole reaching the insulation film, and forming a conductive film in the first, the second, and the third contact hole and the additional hole to form first, second and third electrically conductive via and electrically conductive member. | 12-20-2012 |
20140048858 | SEMICONDUCTOR DEVICE - A semiconductor device including a silicon substrate including a first region and a second region; a gate electrode above the first region and the second region; an insulation film extending from the gate electrode to the second region to cover part of the gate electrode and part of the second region; a source region and a drain region formed in the silicon substrate, silicide formed on the source region, on the drain region, and on the gate electrode; an interlayer insulation film formed above the gate electrode and the insulation film; a first electrically conductive via formed in the interlayer insulation film, a second electrically conductive via formed in the interlayer insulation, and a third electrically conductive via formed in the interlayer insulation and electrically connecting to the gate electrode; and at least one electrically conductive member formed on the insulation film in the interlayer insulation film. | 02-20-2014 |
Patent application number | Description | Published |
20090028421 | IMAGING CHARACTERISTICS FLUCTUATION PREDICTING METHOD, EXPOSURE APPARATUS, AND DEVICE MANUFACTURING METHOD - A method for predicting imaging characteristics fluctuation of a projection optical system in an exposure apparatus which projects a pattern formed on a mask onto a photosensitive substrate through the projection optical system is provided. In a measurement step, the projection optical system is irradiated with exposure light under a first exposure condition to measure first imaging characteristics fluctuation of the projection optical system. Then, before an imaging characteristics value is restored to an initial value at the start of irradiation after irradiation is stopped, the projection optical system is irradiated with the exposure light under a second exposure condition to measure second imaging characteristics fluctuation of the projection optical system. Approximate expressions of the measured first and second imaging characteristics fluctuations are calculated based on an imaging characteristics model. | 01-29-2009 |
20090147231 | SCANNING EXPOSURE APPARATUS AND METHOD OF MANUFACTURING DEVICE - A scanning exposure apparatus according to this invention has a light source which can change the central wavelength of exposure light to undergo pulsed oscillation, and scan-exposes a substrate with slit-like exposure light while periodically changing the central wavelength in synchronism with the pulsed oscillation of the exposure light. The scanning exposure apparatus includes a controller which controls the light source so that integrated values Sws and Swl obtained by integrating the intensity of the exposure light for each wavelength in the scanning direction in a short-wavelength range and long-wavelength range, respectively, assuming a target central wavelength as a reference satisfy: | 06-11-2009 |
20120152080 | METHOD OF MANUFACTURING BLAZED DIFFRACTIVE GRATING AND METHOD OF MANUFACTURING MOLD FOR MANUFACTURING BLAZED DIFFRACTIVE GRATING - A method of manufacturing a blazed diffractive grating includes a first step of forming a first groove having a first surface and a second surface by moving, in the first direction at a first position in the second direction, a cutting tool having a first cutting blade and a second cutting blade to cut the object; a second step of forming a second groove by moving, in the first direction at a second position separated from the first position in the second direction by a grating pitch, the cutting tool to cut the object; and a third step of forming a blazed surface of the first groove using the first cutting blade by moving, in the first direction at a third position between the first position and the second position, the cutting tool to cut the first surface of the first groove. | 06-21-2012 |
20120156967 | MANUFACTURING METHOD OF DIFFRACTION GRATING - A manufacturing method of a Blazed diffraction grating configured to diffract incident light and made of a CdTe or CdZnTe crystal material includes the step of forming a plurality of grating grooves in a processed surface of a work through machining using a processing machine for the Blazed diffraction grating. The forming step forms the grating grooves so that among surfaces of gratings formed by the forming step, a surface that receives the incident light most is set to a (110) plane as a crystal orientation of the crystal material. | 06-21-2012 |
20120229904 | MANUFACTURING METHOD OF DIFFRACTION GRATING - A method for manufacturing a diffraction grating having a plurality of grating grooves that extends in parallel in a direction includes a first cutting processing step of moving, in the direction, a work and a cutting tool having a first blade and a second blade relatively to each other, and of forming a first surface of the grating groove in the work through cutting processing using the first blade of the cutting tool, and a second cutting step of moving, in the direction, the work and the cutting tool relatively to each other after the first cutting processing step, so that the first blade does not contact the first surface formed by the first cutting processing step, and of forming a second surface of the grating groove in the work through cutting processing using the second blade of the cutting tool. | 09-13-2012 |
20130089117 | ECHELLE DIFFRACTION GRATING, EXCIMER LASER, MANUFACTURING METHOD OF ECHELLE DIFFRACTION GRATING, AND ArF EXCIMER LASER - An Echelle diffraction grating has a Littrow configuration. Each grating includes a resin layer made of light curing resin and having a thickness between 2 μm and 10 μm, and a reflective coating layer formed on the resin layer, having a thickness between 120 nm and 500 nm, and made of aluminum. An apex angle between a blazed surface and a counter surface is between 85° and 90°. A first blaze angle is an angle that maximizes diffraction efficiency of a set blazed order for incident light of a wavelength of 193.3 nm. A blaze angle has an initial value of a second blaze angle smaller than the first blaze angle. 0.25°≦bd−ba≦1.2° is satisfied where bd denotes the first blaze angle and ba denotes the second blaze angle. | 04-11-2013 |
20130089118 | ECHELLE DIFFRACTION GRATING AND ITS MANUFACTURING METHOD, EXCIMER LASER AND ITS MANUFACTURING METHOD - A manufacturing method for an excimer laser that includes a reflective Echelle diffraction grating includes obtaining information of a wavelength of a light source, a blazed order, a repetitive pitch of the grating, a material of the grating, and a predefined orientation ratio B/A that is a ratio between that a diffraction efficiency A of the blazed order and a diffraction efficiency Bb of an order lower by one order than the blazed order, and determining an initial value of a blaze angle based upon these pieces of information. | 04-11-2013 |
20130342908 | METHOD OF MANUFACTURING A DIFFRACTION GRATING - A method for manufacturing a blazed diffraction grating made of a crystalline material comprising gallium phosphide (GaP) or gallium arsenide (GaAs) includes forming the blazed diffraction grating by forming a plurality of grating grooves on a machined surface of a workpiece by machining, wherein the grating grooves are formed so that a surface comprising a (110) plane is arranged to receive the most incident light among the surfaces that constitute each grating, where (110) describes a crystal orientation of the crystalline material. | 12-26-2013 |
20130342909 | METHOD OF MANUFACTURING A DIFFRACTION GRATING - A method for manufacturing a blazed diffraction grating made of a crystalline material comprising zinc selenide (ZnSe) or zinc sulfide (ZnS) includes forming the blazed diffraction grating by forming a plurality of grating grooves on a machined surface of a workpiece by machining, wherein the grating grooves are formed so that a surface comprising a (110) plane is arranged to receive the most incident light among the surfaces that constitute each grating, where (110) describes a crystal orientation of the crystalline material. | 12-26-2013 |
20140363338 | SPECTRAL APPARATUS, DETECTION APPARATUS, LIGHT SOURCE APPARATUS, REACTION APPARATUS, AND MEASUREMENT APPARATUS - The present invention provides a spectral apparatus for spectrally separating light including a predetermined wavelength, including a slit that the light enters, a first optical system configured to collimate the light from the slit, a transmissive type diffraction element configured to diffract the light from the first optical system, and a second optical system including a first mirror configured to reflect the light diffracted by the transmissive type diffraction element, and a second mirror configured to reflect the light reflected by the first mirror and diffracted by the transmissive type diffraction element, and configured to make the light reciprocally travel between the first mirror and the second mirror via the transmissive type diffraction element. | 12-11-2014 |
20150177428 | DIFFRACTION GRATING AND DIFFRACTION GRATING PRODUCING METHOD - A method for producing a blazed diffraction grating made of a crystal material of InP or InAs according to the present invention is characterized in that when the blazed diffraction grating is formed by forming a plurality of grating grooves by machining a process target surface of a workpiece W (step S | 06-25-2015 |