Xue, CA
Chenchen Xue, Irvine, CA US
Patent application number | Description | Published |
---|---|---|
20150183999 | METHOD OF MANUFACTURING HYDROPHOBIC ANTIFOULING COATING MATERIAL AND METHOD OF FORMING HYDROPHOBIC ANTIFOULING COATING FILM - A method of manufacturing a hydrophobic antifouling coating material, including: (a) mixing a sol-gel precursor, water, an aqueous colloidal silica suspension, and a catalyst to perform a sol-gel reaction to form a solution having particles therein, wherein the sol-gel reaction is performed without addition of any organic solvent; (b) chemically modifying the particles with a hydrophobic agent to form surface-modified particles; and (c) adding a surfactant to the solution containing the surface-modified particles to form a hydrophobic antifouling coating material. The hydrophobic antifouling coating material can be dispersed in an aqueous solution, and has properties such as low VOC (Volatile organic compound) value, high solid content, and high stability. | 07-02-2015 |
Cuihua Xue, Irvine, CA US
Patent application number | Description | Published |
---|---|---|
20120322944 | WATER SOLUBLE NEAR INFRARED SENSING POLYMERS WITH LOW BAND GAPS - The present invention is directed to polymeric materials including a copolymer of at least a first and second monomer that have desirable electrical and optical properties, such as a low band gap and near infrared (NIR) absorption, respectively. More specifically, the present invention is directed to polymeric materials with charge neutrality that display increased solubility in aqueous media while retaining their electrical and optical properties. The polymeric materials in accordance with the present invention can be modified with any desired functional group to tailor the polymer materials for a specific application. Also described are methods of making the polymeric materials in accordance with the present invention. | 12-20-2012 |
20140017762 | NETWORK CONJUGATED POLYMERS WITH ENHANCED SOLUBILITY - Cross-linked, conjugated organic semiconducting polymer networks that combine improved solubility with improved electrical and/or optical properties in one package have been developed. New materials that combine advantages of good charge-carrier mobility organic materials and conjugated polymer networks as well as fairly good solubility in common organic solvents, into one package and thus offers a general and powerful platform suitable for use in numerous applications. | 01-16-2014 |
Fei Xue, San Carlos, CA US
Patent application number | Description | Published |
---|---|---|
20150286688 | Apparatus and Method for Management of Bitemporal Objects - A machine has a processor and a memory connected to the processor. The memory stores instructions executed by the processor to construct an object collection where each object in the object collection has a common identifier, a valid time start field, a valid time end field, a system time start field and a system time end field. The object collection includes split objects with a legacy object and an updated object with the system time start field set to the system time that the split objects are formed. | 10-08-2015 |
Fengliang Xue, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20150137233 | HIGH VOLTAGE DEVICE FABRICATED USING LOW-VOLTAGE PROCESSES - A high-voltage transistor includes an active region including a diffused region of a first conductivity type defined by inner edges of a border of shallow trench isolation. A gate having side edges and end edges is disposed over the active region. Spaced apart source and drain regions of a second conductivity type opposite the first conductivity type are disposed in the active region outwardly with respect to the side edges of the gate. Lightly-doped regions of the second conductivity type more lightly-doped than the source and drain regions surround the source and drain regions and extend inwardly between the source and drain regions towards the gate to define a channel, and outwardly towards all of the inner edges of the shallow trench isolation. Outer edges of the lightly-doped region from at least the drain region are spaced apart from the inner edges of the shallow trench isolation. | 05-21-2015 |
Gang Xue, Sunnyvale, CA US
Patent application number | Description | Published |
---|---|---|
20090269916 | METHODS FOR FABRICATING MEMORY CELLS HAVING FIN STRUCTURES WITH SEMICIRCULAR TOP SURFACES AND ROUNDED TOP CORNERS AND EDGES - Methods for fabricating a FIN structure with a semicircular top surface and rounded top surface corners and edges are disclosed. As a part of a disclosed method, a FIN structure is formed in a semiconductor substrate. The FIN structure includes a top surface having corners and edges. The FIN structure is annealed where the annealing causes the top surface to have a semicircular shape and the top surface corners and edges to be rounded. | 10-29-2009 |
20100133646 | SELF-ALIGNED SI RICH NITRIDE CHARGE TRAP LAYER ISOLATION FOR CHARGE TRAP FLASH MEMORY - A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance. U-shaped trap layer edges allow for increased packing density and integration while maintaining isolation between trap layers. | 06-03-2010 |
20100207191 | METHOD AND DEVICE EMPLOYING POLYSILICON SCALING - A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack. | 08-19-2010 |
20100276746 | SONOS MEMORY CELLS HAVING NON-UNIFORM TUNNEL OXIDE AND METHODS FOR FABRICATING SAME - Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure. | 11-04-2010 |
20110195578 | PLANAR CELL ON CUT USING IN-SITU POLYMER DEPOSITION AND ETCH - A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is over the shallow trench. Etching is performed on the polymer layer to expose the first region of the ONO layer, leaving the second region of the ONO unexposed. The etching continues to occur to etch the exposed ONO at the first region so that the ONO layer is etched away in the first region and the second region remains unexposed. | 08-11-2011 |
20110233647 | METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER - Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer. | 09-29-2011 |
20120056260 | METHOD AND DEVICE EMPLOYING POLYSILICON SCALING - A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack. | 03-08-2012 |
20120181601 | METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER - Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer. | 07-19-2012 |
20130277732 | SONOS MEMORY CELLS HAVING NON-UNIFORM TUNNEL OXIDE AND METHODS FOR FABRICATING SAME - Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure. | 10-24-2013 |
20140001537 | SELF-ALIGNED SI RICH NITRIDE CHARGE TRAP LAYER ISOLATION FOR CHARGE TRAP FLASH MEMORY | 01-02-2014 |
Haitao Xue, Santa Clara, CA US
Patent application number | Description | Published |
---|---|---|
20150103094 | REGION-DEPENDENT COLOR MAPPING FOR REDUCING VISIBLE ARTIFACTS ON HALFTONED DISPLAYS - This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for displaying high resolution images with reduced visible halftone noise. In one aspect, an image having a plurality of image pixels is displayed on a display device having a plurality of display pixels, by mapping the tone or color of each input image pixel onto the plurality of display pixels by assigning each display pixel a tone or color value in the color space associated with the display device that is in a neighborhood of the tone or color of each input image pixel and appears to have the same perceptual tone or color value as the image pixel and has a lower visible halftone noise. A size of the neighborhood can be selected based on the color gradient in various portions of the image. | 04-16-2015 |
Hong Xue, Pleasanton, CA US
Patent application number | Description | Published |
---|---|---|
20110105712 | ZWITTERIONIC POLYMERS HAVING BIOMIMETIC ADHESIVE LINKAGES - Zwitterionic polymers having adhesive groups, methods for making the polymers, surfaces having the polymers grafted thereto and grafted therefrom, and methods for making and using the polymer-modified surfaces. | 05-05-2011 |
20110195104 | INTEGRATED ANTIMICROBIAL AND LOW FOULING MATERIALS - Cationic polymers hydrolyzable to zwitterionic polymers, monomers for making the cationic polymers, surfaces that include the polymers, and methods for making and using the cationic polymers and surfaces. The cationic polymers include counterions and/or hydrolyzable groups that release active agents. | 08-11-2011 |
20120259021 | SELF-ASSEMBLED PARTICLES FROM ZWITTERIONIC POLYMERS AND RELATED METHODS - Zwitterionic block copolymers and zwitterionic conjugates that advantageously self-assemble into particles, particles assembled from the zwitterionic block copolymers and zwitterionic conjugates, pharmaceutical compositions that include the self-assembled particles, and methods for delivering therapeutic and diagnostic agents using the particles. | 10-11-2012 |
20120315239 | ZWITTERIONIC POLYMER BIOCONJUGATES AND RELATED METHODS - Zwitterionic polymer and mixed charge copolymer bioconjugates, methods for making and using the bioconjugates. | 12-13-2012 |
20120322939 | CROSSLINKED ZWITTERIONIC HYDROGELS - Zwitterionic crosslinking agents, crosslinked zwitterionic hydrogels prepared from copolymerization of zwitterionic monomers with the zwitterionic crosslinking agent, methods for making crosslinked zwitterionic hydrogels, and devices that include and methods that use the crosslinked zwitterionic hydrogels. | 12-20-2012 |
20130011363 | CATIONIC BETAINE PRECURSORS TO ZWITTERIONIC BETAINES HAVING CONTROLLED BIOLOGICAL PROPERTIES - Cationic polymers hydrolyzable to zwitterionic polymers, monomers for making the cationic polymers, surfaces that include the polymers, therapeutic agent delivery systems that include the cationic polymers, methods for administering a therapeutic agent using the delivery systems, and methods for making and using the cationic polymers, monomers, surfaces, and therapeutic agent delivery systems. | 01-10-2013 |
20130178125 | MARINE COATINGS - Marine coatings including cationic polymers hydrolyzable to nonfouling zwitterionic polymers, coated marine surfaces, and methods for making and using the marine coatings. | 07-11-2013 |
20140174962 | Silicone Hydrogel Contact Lenses For Sustained Release Of Beneficial Polymers - Silicone hydrogel contact lenses comprising an ionic component sustain release of beneficial cationic polymers. | 06-26-2014 |
20140200287 | Reactive Dyes For Contact Lenses - A method for preparing a polymerizable monomer-dye compound is provided in which a monomer, a reactive dye, and base are combined under substantially anhydrous reaction conditions to form the polymerizable monomer-dye compound, wherein the monomer comprises a pendant reactive group that covalently links to the reactive dye to form the monomer-dye compound. | 07-17-2014 |
20140221577 | SELF-ASSEMBLED PARTICLES FROM ZWITTERIONIC POLYMERS AND RELATED METHODS - Zwitterionic block copolymers and zwitterionic conjugates that advantageously self-assemble into particles, particles assembled from the zwitterionic block copolymers and zwitterionic conjugates, pharmaceutical compositions that include the self-assembled particles, and methods for delivering therapeutic and diagnostic agents using the particles. | 08-07-2014 |
20140275614 | PRODUCTION AND PURIFICATION OF CARBOXYLIC BETAINE ZWITTERIONIC MONOMERS - A method is provided for the production and purification of carboxylic betaine-based zwitterionic vinyl monomers, such as (meth)acrylic or (meth)acrylamide monomer containing a betaine-type group of the formula: | 09-18-2014 |
20150037598 | CROSSLINKED ZWITTERIONIC HYDROGELS - Zwitterionic crosslinking agents, crosslinked zwitterionic hydrogels prepared from copolymerization of zwitterionic monomers with the zwitterionic crosslinking agent, methods for making crosslinked zwitterionic hydrogels, and devices that include and methods that use the crosslinked zwitterionic hydrogels. | 02-05-2015 |
20150157732 | ZWITTERIONIC POLYMER BIOCONJUGATES AND RELATED METHODS - Zwitterionic polymer and mixed charge copolymer bioconjugates, methods for making and using the bioconjugates. | 06-11-2015 |
20160054475 | Primary Amine-Containing Silicone Hydrogel Contact Lenses And Related Compositions And Methods - Miscible polymerizable compositions comprising at least one primary amine-containing methacrylate monomer, or at least one primary amine-containing methacrylamide monomer, in addition to 20-80 wt. % siloxane monomer, 20-80 wt. % hydrophilic monomer, cross-linking agent, and polymerization initiator, are described. These polymerizable compositions can be used to form silicone hydrogel contact lenses, and in methods of manufacturing silicone hydrogel contact lenses. | 02-25-2016 |
Hua Xue, Saratoga, CA US
Patent application number | Description | Published |
---|---|---|
20150324509 | PARTITION BASED DESIGN IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES - Various techniques are provided to generate designs for programmable logic devices (PLDs). In one example, a computer-implemented method includes selectively grouping a first plurality of logic components for a first design into a plurality of partitions. The method also includes selectively merging at least a subset of the partitions of the first design. The method also includes converting each partition into a corresponding first physical implementation for a PLD. The method also includes comparing the first plurality of logic components to a second plurality of logic components for a second design to identify changed and unchanged partitions. The method also includes converting each changed partition into a corresponding second physical implementation for the PLD. The method also includes combining the first physical implementations for the unchanged partitions, with the second physical implementations for the changed partitions. | 11-12-2015 |
20150379164 | MIXED-WIDTH MEMORY TECHNIQUES FOR PROGRAMMABLE LOGIC DEVICES - Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a mixed-mode memory operation in the design. The mixed-mode memory operation specifies memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width. The synthesizing further includes determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks. | 12-31-2015 |
Hua J. Xue, Saratoga, CA US
Patent application number | Description | Published |
---|---|---|
20090109793 | Juice apparatus and disposable juicer cups - A blender apparatus includes a disposable cup. The disposable cup has a set of blending blades disposed on a bottom portion of the disposable cup provided for cutting and blending food chunks contained in the disposable cup. The blender apparatus further includes a base unit. The base unit has a rotating mechanism for engaging the set of blending blades for rotating and cutting and blending the food chunks. The set of blending blades further includes a blade-set engagement interface for engaging to the rotating engagement interface for rotating and cutting and blending the food chunks. | 04-30-2009 |
Huansheng Xue, San Gabriel, CA US
Patent application number | Description | Published |
---|---|---|
20090268988 | METHOD AND APPARATUS FOR TWO DIMENSIONAL IMAGE PROCESSING - In one embodiment, the present invention is a system for organizing data flow for two dimensional digital image processing. The system includes a memory access module for accessing an external memory containing image data to be processed, and a data flow organizer module for preparing a data stream from the input image data accessed by the memory access module. The data flow organizer module predicts future data needed for processing, and the memory access module pre-fetches the predicted data from the memory. A data processing module processes the pre-fetched data from the data flow organizer module. Address generation for accessing the memory is performed independent and in parallel with processing the pre-fetched data. | 10-29-2009 |
20100027852 | System and Method for Fast Biometric Pattern Matching - A method and system for matching two biometric images including receiving an input biometric image; generating an index table for the input biometric image, wherein the index table includes a quality quantity for each minutia of the input biometric image; receiving a second biometric image; generating a number of patterns for a first minutia of the second biometric image; associatively accessing the index table by the generated number of patterns; accumulating quality quantities accessed from the index table for each minutia of the input biometric image for the number of patterns of the first minutia of the second biometric image; and selecting a minutia candidate of the input biometric image responsive to the accumulated quality quantities. | 02-04-2010 |
Jianxia Xue, Culver City, CA US
Patent application number | Description | Published |
---|---|---|
20140341429 | COMBINING MULTI-SENSORY INPUTS FOR DIGITAL ANIMATION - Animating digital characters based on motion captured performances, including: receiving sensory data collected using a variety of collection techniques including optical video, electro-oculography, and at least one of optical, infrared, and inertial motion capture; and managing and combining the collected sensory data to aid cleaning, tracking, labeling, and re-targeting processes. Keywords include Optical Video Data and Inertial Motion Capture. | 11-20-2014 |
Jie Xue, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20100207649 | IN SITU AND REAL TIME MONITORING OF INTERCONNECT RELIABILITY USING A PROGRAMMABLE DEVICE - In one embodiment, the reliability of the L2 power and/or ground sub-arrays of contacts of a functional integrated circuit device is verified by applying a reference voltage to a selected contact in sub-array and sequentially measuring the voltage at other contacts in the sub-array. If the voltage levels are greater than a threshold voltage level then the functional integrated circuit device is verified as being reliable. | 08-19-2010 |
Jie Xue, Dublin, CA US
Patent application number | Description | Published |
---|---|---|
20120113608 | METHOD AND APPARATUS FOR SUPPORTING A COMPUTER CHIP ON A PRINTED CIRCUIT BOARD ASSEMBLY - A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly. | 05-10-2012 |
Jie Xue, San Ramon, CA US
Patent application number | Description | Published |
---|---|---|
20120032693 | Crack detection in a semiconductor die and package - A method is provided in which an impedance is measured between a first of a plurality of seal ring contact pads and a ground contact pad coupled to a semiconductor substrate of a semiconductor device. The first impedance value is obtained from the measured impedance, and the first impedance value is compared with a reference impedance value to determine whether a structural defect is present in the semiconductor device based on whether the first impedance value is greater than the reference impedance value. | 02-09-2012 |
20130015557 | SEMICONDUCTOR PACKAGE INCLUDING AN EXTERNAL CIRCUIT ELEMENTAANM Yang; ZhipingAACI CupertinoAAST CAAACO USAAGP Yang; Zhiping Cupertino CA USAANM Xue; JieAACI San RamonAAST CAAACO USAAGP Xue; Jie San Ramon CA USAANM Savic; JovicaAACI Downers GroveAAST ILAACO USAAGP Savic; Jovica Downers Grove IL USAANM Li; LiAACI San RamonAAST CAAACO USAAGP Li; Li San Ramon CA US - Circuit elements such as DC blocking capacitors used in communication such as a serial communication link between two or more electrical components are disposed in pre-existing openings in a support structure that supports at least one of the two electrical components. The openings may be plated and used for signal transmission from the one electrical component to a printed circuit board (PCB) supporting the substrate. The DC blocking capacitors may be oriented substantially vertically, and a non-conducting material may be disposed in each opening in the substrate such that the non-conducting material at least partially surrounds and fixes the orientation of the DC blocking capacitor disposed in the opening. | 01-17-2013 |
20130122658 | MANUFACTURING A SEMICONDUCTOR PACKAGE INCLUDING AN EMBEDDED CIRCUIT COMPONENT WITHIN A SUPPORT STRUCTURE OF THE PACKAGE - A method and apparatus are provided in which a cavity is formed in a support structure, the support structure being operable to support a semiconductor device, disposing at least a portion of a circuit element in the cavity in the support structure, filling the cavity in the support structure with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material, and electrically connecting the semiconductor device to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device. | 05-16-2013 |
20130139033 | TECHNIQUES FOR EMBEDDED MEMORY SELF REPAIR - Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error. | 05-30-2013 |
20150342053 | Manufacturing a Semiconductor Package Including an Embedded Circuit Component within a Support Structure of the Package - An apparatus includes a cavity formed in a support structure, the support structure being operable to support a semiconductor device. A circuit element is disposed in the cavity in the support structure, and the cavity in the support structure is filled with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material. The semiconductor device is electrically connected to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device. | 11-26-2015 |
Jing Xue, Sunnyvale, CA US
Patent application number | Description | Published |
---|---|---|
20110179393 | ETCH-AWARE OPC MODEL CALIBRATION BY USING AN ETCH BIAS FILTER - One embodiment of the present invention relates to a system that constructs and calibrates an etch-aware photolithography model. During operation, the system constructs an etch bias model which models a critical dimension (CD) difference between a measured CD value of a feature after the photolithography process and a measured CD value of the feature after the etch process. The system then fits the photolithography process model based at least on the post-lithography measured CD data and the etch bias model, thereby causing the photolithography process model to be aware of etch effects. The present techniques facilitate bridging the gap between the photolithography and the etch process in the OPC modeling flow. In particular, these techniques can be used to modify conventional staged OPC model or to construct a model based rule table for correcting a retarget model. | 07-21-2011 |
20140112882 | Methods to treat pancreatic inflammation and associated lung injury through regulation of pancreatic interleukin-22 expression - Methods for use of a composition comprising agents that increase pancreatic interleukin-22 production in the treatment of pancreatic inflammatory disorders including pancreatitis-associated acute lung injury. | 04-24-2014 |
Jingyang Xue, Sunnyvale, CA US
Patent application number | Description | Published |
---|---|---|
20160037019 | SEMI-FIXED-HUE GAMUT COMPRESSION - One or more apparatus and method for compressing xvYCC or sRGB color to a narrower color gamut. Embodiments may be utilized in processing images/video image sequences provided in a wide gamut color space for display in standard RGB color space. In further embodiments, an sRGB or xvYCC compliant input is compressed to a gamut narrower than sRGB. Embodiments where a narrow output color gamut lacks a fully-defined 3D color space, semi-fixed-hue gamut compression may be performed by adjusting parameters provided to a fixed-hue compression module capable of mapping 3D color space representations between well-defined gamuts. | 02-04-2016 |
Jiuzhi Xue, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20150034469 | FORMABLE INPUT KEYPAD AND DISPLAY DEVICE USING THE SAME - A formable input keypad includes: an electroactive polymer (EAP) layer having a first surface and a second surface opposite the first surface; a first conductive electrode pattern defining outlines of user input keys at the first surface of the EAP layer; and a second conductive electrode pattern at the second surface of the EAP layer. | 02-05-2015 |
Jun Xue, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20130115778 | Dry Etch Processes - Provided methods of etching and/or patterning films. Certain methods comprise exposing at least part of a film on a substrate, the film comprising one or more of HfO | 05-09-2013 |
20150194317 | DEVELOPMENT OF HIGH ETCH SELECTIVE HARDMASK MATERIAL BY ION IMPLANTATION INTO AMORPHOUS CARBON FILMS - Embodiments described herein provide for a method of forming an etch selective hardmask. An amorphous carbon hardmask is implanted with various dopants to increase the hardness and density of the hardmask. The ion implantation of the amorphous carbon hardmask also maintains or reduces the internal stress of the hardmask. The etch selective hardmask generally provides for improved patterning in advanced NAND and DRAM devices. | 07-09-2015 |
20150279687 | HALOGEN-FREE GAS-PHASE SILICON ETCH - A method of selectively dry etching silicon from patterned heterogeneous structures is described. The method optionally includes a plasma process prior to a remote plasma etch. The plasma process may use a biased plasma to treat some crystalline silicon (e.g. polysilicon or single crystal silicon) to form amorphous silicon. Subsequently, a remote plasma is formed using a hydrogen-containing precursor to form plasma effluents. The plasma effluents are passed into the substrate processing region to etch the amorphous silicon from the patterned substrate. By implementing biased plasma processes, the normally isotropic etch may be transformed into a directional (anisotropic) etch despite the remote nature of the plasma excitation during the etch process. | 10-01-2015 |
20150315707 | REMOTE PLASMA SOURCE BASED CYCLIC CVD PROCESS FOR NANOCRYSTALLINE DIAMOND DEPOSITION - Methods for making a nanocrystalline diamond layer are disclosed herein. A method of forming a layer can include activating a deposition gas comprising an alkane and a hydrogen containing gas at a first pressure, delivering the activated deposition gas to the substrate at a second pressure which is less than the first pressure, forming a nanocrystalline diamond layer, treating the layer with an activated hydrogen containing gas to remove one or more polymers from the surface and repeating the cycle to achieve a desired thickness. | 11-05-2015 |
20150368801 | PLASMA PROCESS CHAMBERS EMPLOYING DISTRIBUTION GRIDS HAVING FOCUSING SURFACES THEREON ENABLING ANGLED FLUXES TO REACH A SUBSTRATE, AND RELATED METHODS - Plasma process chambers employing distribution grids having focusing surfaces thereon enabling angled fluxes to reach a substrate, and associated methods are disclosed. A distribution grid is disposed in a chamber between the plasma and a substrate. The distribution grid includes a first surface facing the substrate and a focusing surface facing the plasma. A passageway extends through the distribution grid, and is sized with a width to prevent the plasma sheath from entering therein. By positioning the focusing surface at an angle other than parallel to the substrate, an ion flux from the plasma may be accelerated across the plasma sheath and particles of the flux pass through the passageway to be incident upon the substrate. In this manner, the angled ion flux may perform thin film deposition and etch processes on sidewalls of features extending orthogonally from or into the substrate, as well as angled implant and surface modification. | 12-24-2015 |
20150371827 | BIAS VOLTAGE FREQUENCY CONTROLLED ANGULAR ION DISTRIBUTION IN PLASMA PROCESSING - The angular ion distribution in plasma processing is controlled using a bias voltage frequency. In one example, a plasma containing gas ions is generated in a plasma chamber. The plasma sheath is modified using an aperture disposed between the plasma sheath and the workpiece so that the plasma sheath takes a shape above the aperture. An oscillating radio frequency bias voltage is generated and applied to a workpiece holder. The workpiece holder applies the bias voltage to the workpiece to generate a workpiece bias voltage with respect to the plasma to attract ions across the plasma sheath toward the workpiece. The aperture and the frequency of the bias voltage control an angle at which the ions are attracted toward the workpiece. | 12-24-2015 |
20150380526 | METHODS FOR FORMING FIN STRUCTURES WITH DESIRED DIMENSIONS FOR 3D STRUCTURE SEMICONDUCTOR APPLICATIONS - Methods for forming fin structure with desired materials formed on different locations of the fin structure using an ion implantation process to define an etching stop layer followed by an etching process for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method for forming a structure on a substrate includes performing an ion implantation process on a substrate having a plurality of structures formed thereon, forming an ion treated region in the structure at an interface between the ion treated region and an untreated region in the structure defining an etch stop layer, and performing a remote plasma etching process to etch the treated region from the substrate to exposed the untreated region. | 12-31-2015 |
20160079034 | FLOWABLE FILM PROPERTIES TUNING USING IMPLANTATION - Species are supplied to a flowable layer over a substrate. A property of the flowable layer is modified by implanting the species to the flowable layer. The property comprises a density, a stress, a film shrinkage, an etch selectivity, or any combination thereof. | 03-17-2016 |
20160099154 | MATERIAL DEPOSITION FOR HIGH ASPECT RATIO STRUCTURES - Ion species are supplied to a workpiece comprising a pattern layer over a substrate. A material layer is deposited on the pattern layer using an implantation process of the ion species. In one embodiment, the deposited material layer has an etch selectivity to the pattern layer. In one embodiment, a trench is formed on the pattern layer. The trench comprises a bottom and a sidewall. The material layer is deposited into the trench using the ion implantation process. The material layer is deposited on the bottom of the trench in a direction along the sidewall. | 04-07-2016 |
Lan Xue, Palo Alto, CA US
Patent application number | Description | Published |
---|---|---|
20130219221 | SYSTEMS AND METHODS TO SIMULATE STORAGE - The embodiments described herein include a host that includes an operating system and a storage simulation module in communication with the host. The storage simulation module includes a pseudo-adapter configured to emulate a storage adapter and a pseudo-storage device coupled to the pseudo-adapter, wherein the pseudo-storage device is configured to emulate a storage device. The storage simulation module is configured to simulate an error event for the pseudo-adapter and/or the pseudo-storage device upon receipt of an operation from the operating system. | 08-22-2013 |
20130219222 | SYSTEMS AND METHODS TO TEST PROGRAMS - The embodiments described herein include a host that includes an operating system and a storage simulation module in communication with the host. The storage simulation module includes a pseudo-adapter configured to emulate a storage adapter and a pseudo-storage device coupled to the pseudo-adapter, wherein the pseudo-storage device is configured to emulate a storage device. The storage simulation module is configured to simulate an error event for the pseudo-adapter and/or the pseudo-storage device upon receipt of an operation from the operating system. | 08-22-2013 |
Lei Xue, Sunnyvale, CA US
Patent application number | Description | Published |
---|---|---|
20140061771 | Memory Device with Charge Trap - A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer. | 03-06-2014 |
Lei Xue, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20090039405 | ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD. | 02-12-2009 |
20090042378 | USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line. | 02-12-2009 |
20090152669 | SI TRENCH BETWEEN BITLINE HDP FOR BVDSS IMPROVEMENT - Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the semiconductor substrate between the first spacers; and second spacers adjacent the side surfaces of the trench. By containing the trench and the first and second spacers between the bitlines, the memory device can improve the electrical isolation between the bitlines, thereby preventing and/or mitigating bitline-to-bitline current leakage and increasing BVdss. | 06-18-2009 |
20100264480 | USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line. | 10-21-2010 |
20110278660 | ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD. | 11-17-2011 |
Lei Xue, Milpitas, CA US
Patent application number | Description | Published |
---|---|---|
20100213535 | ADJACENT WORDLINE DISTURB REDUCTION USING BORON/INDIUM IMPLANT - Semiconductor devices having reduced parasitic current and methods of malting the semiconductor devices are provided. Further provided are memory devices having reduced adjacent wordline disturb. The memory devices contain wordlines formed over a semiconductor substrate, wherein at least one wordline space is formed between the wordlines. Adjacent wordline disturb is reduced by implanting one or more of indium, boron, and a combination of boron and indium in the surface of the at least one wordline space. | 08-26-2010 |
20110317466 | HIGH READ SPEED MEMORY WITH GATE ISOLATION - Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture. | 12-29-2011 |
20120202355 | PATTERNED DUMMY WAFERS LOADING IN BATCH TYPE CVD - A method for semiconductor device fabrication is provided. Embodiments of the present invention are directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. In another embodiment, at least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes. | 08-09-2012 |
20120241871 | INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE - A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away. | 09-27-2012 |
20120327717 | HIGH READ SPEED MEMORY WITH GATE ISOLATION - Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture. | 12-27-2012 |
20130023101 | METHOD AND MANUFACTURE FOR EMBEDDED FLASH TO ACHIEVE HIGH QUALITY SPACERS FOR CORE AND HIGH VOLTAGE DEVICES AND LOW TEMPERATURE SPACERS FOR HIGH PERFORMANCE LOGIC DEVICES - A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and junction formation on both the memory cell region and the high-voltage device region, spacer formation and junction formation is performed on a low-voltage device region in the periphery section. | 01-24-2013 |
20140117435 | INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE - A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away. | 05-01-2014 |
20140209993 | Non-Volatile Memory With Silicided Bit Line Contacts - An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A farther benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes. | 07-31-2014 |
20150017795 | Non-Volatile Memory With Silicided Bit Line Contacts - An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes. | 01-15-2015 |
Lei Xue, Saratoga, CA US
Patent application number | Description | Published |
---|---|---|
20150097224 | BURIED TRENCH ISOLATION IN INTEGRATED CIRCUITS - A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is positioned between first and second devices and comprises a first filled portion and a second filled portion. The first filled portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. | 04-09-2015 |
20150097245 | SELF-ALIGNED TRENCH ISOLATION IN INTEGRATED CIRCUITS - A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC. | 04-09-2015 |
20150179656 | CT-NOR DIFFERENTIAL BITLINE SENSING ARCHITECTURE - Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of memory transistors arranged electrically in serial is configured to control a gate voltage of a pass transistor. The pass transistor, in turn, enables current flow between two metal bitlines of the semiconductor memory architecture. Accordingly, a relative voltage or relative current of the two metal bitlines can be measured and utilized to determine a program or erase state of a transistor of the serial array of transistors. In a particular aspect, a transistor with small capacitance is chosen for the pass transistor, resulting in a fast correspondence of the pass transistor gate voltage/current relative to transistor array current. This can equate to fast read times for the transistor array, based on differential sensing of the two metal bitlines. | 06-25-2015 |
20150262838 | Buried Trench Isolation in Integrated Circuits - A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method of using Hydrogen annealing to create the buried trench is disclosed. | 09-17-2015 |
20160035576 | SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE - A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed. | 02-04-2016 |
Liang Xue, Elk Grove, CA US
Patent application number | Description | Published |
---|---|---|
20120322812 | RUTAECARPINE DERIVATIVES FOR TREATING INSOMNIA - The teachings provided herein generally relate to compositions comprising a rutaecarpine derivative that activates CYP1A2 through enzyme induction. The uses for such a derivative, in some embodiments can include improving sleep, as well as treating insomnia. Other uses for the derivatives are provided herein. | 12-20-2012 |
20120322813 | RUTAECARPINE DERIVATIVES FOR TREATING CAFFEINE TOXICITY - The teachings provided herein generally relate to compositions comprising a rutaecarpine derivative that activates CYP1A2 through enzyme induction. The compound can be used for treating caffeine toxicity, in some embodiments. Caffeine is just one example of a substrate that can be removed using the derivatives taught herein, and other examples, including theophylline, are provided herein. | 12-20-2012 |
20120322816 | RUTAECARPINE DERIVATIVES FOR ACTIVATING CYP1A2 IN A SUBJECT - The teachings provided herein generally relate to compositions comprising rutaecarpine derivatives that activates CYP1A2 through enzyme induction. The uses for such a derivative can include removing caffeine from a subject, improving sleep, treating insomnia, treating caffeine toxicity, treating caffeine addiction and withdrawal symptoms, and the like. Caffeine is just one example of a substrate that can be removed using the derivatives taught herein, and other examples, including theophylline, are provided herein. | 12-20-2012 |
Lin Xue, Sunnyvale, CA US
Patent application number | Description | Published |
---|---|---|
20150255507 | METHOD OF FORMING MAGNETIC TUNNELING JUNCTIONS - A method for fabricating an MRAM bit that includes depositing a spacer layer that protects the tunneling barrier layer during processing is disclosed. The deposited spacer layer prevents byproducts formed in later processing from redepositing on the tunneling barrier layer. Such redeposition may lead to product failure and decreased manufacturing yield. The method further includes non-corrosive processing conditions that prevent damage to the layers of MRAM bits. The non-corrosive processing conditions may include etching without using a halogen-based plasma. Embodiments disclosed herein use an etch-deposition-etch sequence that simplifies processing. | 09-10-2015 |
Mao Xue, Fremont, CA US
Patent application number | Description | Published |
---|---|---|
20140164511 | Eliciting Event-Driven Feedback - Particular embodiments detect events associated with information about activities that a user has engaged in. The activities may be associated with a location or location-agnostic. Based on the received information, the social-networking system sends the user a request for follow-up information after an appropriate time delay. The time delay may vary based on the user activity and the context of the event that triggered the request. After the follow-up information is received, such information is stored in the social-networking system and may be used to determine recommendations, sponsored stories, advertisements, etc. to send to friends of the user. The information may also be used for ranking or filtering recommendations. | 06-12-2014 |
20160044120 | Eliciting Event-Driven Feedback in a Social Network - Particular embodiments detect events associated with information about activities that a user has engaged in. The activities may be associated with a location or location-agnostic. Based on the received information, the social-networking system sends the user a request for follow-up information after an appropriate time delay. The time delay may vary based on the user activity and the context of the event that triggered the request. After the follow-up information is received, such information is stored in the social-networking system and may be used to determine recommendations, sponsored stories, advertisements, etc. to send to friends of the user. The information may also be used for ranking or filtering recommendations. | 02-11-2016 |
20160044121 | Eliciting Event-Driven Feedback in a Social Network - Particular embodiments detect events associated with information about activities that a user has engaged in. The activities may be associated with a location or location-agnostic. Based on the received information, the social-networking system sends the user a request for follow-up information after an appropriate time delay. The time delay may vary based on the user activity and the context of the event that triggered the request. After the follow-up information is received, such information is stored in the social-networking system and may be used to determine recommendations, sponsored stories, advertisements, etc. to send to friends of the user. The information may also be used for ranking or filtering recommendations. | 02-11-2016 |
Min Xue, Los Angeles, CA US
Patent application number | Description | Published |
---|---|---|
20120207795 | CATIONIC POLYMER COATED MESOPOROUS SILICA NANOPARTICLES AND USES THEREOF - A submicron structure having a silica body defining a plurality of pores is described. The submicron body may be spherical or non-spherical, and may include a cationic polymer or co-polymer on the surface of said silica body. The submicron structure may further include an oligonucleotide and be used to deliver the oligonucleotide to a cell. The submicron structure may further include a therapeutic agent and be used to deliver the therapeutic agent to a cell. An oligonucleotide and therapeutic agent may be used together. For example, when the oligonucleotide is an siRNA, the composition may be used to decrease cellular resistance to the therapeutic agent by decreasing translation of a resistance gene. | 08-16-2012 |
Qi Xue, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20090010180 | METHODS AND APPARATUS FOR RESOURCE PROVISIONING AND PLANNING IN A COMMUNICATION NETWORK - Methods and apparatus for resource provisioning and planning in a communication network. In an aspect, a method includes generating resource entities that represent resource requirements of targeted services, wherein the resource entities are modeled from at least one of transport network (TN) dependent information and TN independent information, and determining whether the resource entities can be supported by one or more transport networks. An apparatus includes input logic to receive at least one of TN dependent information and TN independent information, and processing logic to generate resource entities that represent resource requirements of targeted services, wherein the resource entities are modeled from at least one of the TN dependent information and the TN independent information, and to determine whether the resource entities can be supported by one or more transport networks. | 01-08-2009 |
20090291631 | SYSTEMS AND METHODS FOR CARRYING BROADCAST SERVICES OVER A MOBILE BROADCAST NETWORK - A method for carrying different types of broadcast services over a first mobile broadcast network that carries a first type of service content may include adapting a second type of service content, different from the first type of service content, for transport over the first mobile broadcast network, adapting service bootstrapping information, and mapping service layer addresses to data flow addresses of the first mobile broadcast network. On the receiver side, a broadcast flow address for service bootstrapping information may be discovered, the service bootstrapping information acquired from the discovered broadcast flow address, service layer addresses may be obtained from the bootstrapping information, and service components of the second type of service content acquired from the broadcast network. | 11-26-2009 |
20110167455 | ADAPTIVE MONITORING METHOD FOR UPDATE DETECTION IN A MOBILE BROADCAST NETWORK - Information included within metadata broadcast within an overhead flow of a mobile broadcast network enables receiver devices to determine when metadata updates will occur. The mobile broadcast network can include within metadata messages information related to a time for the next metadata update. Using this information, receiver devices can determine when the next metadata update will occur and de-energize the receiver until that time. Enabling mobile devices to remain de-energized until the next metadata update improves their power efficiency. Synchronizing mobile devices to access the overhead flow for updated metadata reduces the content delivery latency that the system must accommodate, thereby improving system flexibility and bandwidth efficiency. Specify the time of a next metadata update enables the broadcast system to change the rate and timing at which metadata updates are performed. | 07-07-2011 |
20110228716 | METHODS AND SYSTEMS FOR MULTIPLEXING MULTIPLE SERVICE COMPONENTS INTO ONE FLOW IN A FORWARD LINK ONLY NETWORK - Methods and systems for transmitting multiple service components in a single mediaFLO logical channel (MLC) stream within a MediaFLO® broadcast signal to distinguish data packets of different components based upon different media type header information or a component identifier added to the data packet header information. In a first embodiment, multiple service components of different media types are broadcast within the same MLC stream. Mobile device can separate received data packets within the MLC based upon their respective media type header information, and route each pack to its corresponding component processing module. In a second embodiment, different service components are identified with a component identifier that is added to the packet headers. A new layer in the protocol architecture stack can use the component ID within each data packet header to select and properly route the data packets for processing. | 09-22-2011 |
20110270653 | SYNCHRONIZATION OF INTERACTIVITY WITH LINEAR ADVERTISEMENT IN A MOBILE BROADCAST NETWORK - Methods, systems, and apparatus for synchronizing interactive advertisements with linear advertisements, including: a traffic module configured to generate advertisement schedule information about slots for linear advertisements on channels; an automation module configured to detect cue messages in real-time media, each cue message indicating a respective start time and a respective index of a respective slot for respective linear advertisements, and to forward information about the cue messages; and an interactivity production module configured to receive the advertisement schedule information, the information about the cue messages, and information about interactive sequences, each interactive sequence to be synchronized with a respective spot for an associated linear advertisement, to generate an interactivity event for each respective interactive sequence, to calculate a start time for each respective interactivity event using information about a respective associated cue message, and to forward an activation message with the respective start time for each respective interactivity event. | 11-03-2011 |
20110307561 | SYSTEM AND APPARATUS FOR POWER-EFFICIENTLY DELIVERING WEBPAGE CONTENTS IN A BROADCAST NETWORK - Embodiments provide bandwidth efficient mechanisms for delivering rich media content, such as webpages, to receiver devices via a multimedia broadcast network. Content, such as selected webpages, is broadcast as disassembled content elements via the broadcast network. To enable reception, the disassembled content elements are broadcast according to a broadcast schedule that is communicated in an overhead content description flow, such as a catalog file. Receiver devices receive the catalog file and use the metadata information to selectively receive disassembled content and store the content elements in memory. When a user requests access to the content (e.g., a webpage via a web browser), an application operating in the receiver device assembles the requested content from the previously received and stored disassembled content elements, and passes the assembled webpage to a using or rendering application. | 12-15-2011 |
20120293635 | HEAD POSE ESTIMATION USING RGBD CAMERA - A three-dimensional pose of the head of a subject is determined based on depth data captured in multiple images. The multiple images of the head are captured, e.g., by an RGBD camera. A rotation matrix and translation vector of the pose of the head relative to a reference pose is determined using the depth data. For example, arbitrary feature points on the head may be extracted in each of the multiple images and provided along with corresponding depth data to an Extended Kalman filter with states including a rotation matrix and a translation vector associated with the reference pose for the head and a current orientation and a current position. The three-dimensional pose of the head with respect to the reference pose is then determined based on the rotation matrix and the translation vector. | 11-22-2012 |
20130278777 | CAMERA GUIDED WEB BROWSING - Systems and methods for performing camera-guided browsing, such as web browsing, are described herein. A method for operating a camera-guided web browser as provided herein includes displaying a web page on a display associated with a portable device; passively detecting a first object within a field of view of a camera associated with the portable device; and altering at least part of the web page with first content associated with the first object in response to passively detecting the first object within the field of view of the camera. | 10-24-2013 |
20140098796 | INTERFACE SELECTION IN A HYBRID COMMUNICATION DEVICE - A hybrid device can be configured to select a transmit interface to attempt to ensure that each network interface of the hybrid device supports unidirectional traffic. Each of the plurality of network interfaces of the hybrid device can be categorized into one of a set of interface classes based on whether incoming traffic is received at the network interface and/or whether outgoing traffic is transmitted from the network interface. A transmit interface class is selected from the set of interface classes based, at least in part, on a priority level associated with each of the interface classes. One of the network interfaces that belongs to the transmit interface class is selected as a transmit interface for transmitting the frame on the communication network. | 04-10-2014 |
20140169383 | SEAMLESS SWITCHING FOR MULTIHOP HYBRID NETWORKS - Seamless path switching is made possible in a multi-hop network based upon stream marker packets and additional path distinguishing operations. A device receiving out-of-order packets on the same ingress interface is capable of determining a proper order for the incoming packets having different upstream paths. Packets may be reordered at a relay device or a destination device based upon where a path update is initiated. Reordering packets from the various upstream paths may be dependent upon a type of service associated with the packet. | 06-19-2014 |
20140269260 | DISTRIBUTED PATH UPDATE IN HYBRID NETWORKS - A network condition prompts a hybrid device to select a new path for a packet stream. A path update may occur in response to a change in network topology or a traffic loading condition (e.g., congestion or saturation of a link in the current path). Path selections may be made at each hybrid device in the path from a source hybrid device to a destination hybrid device. A path update procedure may be dependent upon path selection procedures that are optimized for a hybrid network in which multiple hybrid devices may be utilized for a particular path. Path update for load balancing may be dependent upon whether a packet stream is elastic or non-elastic. | 09-18-2014 |
20140269691 | DISTRIBUTED PATH SELECTION IN HYBRID NETWORKS - A hybrid device may select a next hop for a packet stream based upon a path selection. The path selection includes calculating end-to-end path capacity for candidate paths to a destination device. End-to-end path capacity is calculated based upon contention groups of particular links in at least one of the plurality of paths. Selected paths are recorded in a stream forwarding table for use with subsequent packets of a packet stream. In some embodiments, each hybrid device independently performs path selection logic or path update logic for a packet stream. | 09-18-2014 |
20140321480 | NAMED DATA NETWORKING IN LOCAL AREA NETWORKS - A named data networking (NDN) architecture may be implemented within a local area network. A local area networking naming convention may be used in relation to named content from a variety of NDN-enabled devices. A network node (such as an NDN gateway or NDN bridge) may manage the local area networking naming convention and assign a name for the named content of the NDN-enabled device. A network-assigned name in accordance with a local area networking naming convention may be used for group control of multiple NDN-enabled devices. An NDN gateway may be used for translating NDN protocol layer communication to an IP network protocol layer. An NDN bridge may be used for bridging NDN protocol layer communication between various different segments of a local area network. NDN-enabled devices may benefit from longer sleep cycles based upon NDN content caching implemented in the local area network. | 10-30-2014 |
20150036573 | WLAN-CAPABLE REMOTE CONTROL DEVICE - Operations for a WLAN-capable remote control device and a controlled device are disclosed. A first network device (e.g., remote control) may receive a user input for controlling operation of a second network device (e.g., controlled device) of a communication network. The first network device may transition to an active operating state in response to receiving the user input. The first network device may transmit the first user input to the second network device. The first network device may exit the active operating state in response to successfully transmitting the first user input to the second network device. | 02-05-2015 |
20160073340 | ENHANCEMENTS FOR WIFI MULTIMEDIA EXTENSIONS - A method of operating a station (STA) in a communications network is disclosed. A set of access categories of the STA that are enabled for unscheduled automatic power save delivery (U-APSD) are identified. Specifically, each access category in the set of access categories is associated with one or more user priority values. A lowest-priority access category is determined among the set of access categories. Specifically, the lowest-priority access category is associated with the lowest user priority value among the set of access categories. A trigger frame associated with the lowest-priority access category is then transmitted to an access point (AP) to initiate a first unscheduled service period with the AP. | 03-10-2016 |
Qiufen Xue, Thousand Oaks, CA US
Patent application number | Description | Published |
---|---|---|
20160046618 | Cyclopropyl Fused Thiazin-2-Amine Compounds as Beta-Secretase Inhibitors and Methods of Use - The present invention provides a new class of compounds useful for the modulation of beta-secretase enzyme (BACE) activity. The compounds have a general Formula I: | 02-18-2016 |
Qiufen Xue, Newbury Park, CA US
Patent application number | Description | Published |
---|---|---|
20090036478 | Substituted hydroxyethyl amine compounds as beta-secretase modulators and methods of use - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I | 02-05-2009 |
20090275602 | Substituted hydroxyethyl amine compounds as beta-secretase modulators and methods of use - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I | 11-05-2009 |
20100222338 | BETA-SECRETASE MODULATORS AND METHODS OF USE - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I | 09-02-2010 |
20110118250 | BETA-SECRETASE MODULATORS AND METHODS OF USE - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I | 05-19-2011 |
20110251190 | SPIRO-TETRACYCLIC RING COMPOUNDS AS BETA-SECRETASE MODULATORS AND METHODS OF USE - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and other related conditions. In one embodiment, the compounds have a general Formula I | 10-13-2011 |
20120220583 | SUBSTITUTED HYDROXYETHYL AMINE COMPOUNDS AS BETA-SECRETASE MODULATORS AND METHODS OF USE - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase activity and for the treatment of diseases, including Alzheimer's disease (AD) and related CNS conditions, mediated thereby. In one embodiment, the compounds have a general Formula I | 08-30-2012 |
20120329830 | Amino Heteroaryl Compounds as Beta-Secretase Modulators and Methods of Use - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I wherein ring A, B | 12-27-2012 |
20130018064 | Amino Heteroaryl Compounds as Beta-Secretase Modulators and Methods of UseAANM Paras; Nick A.AACI San FranciscoAAST CAAACO USAAGP Paras; Nick A. San Francisco CA USAANM Cheng; YuanAACI Newbury ParkAAST CAAACO USAAGP Cheng; Yuan Newbury Park CA USAANM Powers; TimothyAACI MalibuAAST CAAACO USAAGP Powers; Timothy Malibu CA USAANM Brown; JamesAACI MoorparkAAST CAAACO USAAGP Brown; James Moorpark CA USAANM Hitchcock; Stephen A.AACI JupiterAAST FLAACO USAAGP Hitchcock; Stephen A. Jupiter FL USAANM Judd; TedAACI Simi ValleyAAST CAAACO USAAGP Judd; Ted Simi Valley CA USAANM Lopez; PatriciaAACI West HillsAAST CAAACO USAAGP Lopez; Patricia West Hills CA USAANM Xue; QiufenAACI Newbury ParkAAST CAAACO USAAGP Xue; Qiufen Newbury Park CA USAANM Yang; BryantAACI Simi ValleyAAST CAAACO USAAGP Yang; Bryant Simi Valley CA US - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I, wherein ring A, B | 01-17-2013 |
20130040931 | Amino Heteroaryl Compounds as Beta-Secretase Modulators and Methods of Use - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula (I); wherein ring A, B | 02-14-2013 |
20130072483 | SUBSTITUTED HYDROXYETHYL AMINE COMPOUNDS AS BETA-SECRETASE MODULATORS AND METHODS OF USE - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I | 03-21-2013 |
20140107109 | AMINO-DIHYDROTHIAZINE AND AMINO-DIOXIDO DIHYDROTHIAZINE COMPOUNDS AS BETA-SECRETASE ANTAGONISTS AND METHODS OF USE - The present invention provides a new class of compounds useful for the modulation of beta-secretase enzyme (BACE) activity. The compounds have a general Formula I: | 04-17-2014 |
20140249104 | PERFLUORINATED 5,6-DIHYDRO-4H-1,3-OXAZIN-2-AMINE COMPOUNDS AS BETA-SECRETASE INHIBITORS AND METHODS OF USE - The present invention provides a new class of compounds useful for the modulation of beta-secretase enzyme (BACE) activity. The compounds have a general Formula I: | 09-04-2014 |
20140275058 | PERFLUORINATED CYCLOPROPYL FUSED 1,3-OXAZIN-2-AMINE COMPOUNDS AS BETA-SECRETASE INHIBITORS AND METHODS OF USE - The present invention provides a new class of compounds useful for the modulation of beta-secretase enzyme (BACE) activity. The compounds have a general Formula I: | 09-18-2014 |
20140296226 | Amino-Oxazine and Amino-Dihydrothiazine Compounds as Beta-Secretase Modulators and Methods of Use - The present invention comprises a new class of compounds useful for the modulation of Beta-secretase enzyme activity and for the treatment of Beta-secretase mediated diseases, including Alzheimer's disease (AD) and related conditions. In one embodiment, the compounds have a general Formula I wherein A | 10-02-2014 |
20150252011 | PERFLUORINATED CYCLOPROPYL FUSED 1,3-OXAZIN-2-AMINE COMPOUNDS AS BETA-SECRETASE INHIBITORS AND METHODS OF USE - The present invention provides a new class of compounds useful for the modulation of beta-secretase enzyme (BACE) activity. The compounds have a general Formula I: | 09-10-2015 |
20150259308 | AMINO-DIHYDROTHIAZINE AND AMINO-DIOXIDO DIHYDROTHIAZINE COMPOUNDS AS BETA-SECRETASE ANTAGONISTS AND METHODS OF USE - The present invention provides a new class of compounds useful for the modulation of beta-secretase enzyme (BACE) activity. The compounds have a general Formula I: wherein variables A | 09-17-2015 |
Qiufen May Xue, Thousand Oaks, CA US
Patent application number | Description | Published |
---|---|---|
20090306095 | COMPOSITION AND ANTIVIRAL ACTIVITY OF SUBSTITUTED AZAINDOLEOXOACETIC PIPERAZINE DERIVATIVES - This invention provides compounds having drug and bio-affecting properties, their pharmaceutical compositions and method of use. In particular, the invention is concerned with azaindoleoxoacetyl piperazine derivatives. These compounds possess unique antiviral activity, whether used alone or in combination with other antivirals, antiinfectives, immunomodulators or HIV entry inhibitors. More particularly, the present invention relates to the treatment of HIV and AIDS. | 12-10-2009 |
Qiufen May Xue, Newbury Park, CA US
Patent application number | Description | Published |
---|---|---|
20090186933 | INDOLE, AZAINDOLE AND RELATED HETEROCYCLIC PYRROLIDINE DERIVATIVES - This invention provides compounds having drug and bio-affecting properties, their pharmaceutical compositions and method of use. In particular, the invention is concerned with amido piperazine derivatives. These compounds possess unique antiviral activity, whether used alone or in combination with other antivirals, antiinfectives, immunomodulators or HIV entry inhibitors. More particularly, the present invention relates to the treatment of HIV and AIDS. | 07-23-2009 |
20100093752 | PHARMACEUTICAL FORMULATIONS OF SUBSTITUTED AZAINDOLEOXOACETIC PIPERAZINE DERIVATIVES WITH PROTEASE INHIBITORS - This invention provides compounds having drug and bio-affecting properties, their pharmaceutical compositions and method of use. In particular, the invention is concerned with azaindoleoxoacetyl piperazine derivatives. These compounds possess unique antiviral activity, whether used alone or in combination with other antivirals, antiinfectives, immunomodulators or HIV entry inhibitors. More particularly, the present invention relates to the treatment of HIV and AIDS. | 04-15-2010 |
20110118279 | PHARMACEUTICAL FORMULATIONS OF SUBSTITUTED AZAINDOLEOXOACETIC PIPERAZINE DERIVATIVES WITH PROTEASE INHIBITORS - This invention provides compounds having drug and bio-affecting properties, their pharmaceutical compositions and method of use. In particular, the invention is concerned with azaindoleoxoacetyl piperazine derivatives. These compounds possess unique antiviral activity, whether used alone or in combination with other antivirals, antiinfectives, immunomodulators or HIV entry inhibitors. More particularly, the present invention relates to the treatment of HIV and AIDS. | 05-19-2011 |
20110245268 | PHARMACEUTICAL FORMULATIONS OF SUBSTITUTED AZAINDOLEOXOACETIC PIPERAZINE DERIVATIVES WITH PROTEASE INHIBITORS - This invention provides compounds having drug and bio-affecting properties, their pharmaceutical compositions and method of use. In particular, the invention is concerned with azaindoleoxoacetyl piperazine derivatives. These compounds possess unique antiviral activity, whether used alone or in combination with other antivirals, antiinfectives, immunomodulators or HIV entry inhibitors. More particularly, the present invention relates to the treatment of HIV and AIDS. | 10-06-2011 |
20120095017 | PHARMACEUTICAL FORMULATIONS OF SUBSTITUTED AZAINDOLEOXOACETIC PIPERAZINE DERIVATIVES WITH PROTEASE INHIBITORS - This invention provides compounds having drug and bio-affecting properties, their pharmaceutical compositions and method of use. In particular, the invention is concerned with azaindoleoxoacetyl piperazine derivatives. These compounds possess unique antiviral activity, whether used alone or in combination with other antivirals, antiinfectives, immunomodulators or HIV entry inhibitors. More particularly, the present invention relates to the treatment of HIV and AIDS. | 04-19-2012 |
20120238583 | PHARMACEUTICAL FORMULATIONS OF SUBSTITUTED AZAINDOLEOXOACETIC PIPERAZINE DERIVATIVES WITH PROTEASE INHIBITORS - This invention provides compounds having drug and bio-affecting properties, their pharmaceutical compositions and method of use. In particular, the invention is concerned with azaindoleoxoacetyl piperazine derivatives. These compounds possess unique antiviral activity, whether used alone or in combination with other antivirals, antiinfectives, immunomodulators or HIV entry inhibitors. More particularly, the present invention relates to the treatment of HIV and AIDS. | 09-20-2012 |
20130289046 | PHARMACEUTICAL FORMULATIONS OF SUBSTITUTED AZAINDOLEOXOACETIC PIPERAZINE DERIVATIVES WITH PROTEASE INHIBITORS - This invention provides compounds having drug and bio-affecting properties, their pharmaceutical compositions and method of use. In particular, the invention is concerned with azaindoleoxoacetyl piperazine derivatives. These compounds possess unique antiviral activity, whether used alone or in combination with other antivirals, antiinfectives, immunomodulators or HIV entry inhibitors. More particularly, the present invention relates to the treatment of HIV and AIDS. | 10-31-2013 |
20140135342 | PHARMACEUTICAL FORMULATIONS OF SUBSTITUTED AZAINDOLEOXOACETIC PIPERAZINE DERIVATIVES WITH PROTEASE INHIBITORS - This invention provides compounds having drug and bio-affecting properties, their pharmaceutical compositions and method of use. In particular, the invention is concerned with azaindoleoxoacetyl piperazine derivatives. These compounds possess unique antiviral activity, whether used alone or in combination with other antivirals, antiinfectives, immunomodulators or HIV entry inhibitors. More particularly, the present invention relates to the treatment of HIV and AIDS. | 05-15-2014 |
20150087652 | PHARMACEUTICAL FORMULATIONS OF SUBSTITUTED AZAINDOLEOXOACETIC PIPERAZINE DERIVATIVES WITH PROTEASE INHIBITORS - This invention provides compounds having drug and bio-affecting properties, their pharmaceutical compositions and method of use. In particular, the invention is concerned with azaindoleoxoacetyl piperazine derivatives. These compounds possess unique antiviral activity, whether used alone or in combination with other antivirals, antiinfectives, immunomodulators or HIV entry inhibitors. More particularly, the present invention relates to the treatment of HIV and AIDS. | 03-26-2015 |
20150259342 | SUBSTITUTED AZAINDOLEOXOACETIC PIPERAZINE DERIVATIVES - This invention provides compounds having drug and bio-affecting properties, their pharmaceutical compositions and method of use. In particular, the invention is concerned with azaindoleoxoacetyl piperazine derivatives having the Formula I: | 09-17-2015 |
20150329543 | PRODRUGS OF SUBSTITUTED AZAINDOLEOXOACETIC PIPERAZINE DERIVATIVES - This invention provides compounds having drug and bio-affecting properties, their pharmaceutical compositions and method of use. In particular, the invention is concerned with azaindoleoxoacetyl piperazine derivatives. These compounds possess unique antiviral activity, whether used alone or in combination with other antivirals, antiinfectives, immunomodulators or HIV entry inhibitors. More particularly, the present invention relates to the treatment of HIV and AIDS. | 11-19-2015 |
20160075703 | SUBSTITUTED AZAINDOLEOXOACETIC PIPERAZINE DERIVATIVES - This invention provides compounds having drug and bio-affecting properties, their pharmaceutical compositions and method of use. In particular, the invention is concerned with azaindoleoxoacetyl piperazine derivatives having the Formula I: | 03-17-2016 |
Quifen May Xue, Newbury Park, CA US
Patent application number | Description | Published |
---|---|---|
20130030005 | PHARMACEUTICAL FORMULATIONS OF SUBSTITUTED AZAINDOLEOXOACETIC PIPERAZINE DERIVATIVES WITH PROTEASE INHIBITORS - This invention provides compounds having drug and bio-affecting properties, their pharmaceutical compositions and method of use. In particular, the invention is concerned with azaindoleoxoacetyl piperazine derivatives. These compounds possess unique antiviral activity, whether used alone or in combination with other antivirals, antiinfectives, immunomodulators or HIV entry inhibitors. More particularly, the present invention relates to the treatment of HIV and AIDS. | 01-31-2013 |
Shan Xue, Santa Clara, CA US
Patent application number | Description | Published |
---|---|---|
20130279792 | Method and System for Hybrid Reticle Inspection - A semiconductor inspection apparatus performs a hybrid inspection process including cell-to-cell inspection, die-to-die inspection and die-to-golden or die-to-database inspection. The apparatus creates a golden image of a reticle complimentary to portions of the reticle that can be inspected by cell-to-cell inspection or die-to-die inspection. Alternatively, the apparatus creates a reduced database complimentary to portions of the reticle that can be inspected by cell-to-cell inspection or die-to-die inspection. | 10-24-2013 |
Shanhua Xue, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20100128800 | Method and Apparatus for Closed Caption Transcoding - Caption data incorporated in an input coded bit stream conveying a video service is processed by recovering the caption data from the input coded bit stream, decoding the input coded bit stream to form a digital video signal composed of a sequence of frames, embedding the caption data in an ancillary data space of the digital video signal, and encoding the digital video signal to produce an output coded bit stream incorporating the caption data. | 05-27-2010 |
20130083859 | METHOD TO MATCH INPUT AND OUTPUT TIMESTAMPS IN A VIDEO ENCODER AND ADVERTISEMENT INSERTER - A method, a video processing system, and an electronic device are disclosed. A video transcoder may decode a compressed video data frame creating a decoded video data frame. The video transcoder may embed a network presentation timestamp in the decoded video data frame. The video transcoder may re-encode the decoded video data frame creating a transcoded video data frame. A field programmable gate array may compare the network presentation timestamp with a transcoder presentation timestamp to determine a timestamp offset. | 04-04-2013 |
Song Xue, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20100141810 | Bad Pixel Detection and Correction - The invention relates to a method for bad pixel classification for an image sensor having a plurality of sensing elements. The method includes capturing a plurality of images using the image sensor, determining based on a pre-determined criterion, using an image of the plurality of images and a threshold value selected from one or more pre-determined threshold values, whether a sensing element in the image sensor is defective to generate a vote, wherein a threshold parameter associated with the pre-determined criterion is set to the threshold value, tallying the vote to generate a voting count by performing iterations of the determining step using different images of the plurality of images and different threshold values of the one or more pre-determined threshold values, and classifying the sensing element as a bad pixel if the voting count exceeds a pre-determined classification threshold. | 06-10-2010 |
20100141822 | ANALOG MULTIPLEXER CONFIGURED TO REDUCE KICKBACK PERTURBATION IN IMAGE SENSOR READOUT - An analog multiplexer is configured to multiplex a plurality of input analog signal channels into a single output analog signal channel. The analog multiplexer comprises a plurality of input sampling circuits associated with respective ones of the input analog signal channels and an amplifier having an input controllably connectable in turn to each of the input sampling circuits. The analog multiplexer is further configured to connect at least a given one of the input analog signal channels to a sampling element of its corresponding input sampling circuit at a predetermined time prior to connecting the sampling element of that input sampling circuit to the input of the amplifier. The predetermined time is less than a full clock cycle of a sampling clock of the amplifier. The analog multiplexer may be implemented in readout circuitry coupled to a pixel array in an image sensor. | 06-10-2010 |
20140175264 | Pixel Structure and Reset Scheme - An image sensor that includes a pixel array with image pixels with conditional reset circuitry. The pixels can be reset by a combination of row select and column reset signals, which implements the reset function while minimizing the number of extra signal lines. The pixels may also include pinned photodiodes. The manner in which the pinned photodiodes are used reduces noise and allows the quantization of the pixel circuits to be programmable. | 06-26-2014 |
20140267884 | Increasing Dynamic Range Using Multisampling - Methods and systems for increasing the effective dynamic range of an image sensor are disclosed. Each pixel in the sensor is exposed for a respective first exposure time. Each pixel's response to the respective first exposure is measured and compared to threshold values. Based on the pixel's response to the respective first exposure time, an optimal exposure is calculated for each pixel. The optimal exposure time is applied to each pixel by utilizing row-enabled and column-enabled signals at each pixel within the sensor. | 09-18-2014 |
20150281613 | CONDITIONAL-RESET, MULTI-BIT READ-OUT IMAGE SENSOR - An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data. | 10-01-2015 |
20160028985 | THRESHOLD-MONITORING, CONDITIONAL-RESET IMAGE SENSOR - An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data. | 01-28-2016 |
Tao Xue, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20100027663 | INTELLEGENT FRAME SKIPPING IN VIDEO CODING BASED ON SIMILARITY METRIC IN COMPRESSED DOMAIN - This disclosure provides intelligent frame skipping techniques that may be used by an encoding device or a decoding device to facilitate frame skipping in a manner that may help to minimize quality degradation due to the frame skipping. In particular, the described techniques may implement a similarity metric designed to identify good candidate frames for frame skipping. In this manner, noticeable reductions in the video quality caused by frame skipping, as perceived by a viewer of the video sequence, may be reduced relative to conventional frame skipping techniques. The described techniques advantageously operate in a compressed domain. | 02-04-2010 |
20110173360 | SYSTEM AND METHOD OF MONITORING A CENTRAL PROCESSING UNIT IN REAL TIME - A method of monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. | 07-14-2011 |
20120200587 | Method and Apparatus For Content-Based Reduction of Display Power - Methods and devices for displaying content in a power efficient manner are disclosed. In accordance with many embodiments, content is received that includes a plurality of subcomponents, and a subcomponent with a larger surface is darkened so as to generate at least one darkened subcomponent. In addition, a contrast of selected ones of the subcomponents is adjusted so as to enable the selected ones of the subcomponents to be viewed against the darkened subcomponent while others of the plurality of subcomponents are left in their source format. The at least one darkened subcomponent, selected ones of the subcomponents, and the subcomponents that are in their source format are composited into a composite view; and displayed. | 08-09-2012 |
20130061069 | SYSTEM AND METHOD OF MONITORING A CENTRAL PROCESSING UNIT IN REAL TIME - Devices and methods for monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit. | 03-07-2013 |
20150178138 | MULTI-CORE DYNAMIC WORKLOAD MANAGEMENT - A dynamic scheduler is provided that schedules tasks for a plurality of cores based upon current operating characteristics for the cores. The current operating characteristics include a predicted leakage current for each core based upon an analytical model. | 06-25-2015 |
20150338902 | Algorithm For Preferred Core Sequencing To Maximize Performance And Reduce Chip Temperature And Power - Aspects include computing devices, systems, and methods for selecting preferred processor core combinations for a state of a computing device. In an aspect, a state of a computing device containing the multi-core processor may be determined. A number of current leakage ratios may be determined by comparing current leakages of the processor cores to current leakages of the other processor cores. The ratios may be compared to boundaries for the state of the computing device in respective inequalities. A processor core associated with a number of boundaries may be selected in response to determining that the respective inequalities are true. The boundaries may be associated with a set of processor cores deemed preferred for an associated state of the computing device. The processor core present in the set of processor cores for each boundary of a true inequality may be the selected processor core. | 11-26-2015 |
Van Xun Xue, Los Gatos, CA US
Patent application number | Description | Published |
---|---|---|
20140312480 | DOUBLE-SIDE EXPOSED SEMICONDUCTOR DEVICE - A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device. | 10-23-2014 |
Xiaohua Xue, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20140107094 | METHYLENE LINKED QUINOLINYL MODULATORS OF RORyt - The present invention comprises compounds of Formula I. | 04-17-2014 |
20140107096 | HETEROARYL LINKED QUINOLINYL MODULATORS OF RORyt - The present invention comprises compounds of Formula I. | 04-17-2014 |
20140107097 | HETEROARYL LINKED QUINOLINYL MODULATORS OF RORyt - The present invention comprises compounds of Formula I. | 04-17-2014 |
20150105365 | HETEROARYL LINKED QUINOLINYL MODULATORS OF RORgammat - The present invention comprises compounds of Formula I. | 04-16-2015 |
20150105366 | METHYLENE LINKED QUINOLINYL MODULATORS OF RORyt - The present invention comprises compounds of Formula I. | 04-16-2015 |
20150105369 | ALKYL LINKED QUINOLINYL MODULATORS OF RORyt - The present invention comprises compounds of Formula I. | 04-16-2015 |
20150105372 | SECONDARY ALCOHOL QUINOLINYL MODULATORS OF RORyt - The present invention comprises compounds of Formula I. | 04-16-2015 |
20150105404 | PHENYL LINKED QUINOLINYL MODULATORS OF RORyt - The present invention comprises compounds of Formula I. | 04-16-2015 |
20150111870 | QUINOLINYL MODULATORS OF RORyt - The present invention comprises compounds of Formula I. | 04-23-2015 |
Xin Xue, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20110161287 | MIDDLEWARE FILTER AGENT BETWEEN SERVER AND PDA - A content server provides content to a first network device during a data synchronization between the two devices. A middleware filter selectively filters content provided by the content server such that selected content is provided to the first network device. The middleware filter is included within a second network device coupled between the content server and the first network device. The second network device acts as a proxy for the first network device to receive the content provided by the content server. The content is provided from the content server according to a subscription service between the content server and the first network device. The first network device is preferably a personal digital assistant (PDA) and the second network device is preferably a personal computer. Alternatively, the content server is coupled to the first network device, without the second network device coupled in between. In the alternative case, the middleware filter is included within the content server, and the content is selectively provided from the middleware filter, on the content server, to the first network device. | 06-30-2011 |
20130111567 | MIDDLEWARE FILTER AGENT BETWEEN SERVER AND PDA | 05-02-2013 |
Xinwei Xue, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20100228580 | FRAUD DETECTION BASED ON EFFICIENT FREQUENT-BEHAVIOR SORTED LISTS - A computerized method for detecting fraud includes obtaining frequency information on entities in transaction data for at least one individual account, converting frequency information to a frequency variable, and predicting whether an activity is fraudulent in response to the frequency variable. In some embodiments, the frequency variable is used with at least one other variable to predict fraudulent activity. | 09-09-2010 |
20120101937 | FRAUD DETECTION BASED ON EFFICIENT FREQUENT-BEHAVIOR SORTED LISTS - A computerized method for detecting fraud includes obtaining frequency information on entities in transaction data for at least one individual account, converting frequency information to a frequency variable, and predicting whether an activity is fraudulent in response to the frequency variable. In some embodiments, the frequency variable is used with at least one other variable to predict fraudulent activity. | 04-26-2012 |
20150195299 | CYBER SECURITY ADAPTIVE ANALYTICS THREAT MONITORING SYSTEM AND METHOD - A system and method of detecting command and control behavior of malware on a client computer is disclosed. One or more DNS messages are monitored from one or more client computers to a DNS server to determine a risk that one or more client computers is communicating with a botnet. Real-time entity profiles are generated for at least one of each of the one or more client computers, DNS domain query names, resolved IP addresses of query domain names, client computer-query domain name pairs, pairs of query domain name and corresponding resolved IP address, or query domain name-IP address cliques based on each of the one or more DNS messages. Using the real-time entity profiles, a risk that any of the one or more client computers is infected by malware that utilizes DNS messages for command and control or illegitimate data transmission purposes is determined. One or more scores are generated representing probabilities that one or more client computers is infected by malware. | 07-09-2015 |
Yan Xun Xue, Los Gatos, CA US
Patent application number | Description | Published |
---|---|---|
20110024884 | Structure of Mixed Semiconductor Encapsulation Structure with Multiple Chips and Capacitors - A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level. | 02-03-2011 |
20110059593 | Method of Integrating a MOSFET with a Capacitor - A bypass capacitor is directly integrated on top of a MOSFET chip. The capacitor comprises multi layers of conductive material and dielectric material staking on top of each other with connection vias through dielectric layer for connecting different conductive layers. The method of integrating the bypass capacitor comprises repeating steps of depositing a dielectric layer, forming connection vias through the dielectric layer, depositing a conductive layer and patterning the conductive layer. | 03-10-2011 |
20110062506 | Metal Oxide Semiconductor Field Effect Transistor Integrating a Capacitor - A bypass capacitor is directly integrated on top of a MOSFET chip. The capacitor comprises multi layers of conductive material and dielectric material staking on top of each other with connection vias through dielectric layer for connecting different conductive layers. The method of integrating the bypass capacitor comprises repeating steps of depositing a dielectric layer, forming connection vias through the dielectric layer, depositing a conductive layer and patterning the conductive layer. | 03-17-2011 |
20110095409 | Method of Attaching an Interconnection Plate to a Semiconductor Die within a Leadframe Package - A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package. | 04-28-2011 |
20110129961 | Process to form semiconductor packages with external leads - This invention discloses a process for packaging semiconductor device with external leads. The process includes comprises Step 1: providing a lead frame comprising a plurality of lead frame units connected by a plurality of metal beams, each lead frame unit comprising a die pad and a plurality of leads located on opposite sides of the die pad; adhering a semiconductor chip onto each of the die pad, and providing a plurality of metal connections for electrically connecting each chip to its corresponding leads; Step 2 providing a plastic molding material to enclose the plurality of the lead frame units, the metal beams, the chips, and at least portions of the metal connections; Step 3 removing a portion of the plastic molding material above the metal beams to expose the metal beams and portions of the leads in connection with the metal beams; and Step 4 separating each lead frame unit, forming a plurality of individual semiconductor plastic package components with external leads. | 06-02-2011 |
20110193208 | SEMICONDUCTOR PACKAGE OF A FLIPPED MOSFET AND ITS MANUFACTURING METHOD - The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area. | 08-11-2011 |
20110221008 | Semiconductor Packaging and Fabrication Method Using Connecting Plate for Internal Connection - A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding. | 09-15-2011 |
20110227207 | STACKED DUAL CHIP PACKAGE AND METHOD OF FABRICATION - The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication. | 09-22-2011 |
20110284997 | Chip-Exposed Semiconductor Device and Its Packaging Method - A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chi on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices. | 11-24-2011 |
20110309454 | COMBINED PACKAGED POWER SEMICONDUCTOR DEVICE - A combined packaged power semiconductor device includes a flipped top source low-side MOSFET electrically connected to a top surface of a die paddle, a first metal interconnection plate connecting between a bottom drain of a high-side MOSFET or a top source of a flipped high-side MOSFET to a bottom drain of the low-side MOSFET, and a second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally that reduces the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation. | 12-22-2011 |
20120025298 | WAFER LEVEL CHIP SCALE PACKAGE - A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads. | 02-02-2012 |
20120025360 | SEMICONDUCTOR ENCAPSULATION AND METHOD THEREOF - A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves. | 02-02-2012 |
20120032259 | BOTTOM SOURCE POWER MOSFET WITH SUBSTRATELESS AND MANUFACTURING METHOD THEREOF - A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface. | 02-09-2012 |
20120061813 | Package Structure for DC-DC Converter - A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package. | 03-15-2012 |
20120146202 | Top exposed Package and Assembly Method - A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls. | 06-14-2012 |
20120164793 | Power Semiconductor Device Package Method - Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected. | 06-28-2012 |
20120164794 | METHOD OF MAKING A COPPER WIRE BOND PACKAGE - A method for making a wire bond package comprising the step of providing a lead frame array comprising a plurality of lead frame units therein, each lead frame unit comprises a first die pad and a second die pad each having a plurality of tie bars connected to the lead frame array, a plurality of reinforced bars interconnecting the first and second die pads; the reinforced bars are removed after molding compound encapsulation. | 06-28-2012 |
20120175706 | Chip-Exposed Semiconductor Device - A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices. | 07-12-2012 |
20120193695 | Structure of Mixed Semiconductor Encapsulation Structure with Multiple Chips and Capacitors - A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level. | 08-02-2012 |
20120235289 | POWER DEVICE WITH BOTTOM SOURCE ELECTRODE AND PREPARATION METHOD - A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process. | 09-20-2012 |
20120248593 | PACKAGE STRUCTURE FOR DC-DC CONVERTER - A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package. | 10-04-2012 |
20120299119 | STACKED POWER SEMICONDUCTOR DEVICE USING DUAL LEAD FRAME AND MANUFACTURING METHOD - A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip. | 11-29-2012 |
20130026615 | DOUBLE-SIDE EXPOSED SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device. | 01-31-2013 |
20130037917 | WAFER LEVEL CHIP SCALE PACKAGE WITH THICK BOTTOM METAL EXPOSED AND PREPARATION METHOD THEREOF - A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices. | 02-14-2013 |
20130037935 | WAFER LEVEL PACKAGE STRUCTURE AND THE FABRICATION METHOD THEREOF - The present invention relates to a package for semiconductor device and the fabrication method for integrally encapsulating a whole semiconductor chip within a molding compound. In the semicondcutor device package, bonding pads distributed on the top of the chip are redistributed into an array of redistributed bonding pads located in an dielectric layer by utilizing the redistribution technique. The electrodes or signal terminals on the top of the semiconductor chip are connected to an electrode metal segment on the bottom of the chip by conductive materials filled in through holes formed in a silicon substrate of a semiconductor wafer. Furthermore, the top molding portion and the bottom molding portion seal the semiconductor chip completely, thus providing optimum mechanical and electrical protections. | 02-14-2013 |
20130037962 | WAFER LEVEL PACKAGING STRUCTURE WITH LARGE CONTACT AREA AND PREPARATION METHOD THEREOF - A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package. | 02-14-2013 |
20130075884 | SEMICONDUCTOR PACKAGE WITH HIGH-SIDE AND LOW-SIDE MOSFETS AND MANUFACTURING METHOD - A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction. | 03-28-2013 |
20130130443 | METHOD FOR PACKAGING ULTRA-THIN CHIP WITH SOLDER BALL THERMO-COMPRESSION IN WAFER LEVEL PACKAGING PROCESS - The invention generally relates to a packaging method of an ultra-thin chip, more specifically, the invention relates to a method for packaging the ultra-thin chip with solder ball thermo-compression in wafer level packaging process. The method starts with disposing solder balls on metal pads arranged on the front surface of semiconductor chips that are formed at the front surface of a semiconductor wafer. The solder balls are soften by heating the wafer, a compression plate is applied with a pressure on the top ends of the solder balls thus forming a co-planar top surface at the top ends of the solder balls. A molding compound is deposited on the front surface of the wafer with the top ends of the solder balls exposed. The wafer is then ground from its back surface to reduce its thickness to achieve ultra-thin chip. | 05-23-2013 |
20130134502 | WAFER LEVEL CHIP SCALE PACKAGE - A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads. | 05-30-2013 |
20130210195 | PACKAGING METHOD OF MOLDED WAFER LEVEL CHIP SCALE PACKAGE (WLCSP) - A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove. | 08-15-2013 |
20130210215 | PACKAGING METHOD WITH BACKSIDE WAFER DICING - A packaging method with backside wafer dicing includes the steps of forming a support structure at the front surface of the wafer then depositing a metal layer on a centre area of the backside of the wafer after grinding the wafer backside to reduce the wafer thickness; detecting from the backside of the wafer sections of scribe lines formed in the front surface in the region between the edge of the metal layer and the edge of the wafer and cutting the wafer and the metal layer from the wafer backside along a straight line formed by extending a scribe line section detected from the wafer backside. | 08-15-2013 |
20130221507 | ALUMINUM ALLOY LEAD-FRAME AND ITS USE IN FABRICATION OF POWER SEMICONDUCTOR PACKAGE - A semiconductor package is provided with an Aluminum alloy lead-frame without noble metal plated on the Aluminum base lead-frame. Aluminum alloy material with proper alloy composition and ratio for making an aluminum alloy lead-frame is provided. The aluminum alloy lead-frame is electroplated with a first metal electroplating layer, a second electroplating layer and a third electroplating layer in a sequence. The lead-frame electroplated with the first, second and third metal electroplating layers is then used in the fabrication process of a power semiconductor package including chip connecting, wire bonding, and plastic molding. After the molding process, the area of the lead-frame not covered by the molding compound is electroplated with a fourth metal electroplating layer that is not easy to be oxidized when exposing to air. | 08-29-2013 |
20130309816 | SEMICONDUCTOR ENCAPSULATION METHOD - A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves. | 11-21-2013 |
20140001617 | METHOD OF USING BONDING BALL ARRAY AS HEIGHT KEEPER AND PASTE HOLDER IN SEMICONDUCTOR DEVICE PACKAGE | 01-02-2014 |
20140035116 | Top Exposed Semiconductor Chip Package - A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls. | 02-06-2014 |
20140054758 | STACKED DUAL CHIP PACKAGE HAVING LEVELING PROJECTIONS - The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication. | 02-27-2014 |
20140070386 | Semiconductor Package with Connecting Plate for Internal Connection - A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding. | 03-13-2014 |
20140080263 | Semiconductor Packaging Method Using Connecting Plate for Internal Connection - A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding. | 03-20-2014 |
20140091446 | SEMICONDUCTOR DEVICE EMPLOYING ALUMINUM ALLOY LEAD-FRAME WITH ANODIZED ALUMINUM - A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices. | 04-03-2014 |
20140117523 | STACKED DUAL-CHIP PACKAGING STRUCTURE AND PREPARATION METHOD THEREOF - The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate. | 05-01-2014 |
20140141567 | Flip-chip Semiconductor Chip Packing Method - Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected. | 05-22-2014 |
20140191334 | STACKED POWER SEMICONDUCTOR DEVICE USING DUAL LEAD FRAME - A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip. | 07-10-2014 |
20140242756 | METHOD FOR PREPARING SEMICONDUCTOR DEVICES APPLIED IN FLIP CHIP TECHNOLOGY - A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices. | 08-28-2014 |
20140264802 | Semiconductor Device with Thick Bottom Metal and Preparation Method Thereof - A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body. | 09-18-2014 |
20140264805 | Semiconductor Package And Fabrication Method Thereof - A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies. | 09-18-2014 |
20140315350 | WAFER PROCESS FOR MOLDED CHIP SCALE PACKAGE (MCSP) WITH THICK BACKSIDE METALLIZATION - A wafer process for MCSP comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer covering metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer and a thick metal layer at bottom surface of wafer in recessed space in a sequence; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and the metal seed and metal layers along the scribe line. | 10-23-2014 |
20140319601 | BOTTOM SOURCE SUBSTRATELESS POWER MOSFET - A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface. | 10-30-2014 |
20140361418 | A SEMICONDUCTOR PACKAGE OF A FLIPPED MOSFET - The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area. | 12-11-2014 |
20140361419 | POWER CONTROL DEVICE AND PREPARATION METHOD THEREOF - A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon. | 12-11-2014 |
20140361420 | HYBRID PACKAGING MULTI-CHIP SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF - A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure. | 12-11-2014 |
20150021753 | PACKAGING STRUCTURE OF A SEMICONDUCTOR DEVICE - A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies. | 01-22-2015 |
20150021780 | THIN POWER DEVICE AND PREPARATION METHOD THEREOF - A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back surface of the substrate, a through opening opened from the front surface and through the substrate exposing a third contact pad at the back surface of the substrate, a semiconductor chip embedded into the through opening with a back metal layer at a back surface of the semiconductor chip attached on the third contact pad, and a plurality of conductive structures electrically connecting electrodes at a front surface of the semiconductor chip with the corresponding first contact pads in the first sets of first contact pads. | 01-22-2015 |
20150069590 | Multi-Die Power Semiconductor Device Packaged On a Lead Frame Unit with Multiple Carrier Pins and a Metal Clip - A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon. | 03-12-2015 |
20150087114 | METHOD FOR PACKAGING A POWER DEVICE WITH BOTTOM SOURCE ELECTRODE - A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process. | 03-26-2015 |
20150162257 | METHOD AND STRUCTURE FOR WAFER LEVEL PACKAGING WITH LARGE CONTACT AREA - A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package. | 06-11-2015 |
20150189764 | PREPARATION METHOD OF A THIN POWER DEVICE - A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back surface of the substrate, a through opening opened from the front surface and through the substrate exposing a third contact pad at the back surface of the substrate, a semiconductor chip embedded into the through opening with a back metal layer at a back surface of the semiconductor chip attached on the third contact pad, and a plurality of conductive structures electrically connecting electrodes at a front surface of the semiconductor chip with the corresponding first contact pads in the first sets of first contact pads. | 07-02-2015 |
20150236005 | Method of Hybrid Packaging a Lead Frame Based Multi-Chip Semiconductor Device with Multiple Interconnecting Structures - A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure. | 08-20-2015 |
20150243589 | COMBINED PACKAGED POWER SEMICONDUCTOR DEVICE - A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation. | 08-27-2015 |
20150249045 | POWER SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF - A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units. | 09-03-2015 |
20150262925 | SEMICONDUCTOR DEVICE EMPLOYING ALUMINUM ALLOY LEAD-FRAME WITH ANODIZED ALUMINUM - A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices. | 09-17-2015 |
20150279766 | SEMICONDUCTOR DEVICE WITH THICK BOTTOM METAL AND PREPARATION METHOD THEREOF - A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body. | 10-01-2015 |
20160056096 | POWER SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF - A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units. | 02-25-2016 |
20160056098 | SEMICONDUCTOR DEVICE EMPLOYING ALUMINUM ALLOY LEAD-FRAME WITH ANODIZED ALUMINUM - A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices. | 02-25-2016 |
20160064251 | METHOD AND STRUCTURE FOR WAFER LEVEL PACKAGING WITH LARGE CONTACT AREA - A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package. | 03-03-2016 |
20160093559 | SEMICONDUCTOR PACKAGE WITH SMALL GATE CLIP AND ASSEMBLY METHOD - A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads. | 03-31-2016 |
20160093560 | POWER SEMICONDUCTOR DEVICE AND THE PREPARATION METHOD - An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip. | 03-31-2016 |
20160104661 | A SEMICONDUCTOR PACKAGE OF A FLIPPED MOSFET - The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area. | 04-14-2016 |
Yan Yun Xue, Los Gatos, CA US
Patent application number | Description | Published |
---|---|---|
20150357267 | COMBINED PACKAGED POWER SEMICONDUCTOR DEVICE - A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation. | 12-10-2015 |
Yi Xue, East Palo Alto, CA US
Patent application number | Description | Published |
---|---|---|
20130018307 | Multi-Lumen Steerable Catheter - A steerable multi-lumen catheter is provided which can be used in cardiology procedures where the catheter allows clinicians to access the small pulmonary arteries for monitoring and performing interventional procedures. The catheter allows precise changes in direction and simplifies challenging navigation procedures such as crossing a thick and calcified aortic valve with a wire. A bendable tip aids navigation during interventional radiology and neurology procedures to enter tortuous vessels or aneurysms. | 01-17-2013 |
Yisheng Xue, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20150312056 | APPARATUS AND METHODS FOR ESTIMATING OPTICAL ETHERNET DATA SEQUENCES - A receiver is disclosed that includes a slicer having an input to receive a sequence of symbols exhibiting inter-symbol-interference (ISI). The slicer determines a state associated with each symbol based on a threshold. A feedback equalization unit is coupled to the slicer to apply equalization to the symbol fed to the slicer input based on prior detected symbol states. A Least-Mean-Square (LMS) unit cooperates with the slicer and feedback equalization unit to estimate a channel impulse response based on the equalized symbols. The LMS unit feeds the estimated channel impulse response to a Maximum-Likelihood-Sequence-Estimation (MLSE) unit to generate an estimated sequence of bits based on the estimated channel impulse response. | 10-29-2015 |
20150326382 | INITIALIZATION OF TIMING RECOVERY AND DECISION-FEEDBACK EQUALIZATION IN A RECEIVER - A method of initializing a receiver is performed during an initialization mode. Timing offset values for a timing recovery circuit are repeatedly selected. For each selected timing offset value, timing recovery is performed using the timing offset value and groups of weights for a decision feedback equalizer are repeatedly selected. Each selected group of weights is used to perform blind decision feedback equalization. For each selected group of weights, a metric indicating data reception quality is computed. A timing offset value and a group of weights are chosen based on the computed metrics. | 11-12-2015 |
20150372695 | METHOD AND APPARATUS OF LDPC DECODER WITH LOWER ERROR FLOOR - A method of error correction using low density parity check (LDPC) codes is disclosed. A communications device receives a codeword and detects one or more bit errors in the received codeword using an LDPC code. The device then generates a corrected codeword based, at least in part, on a set of unsatisfied check nodes of the LDPC code. The device may determine that the one or more bit errors are associated with an absorption set of the LDPC code. The device may also determine a plurality of candidate codewords based on the set of unsatisfied check node and select the corrected codeword from the plurality of candidate codewords. Each of the plurality of candidate codewords may represent a valid codeword associated with the LDPC code. | 12-24-2015 |
20150372803 | METHOD AND APPARATUS FOR DATA AIDED TIMING RECOVERY IN 10GBASE-T SYSTEM - A method of data-aided timing recovery for Ethernet systems is disclosed. A first device negotiates a pseudorandom number sequence with a second device and receives a data signal from the second device. The first device samples the received data signal to recover a first training sequence. The first device also generates a second training sequence based on the pseudorandom number sequence. The second training sequence is then synchronized with the first training sequence. The synchronized second training sequence is used to align a receive clock signal of the first device with the data signal received from the second device. | 12-24-2015 |
Yuanchao Xue, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20150299698 | METHODS FOR ENGINEERING NON-NEURONAL CELLS INTO NEURONS AND USING NEWLY ENGINEERED NEURONS TO TREAT NEURODEGENERATIVE DISEASES - The invention provides compositions and in vivo, ex vivo and in vitro methods for trans-differentiation of or re-programming mammalian cells to functional neurons. In particular, the invention provides methods for engineering non-neuronal cells into neurons, including fully functional human neuronal cells, and methods for engineering non-neuronal cells into neurons, e.g., fully functional human neuronal cells, in the brain to treat a neurodegenerative disease. In alternative embodiments, the invention provides compositions comprising re-differentiated or re-programmed mammalian cells, such as human cells, of the invention. The invention also provides compositions and methods for direct reprogramming of cells to a second phenotype or differentiated phenotype, such as a neuron, including a fully functional human neuronal cell. The invention also provides formulations, products of manufacture, implants, artificial organs or tissues, or kits, comprising a trans-differentiated or re-programmed cell of the invention, e.g., a fully functional human neuronal cell. | 10-22-2015 |
Yun Xue, Sunnyvale, CA US
Patent application number | Description | Published |
---|---|---|
20140032531 | SYSTEM AND METHOD FOR A SERVICE METERING FRAMEWORK IN A NETWORK ENVIRONMENT - A method is provided in one example embodiment and includes causing generation of a metered record associated with a metering event of an application executed within a cloud-based computing system, the metered record including a metering attribute and a corresponding value, the corresponding value being determined substantially simultaneous to a runtime execution of the application, and facilitating searching for the metered record based on the metering attribute and the corresponding value of the metering attribute. In specific embodiments, the metered record is communicated using a REpresentational State Transfer (REST) Application Programming Interface (API). In an example embodiment, the notification of the metering event can be received by any one of a REST API, a Java Messaging Service listener, an Extensible Messaging and Presence Protocol (XMPP) listener, or a metering plugin. | 01-30-2014 |
20150149628 | SYSTEM AND METHOD FOR A SERVICE METERING FRAMEWORK IN A NETWORK ENVIRONMENT - A method is provided in one example embodiment executed at a service metering framework (SMF) engine including a processor, and includes interfacing, by an event listener at the SMF engine, with an application being executed in a cloud by a remote client device, detecting a metering event associated with the application during execution of the application, receiving a value of at least one metering attribute associated with the metering event, and storing the at least one metering attribute and the value as a formatted metered record in a SMF database searchable according to the metering attribute. In a specific embodiment, the event listener exposes an application programming interface (API) of the SMF engine to the application to facilitate definitions of the metering event and the at least one metering attribute in the application. | 05-28-2015 |
Zhen Xue, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20120078995 | SYSTEM AND METHOD FOR WARMING AN OPTIMIZATION DEVICE - A system and method are provided for warming a network intermediary (e.g., a proxy, a transaction accelerator) to enable it to provide effective optimization (e.g., data reduction) without a cold start. When a pair of network intermediaries cooperate to optimize a communication connection (e.g., between a client and a server), either or both intermediaries may form branch channels with one or more peers. Via these branch channels, the intermediaries may forward optimization information such as data references received from the other intermediary (i.e., in place of data segments, as part of a data reduction scheme), and/or resolve unknown references. | 03-29-2012 |