Patent application number | Description | Published |
20090054023 | AUDIO AMPLIFIER AND METHODS OF GENERATING AUDIO SIGNALS - Audio amplifiers and methods of generating audio signals are disclosed. A disclosed example amplifier comprises a first driver to receive a first signal; a second driver to receive a second signal; a configurable signal delivery circuit; and a mode selector in communication with the first and second drivers to selectively configure the signal delivery circuit in a voltage boost mode or a voltage buck-boost mode based on a characteristic of the input signal. | 02-26-2009 |
20120235745 | VARIABLE GAIN AMPLIFIER - An apparatus and method are provided. Generally, an input signal is applied across a main path (through an input network) and across a cancellation path (through a cancellation circuit). The cancellation circuit subtracts a cancellation current from the main path as part of the control mechanism, where the magnitude of the cancellation current is based on a gain control signal (that has been linearized to follow a control voltage). | 09-20-2012 |
20130113566 | VARIABLE GAIN AMPLIFIER - An apparatus and method are provided. Generally, an input signal is applied across a main path (through an input network) and across a cancellation path (through a cancellation circuit). The cancellation circuit subtracts a cancellation current from the main path as part of the control mechanism, where the magnitude of the cancellation current is based on a gain control signal (that has been linearized to follow a control voltage). | 05-09-2013 |
20130264973 | METHOD AND APPARATUS TO DRIVE A LINEAR RESONANT ACTUATOR AT ITS RESONANT FREQUENCY - A method for driving a Linear Resonant Actuator (LRA) is provided. During a first off interval, the back-emf of the LRA is measured. During a first off interval, a timer is started when the back-emf reaches a predetermined threshold, and after a predetermined delay has lapsed following the back-emf reaching the predetermined threshold during the first off interval, the LRA is driven over a drive interval having a length and drive strength. A second off interval is entered following the drive interval, and during the second off interval, the back-emf of the LRA is measured. During the second off interval, the timer is stopped when the back-emf reaches the predetermined threshold. The value from the timer that corresponds to the duration between the back-emf reaching the predetermined threshold during the first off interval and the back-emf reaching the predetermined threshold during the second off interval determines the length. | 10-10-2013 |
20130334987 | DRIVER FOR CAPACITIVE LOADS - A method for driving a piezoelectric transducer is provided. An input signal is received. At least one of a plurality of modes is selected for a buck-boost stage from a comparison of a desired voltage on a capacitor to a first threshold and a second threshold, where the desired voltage is determined from the input signal. The piezoelectric transducer is then driven substantially within the audio band using the desired voltage on the capacitor using an H-bridge that changes state with each zero-crossing. | 12-19-2013 |
20140320045 | CIRCUITS AND METHODS FOR DRIVING ECCENTRIC ROTATING MASS MOTORS - Circuits and methods for driving ERM motors are disclosed herein. An embodiment of the circuit includes an input, wherein an input signal is receivable at the input and a back EMF signal. The circuit operates in a closed loop mode when the back EMF signal is less than a lower threshold value and the difference between the value of the input signal and the back EMF signal indicates that the velocity of the motor needs to increase. The circuit operates in an open loop mode when the back EMF signal is greater than a high threshold value and the difference between the value of the input signal and the back EMF signal indicates that the velocity of the motor needs to increase. | 10-30-2014 |
Patent application number | Description | Published |
20090108884 | High Side Boosted Gate Drive Circuit - A high-side boosted gate drive circuit is disclosed. In a particular example, an output driver is described, comprising a switching device configured to selectively conduct current in response to a charge being present at a control terminal for a duty cycle, a charging device configured to deliver charge to the control terminal based on the first duty cycle, a charge control device configured to selectively couple the charging device to deliver charge to the control terminal and to selectively decouple the charging device from the control terminal to charge the charging device, and a discharge control device configured to remove charge from the control terminal. | 04-30-2009 |
20130106514 | HIGH VOLTAGE DRIVER AMPLIFIER FOR PIEZO HAPTICS | 05-02-2013 |
20130194856 | Reference and Read OTP Sensors - The present disclosure provides a reference one time programmable (OTP) cell, wherein the reference OTP cell can generate a reference bias current in at least a programmed-on configuration;a current mirror coupled to an output of the OTP cell, wherein the current mirror includes at least two gate-coupled field effect transistors (FETs); wherein a current gain of a second of the two FETS is a fraction less than one of a first of the at least two gate-coupled FETs; a programmable OTP memory bit element (OTPMBE) coupled to an input of the current mirror; and a comparator having an input coupled to a node between the OTPMBE and the current mirror. | 08-01-2013 |
20150229254 | ANGULAR FREQUENCY EXTRACTOR FOR CONTROLLING A BRUSHED DC MOTOR - An apparatus includes a motor driver configured to drive a motor across a pair of input terminals to the motor and a current sense unit configured to sense the motor's electrical current amplitude. Further, an angular frequency extractor is operatively coupled to the motor driver and the current sense unit and configured to detect discontinuities in the motor's electrical current amplitude. The angular frequency extractor also is configured to determine a time period for one complete revolution of a rotor of the motor and to generate a feedback signal based on the determined period to control an angular frequency of the motor. The feedback signal may be used to adjust how the motor is being driven (e.g., to slow the motor down or speed it up). | 08-13-2015 |
Patent application number | Description | Published |
20110171719 | Prevention and Remediation of Petroleum Reservoir Souring and Corrosion by Treatment with Virulent Bacteriophage - Petroleum reservoir souring, caused by microbially induced production of hydrogen sulfide and other sulfur compounds, and the attendant corrosion are remediated by isolating bacteriophage(s) specific for the problematic bacteria (target bacteria) and adding an effective amount of such bacteriophage(s) to water introduced into or resident in the reservoir to kill at least some of the target bacteria. Suitable virulent bacteriophage(s) may be indigenous to the water, located in surrounding areas, or taken from a known banked stock. Means of concentrating solutions of bacteriophage(s) are also disclosed. | 07-14-2011 |
20120040329 | Process For Continuous Production Of Bacteriophage - As bacteriophage use in industrial application grows there is a need for commercial quantities of identified bacteriophage. This invention discloses a continuous flow bacteriophage proliferation process that can provide commercial quantities of desired bacteriophage in concentrations suitable for industrial use. Host bacteria and virulent bacteriophage are fed into a reactor vessel where the phage attach to, infect and lyse the host bacteria providing multiple replications of it and coincidentally concentrating the phage. | 02-16-2012 |
20120040439 | Use of Prokaryote Viruses to Remediate Bio-Fouling - This invention provides a process for control in oil and gas wells and related facilities of prokaryote caused souring, fouling and corrosion by reduction of problematic prokaryotes with naturally occurring lysing organisms, particularly sulfate-reducing prokaryotes by proliferating suitable virulent lysing organisms under conditions in which problematic prokaryotes thrive, including in a gas production wellbore. The process provides in situ proliferation of virulent lysing organism in a wellbore by providing both virulent lysing organisms and their host prokaryotes to selectively grow an effective control amount and concentrations of lysing organisms in a well formation. | 02-16-2012 |
20120168372 | Prevention and Remediation of Petroleum Reservoir Souring and Corrosion by Treatment with Virulent Bacteriophage - Petroleum reservoir souring caused by microbially induced production of hydrogen sulphide and other sulphur compounds and the attendant corrosion are remediated by isolating bacteriophage specific for the problematic bacteria (target bacteria) and adding an effective amount of such bacteriophage to water introduced into or resident in the reservoir to kill at least some of the target bacteria. Suitable virulent bacteriophage may be indigenous in the water or located in surrounding areas or taken from a known banked stock. Means of concentrating solutions of bacteriophage are also disclosed. | 07-05-2012 |
20140061123 | Prevention and Remediation of Petroleum Reservoir Souring and Corrosion by Treatment with Virulent Bacteriophage - There is provided a safe, natural, environmentally sound means of controlling bacterial contamination, corrosion, and souring of oil and gas wells and reservoirs that result from bacteria-contaminated water in a well. In one aspect it is a process for remediation of souring of petroleum reservoirs and coalbeds by adding to the water used in flooding and “fracing” operations an effective amount of virulent (non-lysogenic) bacteriophages (phages) specific for problematic target bacteria. The invention also provides a means for combating loss of effectiveness of bacterial control by staging bacteriophage production and application to control dominant and sub-dominant target bacteria in a community of target bacteria. | 03-06-2014 |
20140102975 | PROCESS FOR REDUCING BIO-CORROSION IN WATER SYSTEMS - Bacterial contamination of industrial water systems lead to bacterial induced corrosion. This invention provides a method for control of corrosion of industrial water systems caused by bacteria by the destruction of targeted problematic bacteria with naturally occurring, non-engineered bacteriophage virulent for targeted bacteria. The invention also provides a staged sequencing of control to adapt to changing conditions. | 04-17-2014 |
20140273159 | Staged Bacteriophage Remediation of Target Bacteria - A process for remediation of target bacteria, particularly sulfur reducing bacteria (SRB), in waters (“target water”) having a multiplicity and diverse host target bacteria by employing serial or staged bacteria culturing and lysing of dominant bacteria. Remediation of sulfur reducing bacteria (SRB) is effected by application of a series of bacteriophage isolated from the staged culturing and bacteriophage lysing of successive aliquots of waters containing a multiplicity of SRB. | 09-18-2014 |
Patent application number | Description | Published |
20100218884 | Method of manufacture for reinforcing inner tubes within high pressure reinforced hose - A Method of Manufacture for reinforcing the inner tube of reinforced high pressure flexible hose. The method essentially places carbon fibre filaments running axially (longitudinally) with the hose in the first several layers of the built-up inner tube. The filaments are placed as near as possible to the inner wall of the inner tube so that the fibres do not interfere with the overall bending radius of the reinforced high pressure flexible hose. The strengthened inner tube is far more capable of meeting the new API (October 2006) temperature and flexibility (pulsation) standards for oil field equipment reinforced rubber hose. | 09-02-2010 |
20110272943 | CONNECTOR FOR HIGH PRESSURE REINFORCED RUBBER HOSE - An improved swage fitted end connector for high pressure large diameter reinforced flexible rubber hose utilizing sine-wave locking of the reinforcement and particularly suited to the petrochemical and drilling industries. Two embodiments of the improved connector for use with wire reinforced thin internal tube hose are disclosed: one with a diameter of 3-inches and for burst pressures up to 20,000 psi and the other for a diameter of 5-inches and for burst pressures up to 18,000 psi. All of the improved connectors will withstand the rated burst pressure of the hose without pumping off or leaking thus any hose that utilizes the improved device will fail before the connector pops off the hose. The improved connectors are designed to meet or exceed the new API temperature ranges and new API flexible specification levels which became effective in October 2006. | 11-10-2011 |
20140291981 | END CONNECTOR FOR HIGH PRESSURE HIGH TEMPERATURE REINFORCED RUBBER HOSE - An improved swage fitted end connector for high pressure large diameter reinforced flexible rubber hose utilizing sine-wave locking of the reinforcement and carefully machined internal grippers to cause a portion of the reinforcement wire to connect directly to the connector and particularly suited to the petrochemical and drilling industries is disclosed. A connector for use with high temperature-high pressure large diameter wire reinforced rubber hose is discussed along with other embodiments. All connectors will withstand the rated burst pressure and temperature of the hose without pumping off or leaking; thus, any hose that utilizes the improved device will fail before the connector pops off of the hose. Two alternate embodiments are discussed. | 10-02-2014 |
20150176735 | LABYRINTH SEAL SWAGE COUPLING FOR HIGH TEMPERATURE/PRESSURE REINFORCED RUBBER HOSE AND METHODS OF ATTACHMENT - A Specialized Fitting and a Method of Manufacture for swaging hose couplings to high pressure, high temperature reinforced rubber hose having a corrugated or smooth plastic/nylon/elastomer or metal lining (inner tube). The method discloses four embodiments for manufacturing a complete hose assembly from stock hose and discloses a technique for ensuring a labyrinth seal between the inner tube and the hose coupling. The method results in a hose assembly that will meet or exceed the requirements of the American Petroleum Institute for Choke and Kill Hose and/or Rotary Drilling hose. | 06-25-2015 |
Patent application number | Description | Published |
20080286933 | INTEGRATED CIRCUIT INDUCTOR WITH INTEGRATED VIAS - Integrated circuit inductors ( | 11-20-2008 |
20090096031 | DIFFERENTIAL POLY DOPING AND CIRCUITS THEREFROM - A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device. Fabrication of the integrated circuit is then completed, wherein the integrated circuit includes at least one first region formed in the masked portion lacking the first dopant in the polysilicon gates from the pre-gate etch implant and at least one second region formed in the unmasked portion having the first dopant in the polysilicon gates from the pre-gate etch implant. | 04-16-2009 |
20090098694 | CD GATE BIAS REDUCTION AND DIFFERENTIAL N+ POLY DOPING FOR CMOS CIRCUITS - A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices. | 04-16-2009 |
20100327335 | METHOD OF BUILDING COMPENSATED ISOLATED P-WELL DEVICES - Electrical device structures constructed in an isolated p-well that is wholly contained within a core n-well. Methods of forming electrical devices within an isolated p-well that is wholly contained within a core n-well using a baseline CMOS process flow. | 12-30-2010 |
20100327361 | LOW COST SYMMETRIC TRANSISTORS - An integrated circuit is disclosed containing two types of MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. | 12-30-2010 |
20100327374 | LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS - An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed. | 12-30-2010 |
20110133880 | INTEGRATED CIRCUIT INDUCTOR WITH INTEGRATED VIAS - Integrated circuit inductors ( | 06-09-2011 |
20110156144 | Compensated Isolated P-WELL DENMOS Devices - An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. | 06-30-2011 |
20110248347 | LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS - An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed. | 10-13-2011 |
20120261766 | Compensated Isolated P-WELL DENMOS Devices - An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. | 10-18-2012 |
Patent application number | Description | Published |
20120045874 | CMOS INTEGRATION METHOD FOR OPTIMAL IO TRANSISTOR VT - Various embodiments provide methods for fabricating dual supply voltage CMOS devices with a desired I/O transistor threshold voltage. The dual supply voltage CMOS devices can be fabricated in a semiconductor substrate that includes isolated regions for a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor. Specifically, the fabrication can first set and/or adjust the threshold voltage (V | 02-23-2012 |
20120108020 | LOW TEMPERATURE COEFFICIENT RESISTOR IN CMOS FLOW - A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow. | 05-03-2012 |
20120119301 | METHOD FOR IMPROVING DEVICE PERFORMANCE USING DUAL STRESS LINER BOUNDARY - An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. | 05-17-2012 |
20140374836 | METHOD FOR IMPROVING DEVICE PERFORMANCE USING DUAL STRESS LINER BOUNDARY - An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. | 12-25-2014 |
20150187772 | OPTIMIZED LAYOUT FOR RELAXED AND STRAINED LINER IN SINGLE STRESS LINER TECHNOLOGY - An integrated circuit and method with a single stress liner film and a stress relief implant where the distance of the stress relief implant to the transistors is adjusted for improved transistor performance. | 07-02-2015 |
Patent application number | Description | Published |
20120043612 | Device Layout in Integrated Circuits to Reduce Stress from Embedded Silicon-Germanium - An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-channel MOS transistors have source/drain regions formed in eSiGe, while the locations at which p-type guard rings are formed are masked from the recess etch and the eSiGe selective epitaxy. Defects caused by concentrated crystal strain at the corners of guard rings and similar structures are eliminated. | 02-23-2012 |
20120074973 | ON-DIE PARAMETRIC TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS - An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters. | 03-29-2012 |
20120074980 | SCRIBE LINE TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS FOR ICs INCLUDING MOS DEVICES - An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters. | 03-29-2012 |
20120078604 | METHOD FOR MINIMIZING TRANSISTOR AND ANALOG COMPONENT VARIATION IN CMOS PROCESSES THROUGH DESIGN RULE RESTRICTIONS - Various embodiments provide an integrated circuit (IC) design method and design kit for reducing context variations through design rule restrictions. The design method can be applied to components (e.g., analog blocks) with a context variation in an IC design. By drawing a cover layer over such components, context-variation-reduction design rule restrictions can be applied to reduce the context variations. | 03-29-2012 |
20120091531 | Flexible Integration of Logic Blocks with Transistors of Different Threshold Voltages - An integrated circuit constructed according to an arrangement of logic blocks, with one or more logic blocks including transistors of a different threshold voltage than in other logic blocks. Spacing between neighboring active regions of different threshold voltages is minimized by constraining the angle of implant for the threshold adjust implant, and by constraining the thickness of the mask layer used with that implant. These constraints ensure adequate implant of dopant into the channel region while blocking the implant into channel regions not subject to the threshold adjust, while avoiding shadowing from the mask layer. Efficiency is attained by constraining the direction of implant to substantially perpendicular to the run of the gate electrodes in the implanted regions. | 04-19-2012 |
20120205748 | DEVICE LAYOUT IN INTEGRATED CIRCUITS TO REDUCE STRESS FROM EMBEDDED SILICON-GERMANIUM - An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-channel MOS transistors have source/drain regions formed in eSiGe, while the locations at which p-type guard rings are formed are masked from the recess etch and the eSiGe selective epitaxy. Defects caused by concentrated crystal strain at the corners of guard rings and similar structures are eliminated. | 08-16-2012 |
20120280324 | SRAM STRUCTURE AND PROCESS WITH IMPROVED STABILITY - An SRAM memory cell with reduced SiGe formation area using a gate extension ( | 11-08-2012 |
20130200466 | INTEGRATED CIRCUIT HAVING SILICIDE BLOCK RESISTOR - A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor. | 08-08-2013 |
20150187585 | DUMMY GATE PLACEMENT METHODOLOGY TO ENHANCE INTEGRATED CIRCUIT PERFORMANCE - A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an integrated circuit. | 07-02-2015 |