Yang, Jhubei City
Chih-Chin "alan" Yang, Jhubei City TW
Patent application number | Description | Published |
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20100207850 | MATRIX STRUCTURE OF LED (LIGHT EMITTING DIODE) - The present invention is to provide a matrix structure of LED that is a matrix composed of two horizontal scan lines and two vertical scan lines. There is separately set the first and second LEDs with their one ends connect-assemble with the horizontal line and their other ends connect-assemble with the vertical line at the cross points of each horizontal scan line and each vertical scan line. And, each LED has two or more than two light source points with their positive/plus and negative/minus circuitry reversed. By utilizing the method of alternately outputting the positive/plus and negative/minus voltages to horizontal scan lines and vertical scan lines, the four first LEDs and four second LEDs are driven simultaneously. And, while the positive/plus and negative/minus voltages are alternately output, every LEDs all have one light source points lightened such that a matrix is formed to control sixteen LEDs and has the form with eight light source points alternately flashing. | 08-19-2010 |
He-Shun Yang, Jhubei City TW
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20100327301 | LED LIGHTING DEVICE - An LED lighting device includes a circuit board, a plurality of LED units, a waterproof layer and a middle layer. The LED units are disposed on the circuit board by surface mounted way. The light beam emitted from the LED units emits from the light-emitting surface. The waterproof layer wraps the circuit board and the LED units. The middle layer is located between the light-emitting surface and the water-proof layer. The middle layer extends from a direction of the LED units being disposed on the circuit board so that the middle layer fully covers the light-emitting surface. The light beams passing through the light-emitting surface enters into the waterproof layer via the middle layer. Thereby, the middle layer is located between the LED units and the waterproof layer to make the color of the light beam be more uniform. | 12-30-2010 |
Rhey Yang, Jhubei City TW
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20100307602 | System and Method for Processing High Purity Materials - Systems and methods for processing high purity materials are disclosed. A unit operation processes a material stream, an operational parameter of the unit operation is monitored, and a standby unit is charged with pressurized gas to achieve system pressure. The material stream is diverted to the standby unit in response to the operational parameter of the unit operation registering a threshold value. Flow exiting the standby unit is first vented via an outlet, and then directed toward a point of use after the pressurized gas has been purged. The unit operation may then be serviced and subsequently brought back online. A second unit operation may process a second material stream simultaneously, and the second material stream may be periodically diverted to the standby unit in like manner, thus reducing line pressure variation. The disclosed method may be performed manually or implemented automatically through use of a controller. | 12-09-2010 |
20120111413 | System and Method for Delivering Chemicals - Systems and method for delivering materials to a tool are disclosed. A material delivery system utilizes two or more sources of the material to be delivered to the tool. One or more of the sources of the tool may be a batch mixer. The material delivery system also includes at least two material delivery recirculation lines providing material to at tool. The material delivery system may be manually or automatically controlled to switch supply of the material from one source to another, and/or to switch from one material delivery recirculation line to another. | 05-10-2012 |
Shu-Tine Yang, Jhubei City TW
Patent application number | Description | Published |
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20090267176 | A METHOD FOR FORMING A MULTI-LAYER SHALLOW TRENCH ISOLATION STRUCTURE IN A SEMICONDUCTOR DEVICE - The disclosure describes a multi-layer shallow trench isolation structure in a semiconductor device. The shallow trench isolation structure may include a first void-free, doped oxide layer in the shallow trench, and a second void-free layer above the first doped oxide layer. The first layer may be formed by vapor deposition of precursors of a source of silicon, a source of oxygen and sources of doping materials and making the layer void-free by reflowing the initial layer by an annealing process. The second layer may be formed by vapor deposition of precursors of silicon and doping materials and making the layer void-free by reflowing the initial layer by an annealing process. Alternatively, the second layer may be a silicon oxide layer that may be formed by an atomic layer deposition method. The processing conditions for forming the two layers are different. | 10-29-2009 |
20120091538 | FINFET AND METHOD OF FABRICATING THE SAME - The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces; a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin comprises a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin comprises a non-recessed portion having a top surface higher than the tapered top surfaces; and a gate stack over the non-recessed portion of the fin. | 04-19-2012 |
20130228865 | FIN FIELD EFFECT TRANSISTOR - A FinFET is described, the FinFET includes a substrate including a top surface and a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces. The FinFET further includes a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin includes a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin includes a non-recessed portion having a top surface higher than the tapered top surfaces. The FinFET further includes a gate stack over the non-recessed portion of the fin. | 09-05-2013 |
20140327091 | FIN FIELD EFFECT TRANSISTOR - A fin field effect transistor including a first insulation region and a second insulation region over a top surface of a substrate. The first insulation region includes tapered top surfaces, and the second insulation region includes tapered top surfaces. The fin field effect transistor further includes a fin extending above the top surface between the first insulation region and the second insulation region. The fin includes a first portion having a top surface below the tapered top surfaces of the first insulation region. The fin includes a second portion having a top surface above the tapered top surfaces of the first insulation region. | 11-06-2014 |