Patent application number | Description | Published |
20110001112 | NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile memory device according to an embodiment of the present invention includes a first wire that extends in a first direction, a second wire that is formed at a height different from the first wire and extends in a second direction, and a nonvolatile memory cell that is arranged to be sandwiched between the first wire and the second wire at a position at which the first wire and the second wire intersect with each other. The nonvolatile memory cell includes a structure in which a nonvolatile storage element is sandwiched by semiconductor layers having different polarities. | 01-06-2011 |
20110049611 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - In a memory cell portion, a stacked structure, in which dielectric layers and semiconductor layers are alternately stacked, is arranged in a fin shape on a semiconductor substrate, and in a peripheral circuit portion, a gate electrode is arranged on the semiconductor substrate via a gate dielectric film so that a height of an upper surface of the gate electrode is set to be substantially equal to a height of an upper surface of the stacked structure in which the dielectric layers and the semiconductor layers are alternately stacked. | 03-03-2011 |
20110156132 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes memory strings which have a plurality of transistors including gate electrode films formed over sides of columnar semiconductor films on gate dielectric films in a height direction of the semiconductor films, and which are arranged in a matrix shape substantially perpendicularly above a substrate. The gate electrode films of the transistors at same height of the memory strings arranged in a first direction are connected to one another. A distance between the semiconductor films at least in a forming position of the transistor at an uppermost layer of the memory strings adjacent to each other in the first direction is smaller than double of thickness of the gate dielectric films. | 06-30-2011 |
20110309429 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, in a floating-gate type nonvolatile semiconductor memory device in which a tunnel dielectric film and a control gate electrode are connected between memory cells adjacent via a shallow trench isolation, each of a floating gate electrode and the control gate electrode includes an electric-field concentrated portion having a curvature on the tunnel dielectric film side. The electric-field concentrated portion of the floating gate electrode is formed over a forming position of a channel semiconductor. The electric-field concentrated portion of the control gate electrode is formed over a forming position of the shallow trench isolation. | 12-22-2011 |
20120032247 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor obtained by sequentially stacking the gate insulation film, the floating gate electrode, the interelectrode insulation film, and the control gate electrode over the channel semiconductor layer. The control gate electrode has a structure obtained by sequentially stacking the semiconductor film, the silicide phase-change suppressing layer, and the silicide film. In addition, the silicide phase-change suppressing layer includes a polycrystalline silicon film in which at least one of C, F, and N is doped in a concentration range of 1×10 | 02-09-2012 |
20120068144 | RESISTANCE RANDOM ACCESS MEMORY - According to one embodiment, there are provided a first electrode, a second electrode, first and second variable-resistance layers that are arranged between the first electrode and the second electrode, and at least one non variable-resistance layer that is arranged so that positions of the first and second variable-resistance layers between the first electrode and the second electrode are symmetrical to each other. | 03-22-2012 |
20120267699 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes sheet-like memory strings arranged in a matrix shape substantially perpendicularly to a substrate. A control gate electrode film includes a common connecting section that extends in a first direction and an electrode forming section that is provided for each of memory cells above or below a floating gate electrode film via an inter-electrode dielectric film to project from the common connecting section in a second direction. The floating gate electrode film extends in the second direction and is formed on a first principal plane of a sheet-like semiconductor film via a tunnel dielectric film. | 10-25-2012 |
20120280303 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a first trench extending in a first direction is formed in a stacked structure in which a plurality of spacer films and a plurality of channel semiconductor films are alternately stacked. A first space is formed by forming a recess in the channel semiconductor films from the first trench. A tunnel dielectric film is formed in the first space, and the first space is further filled with a floating gate electrode film. Second trenches that divide the stacked structure at predetermined interval in the first direction are formed so as to divide the floating gate electrode film between memory cells adjacent to each other in the first direction but not to divide the channel semiconductor films. | 11-08-2012 |
Patent application number | Description | Published |
20090267123 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a plurality of transistors on the semiconductor substrate, each of the transistors has a source and drain region; an interlayer insulating film on the semiconductor substrate and the plurality of transistors; and at least three capacitors on the interlayer insulation film, each of them has a top electrode, a bottom electrode and an insulating film interposed therebetween; wherein the 1st and 2nd capacitors have an shared electrode, with the top electrodes of the 1st and 2nd capacitors, which has a 1st longer direction, the 2nd and 3rd capacitors have an shared electrode, with the bottom electrodes of the 2nd and 3rd capacitors, which has a 2nd longer direction different from the 1st direction. | 10-29-2009 |
20090283737 | NONVOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile storage device having a plurality of unit memory layers, and a plurality of layer selection transistors is provided. The plurality of unit memory layers are laminated in a direction perpendicular to a layer surface of the unit memory layers. Each of the unit memory layers includes a plurality of first wirings, a plurality of second wirings provided non-parallel to the plurality of first wirings, and a recording layer provided between the plurality of first wirings and the plurality of second wirings. The plurality of layer selection transistors are connected to at least one of the plurality of first wirings and the plurality of second wirings of each of the unit memory layers, and collectively selects the at least one in the same plane. | 11-19-2009 |
20090283739 | NONVOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - There is provided a nonvolatile storage device including a plurality of component memory layers. The plurality of component memory layers are stacked In a direction perpendicular to a layer surface. Each of the plurality of component memory layers includes a first wiring, a second wiring provided non-parallel to the first wiring and a stacked structure unit provided between the first wiring and the second wiring and including a recording layer. At least one of the first wiring and the second wiring includes a protruding portion provided on a portion opposed to the recording layer and protruding toward the recording layer side. | 11-19-2009 |
20090289251 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile memory device includes a plurality of component memory layers stacked on one another. Each of the plurality of component memory layers includes a first wiring, a second wiring provided non-parallel to the first wiring, and a stacked structure unit provided between the first wiring and the second wiring. The stacked structure unit has a memory layer and a rectifying element. The rectifying element has a Schottky junction formed on an interface between an electrode and an oxide semiconductor. The electrode includes a metal and the oxide semiconductor includes a metal. | 11-26-2009 |
20090294751 | NONVOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a nonvolatile storage device with a plurality of unit memory layers stacked therein is provided. Each of the unit memory layers includes: a first interconnect extending in a first direction; a second interconnect extending in a second direction; a recording unit sandwiched between the first and second interconnects and being capable of reversibly transitioning between a first state and a second state in response to a current supplied through the first and second interconnects; and a rectifying element sandwiched between the first interconnect and the recording unit and including at least one of p-type and n-type impurities. In the method, the first interconnect, the second interconnect, the recording unit, and a layer of an amorphous material including the at least one of p-type and n-type impurities used in the plurality of unit memory layers are formed at a temperature lower than a temperature at which the amorphous material is substantially crystallized. The amorphous material used in the plurality of unit memory layers is simultaneously crystallized and the impurities included in the amorphous material used in the plurality of unit memory layers are simultaneously activated. | 12-03-2009 |
20090294836 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor storage device includes: a plurality of stacked units juxtaposed on a major surface of a substrate, each stacked unit aligning in a first direction parallel to the major surface of the substrate; and a gate electrode aligning parallel to the major surface in a second direction non-parallel to the first direction. Each of the plurality of stacked units includes a plurality of stacked semiconductor layers via an insulating layer. The plurality of stacked units are juxtaposed so that the spacings between adjacent stacked units are alternately a first spacing and a second spacing larger than the first spacing. The second spacing is provided at a periodic interval four times a size of a half pitch F of the bit line. The gate electrode includes a protruding portion that enters into a gap of the second spacing between the stacked units. A first insulating film, a charge storage layer, and a second insulating film are provided between a side face of the semiconductor layer and the protruding portion. | 12-03-2009 |
20110027981 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor storage device includes: a plurality of stacked units juxtaposed on a major surface of a substrate, each stacked unit aligning in a first direction parallel to the major surface of the substrate; and a gate electrode aligning parallel to the major surface in a second direction non-parallel to the first direction. Each of the plurality of stacked units includes a plurality of stacked semiconductor layers via an insulating layer. The plurality of stacked units are juxtaposed so that the spacings between adjacent stacked units are alternately a first spacing and a second spacing larger than the first spacing. The second spacing is provided at a periodic interval four times a size of a half pitch F of the bit line. The gate electrode includes a protruding portion that enters into a gap of the second spacing between the stacked units. A first insulating film, a charge storage layer, and a second insulating film are provided between a side face of the semiconductor layer and the protruding portion. | 02-03-2011 |
20110284946 | SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING SAME - A semiconductor memory capable of increasing bit density by three-dimensional arrangement of cells and a method for manufacturing the same are provided. | 11-24-2011 |
20120184078 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method for manufacturing a semiconductor memory device, includes forming a stacked body on a substrate by alternately stacking a first insulating film and a second insulating film, making a through-hole extending in a stacking direction of the first insulating film and the second insulating film to pierce the stacked body, forming at least a portion of a blocking insulating film, a charge trap film, and a tunneling dielectric film of a MONOS on an inner surface of the through-hole, forming a channel semiconductor on the tunneling dielectric film, making a trench in the stacked body, removing the second insulating film by performing etching via the trench, and filling a conductive material into a space made by the removing of the second insulating film. | 07-19-2012 |
20130032873 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, and a plurality of memory cells. The stacked body includes a plurality of stacked gate electrodes and inter-electrode insulating layers provided between the gate electrodes. The semiconductor pillar punches through the stacked body. The plurality of memory cells is provided in stacking direction. The memory cell includes a charge trap layer provided between the semiconductor pillar and the gate electrode via an air gap. The block insulating layer is provided between the charge trap layer and the gate electrode. Each of the plurality of memory cells is provided with a support portion configured to keep air gap distance between the charge trap layer and the semiconductor pillar. | 02-07-2013 |
Patent application number | Description | Published |
20090001442 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material. | 01-01-2009 |
20090011570 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer. | 01-08-2009 |
20090206409 | Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device, includes forming a first insulating film containing silicon oxide as a main ingredient, on an underlying region, adhering water to the first insulating film, forming a polymer solution layer containing a silicon-containing polymer on the water-adhered first insulating film, and forming a second insulating film containing silicon oxide as a main ingredient from the polymer solution layer, wherein forming the second insulating film includes forming silicon oxide by a reaction between the polymer and water adhered to the first insulating film. | 08-20-2009 |
20100055869 | Semiconductor device and method of manufacturing same - A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith. | 03-04-2010 |
20100159710 | Semiconductor manufacturing apparatus, liquid container, and semiconductor device manufacturing method - A semiconductor manufacturing apparatus comprises a discharge portion discharging a coating liquid onto a substrate; a gas supply tube supplying an inert gas into a liquid container that contains the coating liquid, and pressurizing an interior of the liquid container; a coating liquid supply tube airtightly supplying the coating liquid from the liquid container to the discharge portion using pressurization from the gas supply tube; a first connecting portion capable of attaching and detaching the liquid container to and from the coating liquid supply tube; a second connecting portion capable of attaching and detaching the liquid container to and from the gas supply tube; and a solvent supply tube supplying a solvent, which can dissolve the coating liquid, to the first connecting portion. | 06-24-2010 |
20100171164 | Nonvolatile semiconductor memory device and method of manufacturing the same - A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material. | 07-08-2010 |
20110272745 | SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode. | 11-10-2011 |
20140264227 | SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode. | 09-18-2014 |
Patent application number | Description | Published |
20090072323 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - In a nonvolatile semiconductor memory device which has a nonvolatile memory cell portion, a low-voltage operating circuit portion of a peripheral circuit region and a high-voltage operating circuit portion of the peripheral circuit region formed on a substrate and in which elements of the above portions are isolated from one another by filling insulating films, the upper surface of the filling insulating films in the high-voltage operating circuit portion lies above the surface of the substrate and the upper surface of at least part of the filling insulating films in the low-voltage operating circuit portion is pulled back to a portion lower than the surface of the substrate. | 03-19-2009 |
20090124061 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, comprises forming an isolation trench on a semiconductor substrate, exposing a silicon surface of the isolation trench formed on the semiconductor substrate, filling a first insulating film into the semiconductor substrate by means of TEOS/O | 05-14-2009 |
20090194810 | SEMICONDUCTOR DEVICE USING ELEMENT ISOLATION REGION OF TRENCH ISOLATION STRUCTURE AND MANUFACTURING METHOD THEREOF - A stacked film including a gate dielectric film and electrode film of each memory cell of a flash memory is formed on a semiconductor substrate. The stacked film is patterned by reactive ion etching to form an isolation trench for formation of an element isolation region and the surface of the semiconductor substrate is exposed to the internal portion of the isolation trench. An O | 08-06-2009 |
20090212352 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity. | 08-27-2009 |
20110147822 | Semiconductor memory device and method for manufacturing the same - A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity. | 06-23-2011 |
20120139030 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer. | 06-07-2012 |
20130134372 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers. | 05-30-2013 |
20130175490 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure. | 07-11-2013 |
20130181184 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures. | 07-18-2013 |
20130200450 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a fin structure stacked in order of a first oxide layer, a semiconductor layer and a second oxide layer in a first direction perpendicular to a surface of the semiconductor substrate, the fin structure extending in a second direction parallel to the surface of the semiconductor substrate, and a gate structure stacked in order of a gate oxide layer, a charge storage layer, a block insulating layer and a control gate electrode in a third direction perpendicular to the first and second directions from a surface of the semiconductor layer in the third direction. | 08-08-2013 |
20130307047 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a device includes a first fin structure having first to n-th semiconductor layers (n is a natural number equal to or more than 2) stacked in a first direction perpendicular to a surface of a semiconductor substrate, and extending in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory cells provided on surfaces of the first to n-th semiconductor layers in a third direction perpendicular to the first and second directions respectively, and first to n-th select transistors connected in series to the first to n-th memory cells respectively. | 11-21-2013 |
20140213064 | SEMICONDUCTOR MANUFACTURING APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor manufacturing apparatus according to the present embodiment comprises a chamber. A chemical-agent supply part is configured to supply a water-repellent agent or an organic solvent to a surface of a semiconductor substrate having been cleaned with a cleaning liquid in the chamber. A spray part is configured to spray a water-capture agent capturing water into an atmosphere in the chamber. | 07-31-2014 |
20140363963 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a method includes forming workpiece, first and second films on a substrate, processing the second films to form first and second core patterns, forming third and fourth sidewall patterns on side surfaces of the first and second core patterns via first and second sidewall patterns, and removing the first core patterns and first sidewall patterns so that the second core pattern and second to fourth sidewall patterns remain. The method includes processing the first films by transferring the second core pattern and second to fourth sidewall patterns to form third and fourth core patterns, forming fifth and sixth sidewall patterns on side surfaces of the third and fourth core patterns, removing the third core patterns so that the fourth core pattern and fifth and sixth sidewall patterns remain, and processing the workpiece film by transferring the fourth core pattern and fifth and sixth sidewall patterns. | 12-11-2014 |