Patent application number | Description | Published |
20100052645 | REFERENCE CURRENT GENERATOR CIRCUIT FOR LOW-VOLTAGE APPLICATIONS - A reference current generator circuit suitable for low-voltage applications is provided. The generator circuit is fabricated in a chip for generating a precise reference current based on a precise reference voltage and a precise external resistor. The generator circuit provides an equivalent resistance coupled in parallel with the external resistor to provide resistance compensation and reduce the impedance of seeing into the chip from a chip pad. In addition to the resistance compensation, only moderate capacitance compensation is required to enhance the phase margin of the generator circuit, so as to achieve a stable loop. Therefore, chip area and cost can be reduced in low-voltage applications. In addition, the generator circuit reproduces the reference current generated by the external resistor by utilizing current mirrors, so as to eliminate the effect on currents caused by parallel coupling of the equivalent resistance and the external resistor. | 03-04-2010 |
20100054892 | STRUCTURE OF RIVET FIXING DEVICE - A rivet fixing device includes a catch tab retainer tube engageable with a transmission spindle of an electrically-operated, pneumatic or battery-powered electric drill or screwdriver, an inner guide sleeve, a driver, pawls, a rivet breaker, and an outer guide sleeve. By being driven by the transmission structure of the electric screwdriver, a rivet, with a shank section thereof inserted into a front end of the rivet breaker and the rivet being fit through holes defined in steel plates, iron plates, copper plates, or aluminum plates, due to the catch tab retainer tube being depressed inward to engage the transmission spindle, is driven by the rearward movement of the catch tab retainer tube to have a fit end thereof that extends beyond the holes of the plates squeezed and deformed to form an expanded portion, serving as a positioning wall that stretches and secures the rivet between the two metal plates. | 03-04-2010 |
20100230844 | Process for Producing Environmental Protection Wall Plate - A process for producing environmental protection wall plate, includes formulating raw materials including vegetable fiber powder, magnesium oxide powder, talc powder and rigid sour calcium powder in a proper ratio; stirring said raw materials with a stirrer; after stirring for a period of time, adding a solidification agent in said mixture with stirring to form a mix; pouring said mix in a plate mould; vibrating said plate mould with a vibrator to make the mix more compact; and finally, pressing the wall plate with the vibrator, and placing the wall plate for a period of time to gel and cure the wall plate; an environmental protection wall plate can be thus obtained through the above-described steps. | 09-16-2010 |
20140043082 | CLOCK GENERATION METHOD AND SYSTEM - The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock. | 02-13-2014 |
Patent application number | Description | Published |
20130284230 | SOLAR CELL MODULE, ELECTRONIC DEVICE HAVING THE SAME, AND MANUFACTURING METHOD FOR SOLAR CELL - A solar cell module is provided and includes a first solar cell and a second solar cell. The first solar cell includes a first metal substrate, a first photoelectric conversion layer, a first top electrode layer, a first P-N junction semiconductor, and a first bottom electrode layer. The second solar cell includes a second metal substrate, a second photoelectric conversion layer, a second top electrode layer, a second P-N junction semiconductor, and a second bottom electrode layer. The first photoelectric conversion layer and the first P-N junction semiconductor are respectively located on two opposite sides of the first metal substrate. The second photoelectric conversion layer and the second P-N junction semiconductor are respectively located on two opposite sides of the second metal substrate. The second bottom electrode layer is located on the second P-N junction semiconductor, and is electrically coupled to the first metal substrate. | 10-31-2013 |
20130285636 | POWER TRACKING DEVICE AND POWER TRACKING METHOD - A power tracking device and a power tracking method is disclosed herein. The power tracking device includes a power voltage setting circuit, a switch, a switching signal circuit, and a voltage memory circuit. The switching signal circuit is configured for sending a first control signal to the switch. When the switch receives the first control signal and electrically isolates the power source and the power voltage setting circuit, the voltage memory circuit stores an open circuit voltage of the power source and sends a setting voltage relative to the open circuit voltage, and when the switch receives the first control signal and electrically connects the power source and the power voltage setting circuit, the power voltage setting circuit sets an output voltage of the power source to correspond with the setting voltage. | 10-31-2013 |
20150053331 | THIN FILM TRANSISTOR - A method for manufacturing a patterned layer includes the steps of: providing a substrate having a first surface and a second surface opposite to the first surface; providing a material source for supplying a plurality of charged particles, in which the first surface faces the material source; providing a magnetic element, in which the second surface is arranged between the magnetic element and the first surface; and depositing the charged particles on the first surface through using the magnetic element so as to form a patterned layer. A method for manufacturing an electrochromic device is disclosed as well. | 02-26-2015 |
Patent application number | Description | Published |
20120326312 | In-Situ Formation of Silicon and Tantalum Containing Barrier - A method includes forming an opening in a dielectric layer, and forming a silicon rich layer on a surface of the dielectric layer. A portion of the silicon rich layer extends into the opening and contacts the dielectric layer. A tantalum-containing layer is formed over and the contacting the silicon rich layer. An annealing is performed to react the tantalum-containing layer with the silicon rich layer, so that a tantalum-and-silicon containing layer is formed. | 12-27-2012 |
20130154060 | WAFER AND METHOD OF PROCESSING WAFER - A wafer including a substrate, a dielectric layer over the substrate, and a conductive layer over the dielectric layer is disclosed. The substrate has a main portion. A periphery of the dielectric layer and the periphery of the main portion of the substrate are separated by a first distance. A periphery of the conductive layer and the periphery of the main portion of the substrate are separated by a second distance. The second distance ranges from about a value that is 0.5% of a diameter of the substrate less than the first distance to about a value that is 0.5% of the diameter greater than the first distance. | 06-20-2013 |
20130207098 | SOFT MATERIAL WAFER BONDING AND METHOD OF BONDING - A semiconductor device including a first wafer assembly having a first substrate and a first oxide layer over the first substrate. The semiconductor device further includes a second wafer assembly having a second substrate and a second oxide layer over the second substrate. The first oxide layer and the second oxide layer are bonded together by van der Waals bonds or covalent bonds. A method of bonding a first wafer assembly and a second wafer assembly including forming a first oxide layer over a first substrate. The method further includes forming a second oxide layer over a second wafer assembly. The method further includes forming van der Waals bonds or covalent bonds between the first oxide layer and the second oxide layer. | 08-15-2013 |
20130241018 | Grids in Backside Illumination Image Sensor Chips and Methods for Forming the Same - A device includes a semiconductor substrate having a front side and a backside, a photo-sensitive device disposed on the front side of the semiconductor substrate, and a first and a second grid line parallel to each other. The first and the second grid lines are on the backside of, and overlying, the semiconductor substrate. The device further includes an adhesion layer, a metal oxide layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal oxide layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines. | 09-19-2013 |
20140273291 | Wafer Strength by Control of Uniformity of Edge Bulk Micro Defects - A method is provided for qualifying a semiconductor wafer for subsequent processing, such as thermal processing. A plurality of locations are defined about a periphery of the semiconductor wafer, and one or more properties, such as oxygen concentration and a density of bulk micro defects present, are measured at each of the plurality of locations. A statistical profile associated with the periphery of the semiconductor wafer is determined based on the one or more properties measured at the plurality of locations. The semiconductor wafer is subsequently thermally treated when the statistical profile falls within a predetermined range. The semiconductor wafer is rejected from subsequent processing when the statistical profile deviates from the predetermined range. As such, wafers prone to distortion, warpage, and breakage are rejected from subsequent thermal processing. | 09-18-2014 |
20140319626 | Metal Gate Stack Having TiAlCN as Work Function Layer and/or Blocking/Wetting Layer - A metal gate stack having a titanium aluminum carbon nitride (TiAlCN) as a work function layer and/or a multi-function blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate, a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer includes TiAlCN, a work function layer disposed over the multi-function blocking/wetting layer, and a conductive layer disposed over the work function layer. | 10-30-2014 |
20150054029 | Metal Gate Stack Having TaAlCN Layer - An integrated circuit device includes a semiconductor substrate; and a gate stack disposed over the semiconductor substrate. The gate stack further includes a gate dielectric layer disposed over the semiconductor substrate; a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer comprises tantalum aluminum carbon nitride (TaAlCN); a work function layer disposed over the multi-function blocking/wetting layer; and a conductive layer disposed over the work function layer. | 02-26-2015 |