Patent application number | Description | Published |
20090055591 | Hierarchical cache memory system - A hierarchical cache memory system having first and second cache memories includes: a controller which outputs dirty data stored in the first cache memory to write back to a main memory; and a controller which processes the write-back to the main memory of the dirty data outputted from the first cache memory in parallel with the write-back to the main memory of dirty data stored in the second cache memory. | 02-26-2009 |
20100011170 | CACHE MEMORY DEVICE - A cache memory device includes an address generation unit, a data memory, a tag memory, and a hit judging unit. The address generation unit generates a prefetch index address included in a prefetch address based on an input address supplied from a higher-level device. The tag memory stores a plurality of tag addresses corresponding to a plurality of line data stored in the data memory. Further, the tag memory comprises a memory component that is configured to receive the prefetch index address and an input index address included in the input address in parallel and to output a first tag address in accordance with the input index address and a second tag address in accordance with the prefetch index address in parallel. The hit judging unit performs cache hit judgment of the input address and the prefetch address based on the first tag address and the second tag address. | 01-14-2010 |
20100057952 | MEMORY CONTROLLER AND MEMORY CONTROL METHOD - A memory controller has a control unit receiving a transfer data from a transmission circuit and executing a burst transfer of the transfer data to a reception circuit. The transmission circuit transmits a first data of a first bit length for a first burst times by a burst transmission. The amount of the transfer data is equal to a product of the first bit length and the first burst times. The reception circuit receives a second data of a second bit length for a second burst times by a burst reception. When the amount of the first data received by the control unit becomes equal to or more than a product of the second bit length and the second burst times, the control unit transfers the received first data as the second data to the reception circuit, regardless of the number of the first data received by the control unit. | 03-04-2010 |
20110022823 | INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD THEREOF - An information processing system includes an execution unit and a decoder. The execution unit includes a plurality of arithmetic units each having a first operation circuit that performs a first operation on a first input value and a second input value, a second operation circuit that performs a second operation on the first input value and the second input value, and a selector that selects and outputs either a first output value output from the first operation circuit or a second output value output from the second operation circuit based on a selection signal. The decoder decodes an operation instruction and determines each value of the selection signal of each arithmetic unit. The decoder determines the value of the selection signal corresponding to the operation instruction with respect to each program. | 01-27-2011 |
Patent application number | Description | Published |
20100279184 | SOLID ELECTROLYTE FUEL CELL SYSTEM - A solid electrolyte fuel cell system includes a reformer to produce a hydrogen-rich reformed gas from fuel, oxygen and water, and a stack structure including a stack of fuel cell units each receiving supply of the reformed gas and air, and producing electricity. The fuel cell system further includes a reformed gas cooler to cool the reformed gas supplied from the reformer to the stack structure, and a temperature control section to control operation of the reformed gas cooler in accordance with an operating condition such as a request output of the stack structure. The reformed gas cooler includes a device such as a heat exchanger for cooling the reformed gas with a coolant such as air. | 11-04-2010 |
20110045366 | FUEL CELL SYSTEM - Disclosed is a fuel cell system comprising a reformer and a fuel cell body to which a fuel gas reformed through the reformer and air are supplied and in which the supplied fuel gas and air are separated from each other and caused to flow and contact on respective electrodes to perform electric power generation. A moisture quantity adjustment device is configured to adjustably separate a portion of moisture included in the fuel gas supplied from the reformer in order for the moisture included in the fuel gas to be supplied to the fuel cell body in an appropriate quantity. | 02-24-2011 |
20120040265 | FUEL CELL SYSTEM AND METHOD FOR CONTROLLING SAME - Disclosed is a fuel cell system which comprises a power generation means that includes a plurality of fuel cells that are connectable to one another in series or in parallel through connecting terminals, a fuel gas supply conduit through which fuel electrodes of all or part of the fuel cells are connected in series and an oxidant gas supply conduit through which air electrodes of all or part of the fuel cells are connected in series; a switching means that switches an electric connection condition between the connecting terminals and connecting means of an external load device; a fuel gas supply means that supplies the fuel gas supply conduit with a fuel gas and an oxidant gas supply means that supplies the oxidant gas supply conduit with an oxidant gas; a load detecting means that detects a load of the external load device; and a control means that selects, based on an already derived relation between overall electric power output curves corresponding to the number of the fuel cells that are mutually connected and an operation temperature zone, one of the power output curves in accordance with an input from the load detecting means and selects the number of mutually connected fuel cells that brings about the highest voltage of the fuel cells thereby to control the switching means, the fuel gas supply means and the oxidant gas supply means. | 02-16-2012 |
Patent application number | Description | Published |
20130201760 | Reducing Weak-Erase Type Read Disturb In 3D Non-Volatile Memory - A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made non-conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling. | 08-08-2013 |
20140056065 | Reducing Weak-Erase Type Read Disturb In 3D Non-Volatile Memory - A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vb1), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates non-conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vb1. Two-step boosting drives the channel at Vb1, then provides boosting by capacitive coupling. | 02-27-2014 |
20140247659 | REDUCING WEAK-ERASE TYPE READ DISTURB IN 3D NON-VOLATILE MEMORY - A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates non-conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling. | 09-04-2014 |
20150103592 | PROGRAMMING TIME IMPROVEMENT FOR NON-VOLATILE MEMORY - Disclosed herein are techniques for providing a programming voltage to a selected word line in a non-volatile memory array. This may be a 3D NAND, 2D NAND, or another type of memory array. The programming voltage may be quickly ramped up on the selected word line, without the need for adding a stronger charge pump to the memory device. The voltage on the selected word line may be ramped up to a target voltage during a channel pre-charge phase. The target voltage may be limited in magnitude so that program disturb does not occur. Next, during a channel boosting phase, the unselected word lines are increased to a boosting voltage. The voltage on the selected word line is also increased during the boosting phase to a second target level. Then, the voltage on the selected word line is charged up from the second target level to a program voltage. | 04-16-2015 |
Patent application number | Description | Published |
20110064847 | METHOD OF DENATURING PROTEIN WITH ENZYMES - A method of denaturing a protein by treating the protein with a protein glutaminase and a transglutaminase, a food containing a protein having been denatured with these enzymes, and an enzyme preparation for denaturing a protein which contains these enzymes. A protein is denatured by adding protein glutaminase and transglutaminase to the protein substantially at the same timing, or adding protein glutaminase to the protein before the transglutaminase acts on the protein, or controlling the quantitative ratio of protein glutaminase to transglutaminase, by which a protein is treated, to a definite level. | 03-17-2011 |
20110151055 | PROCESSED FOOD AND METHOD OF PRODUCING THE SAME - The present invention provides a processed food obtained by using a starch-containing raw material such as wheat flour as a starting material, which has an excellent color, gloss and texture and shows regulated degradation with the lapse of time after cooking, and a method of producing the same. In producing a processed food by using a starch-containing raw material as a starting material, a deamidated milk raw material obtained by treating a milk material with a protein deamidase is employed as a starting material. | 06-23-2011 |
20110236529 | METHOD FOR PRODUCING MODIFIED MILK - Provided is a method whereby a dairy product having a rich and creamy texture can be obtained by reducing or removing a reaction inhibitor of a protein deamidating enzyme contained in a raw material milk having low heat history to thereby more efficiently and more effectively treat the raw material milk having low heat history with a protein deamidating enzyme. A raw material milk having low heat history is treated with a protein deamidating enzyme after or simultaneously with a treatment, such as an addition of a calcium chelating agent, for reducing a protein deamidating enzyme inhibitor. | 09-29-2011 |
20120207878 | LOW-FAT OR FAT-FREE YOGHURT, AND PROCESS FOR PRODUCTION THEREOF - A fat-free or low-fat yoghurt having a rich and creamy texture like yoghurts produced using whole-fat milk may be produced by adding a proper amount of a milk protein, such as a defatted milk powder, that has been deamidated with a protein deamidating enzyme to a fat-free or low-fat raw material milk. Alternatively, a proper amount of a milk protein, such as a defatted milk powder, is added to a fat-free or low-fat raw material milk, and the resulting mixture is subjected to a deamidation treatment with a protein deamidating enzyme so that the deamidation ratio reaches a proper level. In this manner, a fat-free or low-fat milk raw material having a milk protein mass and a deamidation ratio both falling within proper ranges can be prepared, and yoghurt may be produced using the milk raw material. | 08-16-2012 |
20130022710 | ICE CREAM OR ICE CREAM-LIKE PRODUCT AND METHOD FOR PRODUCING SAME - Provided is an ice cream or ice cream-like product, to which a good body, flavor and a smooth texture have been imparted, and a method for producing the same. In a process of producing an ice cream or ice cream-like product, a step, wherein a protein deamidating enzyme is added to a milk material or a liquid ice cream mix for treating the same to thereby deamidate milk proteins in the milk material, is employed. | 01-24-2013 |
20130236627 | COFFEE WHITENER, PROCESS FOR PRODUCING SAME, AND PROCESS FOR PRODUCING BEVERAGE - Coffee whiteners prepared by using, as the aqueous phase thereof, a casein-containing milk protein solution that has been deamidated with a protein deamidating enzyme, exhibit excellent storage stability and dispersibility in coffee without the use of synthetic emulsifiers. | 09-12-2013 |