Patent application number | Description | Published |
20110245458 | PEPTIDE NUCLEIC ACID MONOMERS AND OLIGOMERS - Disclosed is a peptide nucleic acid monomer as well as a corresponding peptide nucleic acid molecule. The monomer comprises a terminal amino group and a terminal group A. The terminal amino group and the terminal group A are connected by an aliphatic moiety. The main chain of this aliphatic moiety is free of groups that are charged under physiological conditions. The terminal group A is one of —COOH, —COOR | 10-06-2011 |
20130131286 | COMPOUND FOR USE IN PEPTIDE SYNTHESIS - The present invention generally relates to processes and methods of peptide and protein synthesis. The present invention also relates to specific compounds for use in such processes and methods. It is shown herein that peptides with a C-terminal tertiary N,N-bis(2-mercaptoethyl)-amide (BMEA) undergo N-to-S acyl transfer at weakly acidic pH to form a transient thioester which can be captured for direct ligation with a cysteinyl peptide. These C-terminal BMEA peptides are easily prepared with standard Fmoc solid-phase synthesis protocols, thus giving a very convenient access to the thioester components for native chemical ligation. | 05-23-2013 |
20140316105 | METHOD FOR MODIFICATION OF ORGANIC MOLECULES - The present invention is directed to a method of alkylating a thiol group (R—S—H) or seleno group (R—Se—H) in a target molecule wherein the method comprises: reacting a target molecule comprising at least one thiol group with a compound of formula (I) or (II): wherein R is an acetyl group or any other acyl group or is a group comprising any one of: or wherein R in formula (II) can also be an alkyl group; and wherein R′ is selected from a group consisting of a hydrogen, a methyl group and an ethyl group. | 10-23-2014 |
20150024431 | THROMBOPOIETIC COMPOUNDS - The invention relates to the field of compounds, especially peptides or polypeptides, that have thrombopoietic activity. The peptides and polypeptides of the invention may be used to increase platelets or platelet precursors (e.g., megakaryocytes) in a mammal. | 01-22-2015 |
Patent application number | Description | Published |
20100261165 | Methods, Compositions and Kits for Use in Prognosis, Characterization and Treatment of Cancer - The present invention provides methods, compositions and kits for the prognosis, characterization and treatment of cancers. The methods, compositions and kits of the invention comprise a set of markers whose expression is correlated with estrogen receptor beta function. Therefore, the methods, compositions and kits of the invention find particular use in endocrine-related cancers such as breast cancers. | 10-14-2010 |
20100285475 | FUSED GENES - There is provided at least one isolated fused gene comprising at least one first gene and/or fragment thereof fused to at least one second gene and/or fragment thereof, wherein at least the first and/or the second gene, independently, is selected from the group consisting of: RCC2, CENPF, ARFGEF2, SULF2, MTAP, ATXN7, BCAS3, RPS6KB1, TMEM49, EAP30, a gene having the nucleotide sequence SEQ ID NO:1, and a gene having the nucleic acid SEQ ID NO:2, or a fragment thereof. There is also provided a diagnostic method and/or a kit for detecting the susceptibility, prognosis, and/or to tumour in a subject. | 11-11-2010 |
20120100144 | Biomarker and Treatment for Cancer - A correlation between expression of JMJD6 polypeptide and breast cancer metastasis exists accordingly the present invention relates a diagnostic, prognostic and therapeutic biomarker to distinguish between early and advanced/metastatic cancer particularly breast cancer, including compounds and methods to treat the same. | 04-26-2012 |
Patent application number | Description | Published |
20110091083 | AUTOMATIC CUP-TO-DISC RATIO MEASUREMENT SYSTEM - A two-dimensional retinal fundus image of the retinal fundus of an eye is processed by optic disc segmentation ( | 04-21-2011 |
20120230564 | OBTAINING DATA FOR AUTOMATIC GLAUCOMA SCREENING, AND SCREENING AND DIAGNOSTIC TECHNIQUES AND SYSTEMS USING THE DATA - A non-stereo fundus image is used to obtain a plurality of glaucoma indicators. Additionally, genome data for the subject is used to obtain genetic marker data relating to one or more genes and/or SNPs associated with glaucoma. The glaucoma indicators indicators and genetic marker data are input into an adaptive model operative to generate an output indicative of a risk of glaucoma in the subject. In combination, the genetic indicators and genome data are more informative about the risk of glaucoma than either of the two in isolation. The adaptive model may be a two-stage model, having a first stage in which individual genetic indicators are combined with respective portions of the genome data by first adaptive model modules to form respective first outputs, and a second stage in which the first outputs are combined by a second adaptive mode. Texture analysis is performed on the fundus images to classify them based on their quality, and only images which are determined to meet a quality criterion are subjected to an analysis to determine if they exhibit glaucoma indicators. Also, the images are put into a standard format. The system may include estimating the position of the optic cup by combining results from multiple optic cup segmentation techniques. The system may include estimating the position of the optic disc by applying edge detection to the funds image, excluding edge points that are unlikely to be optic disc boundary points, and estimating the position of an optic disc by fitting an ellipse to the remaining edge points. | 09-13-2012 |
20130196300 | ROBOT ASSISTED SURGICAL TRAINING - A surgical training system and method. The system comprises means for recording reference data representing a reference manipulation of a computer generated model of an object by a master user; means for physically guiding a trainee user based on the recorded reference data during a training manipulation of the model of the object by the trainee user; and means for recording assessment data representing an assessment manipulation of the model of the object by the trainee user without guidance. | 08-01-2013 |
20130222767 | METHODS AND SYSTEMS FOR DETECTING PERIPAPILLARY ATROPHY - A method is presented for deciding whether an eye exhibits peripapillary atrophy (PPA). It includes a preliminary step of extracting from an image of the eye a region-of-interest which would be affected if the eye exhibits peripapillary atrophy, which is a region which surrounds the optic disc, and then processing the region in a way which mimics the processing of the cortex, to derive a plurality of numerical measures (biologically-inspired features, BIF). A decision step is then performed using the BIF, for example using an adaptive system which has been subject to a supervised learning process. Preferably, the region-of-interest is partitioned into a plurality of sub-regions, and the BIF are derived as a corresponding plurality of numerical measures for each of the sub-regions. The BIF preferably include intensity units which take values indicative of centre-surround intensity difference; and colour units which take values indicative of centre-surround difference in a parameter characterizing colour in the image. Further, the BIF preferably include direction-specific units. | 08-29-2013 |
20130224710 | ROBOTIC DEVICE FOR USE IN IMAGE-GUIDED ROBOT ASSISTED SURGICAL TRAINING - A robotic device for use in image-guided robot assisted surgical training, the robotic device comprising a manual interface structure configured to simulate handling of a surgical tool; a translational mechanism for translational motion of the manual interface structure; a rotational mechanism for rotational motion of the manual interface structure; and a spherical mechanism configured to decouple the orientation of the manual interface structure into spatial coordinates, wherein a linkage between the rotational mechanism, the rotational mechanism and the spherical mechanism, and the manual interface structure are disposed on opposing sides of an intersection of a pitch axis and a yaw axis of the spherical mechanism. | 08-29-2013 |
20130251230 | CORNEAL GRAFT EVALUATION BASED ON OPTICAL COHERENCE TOMOGRAPHY IMAGE - An OCT image of an eye which has been subject to a DSAEK corneal transplant, in which a Descement's membrane in the cornea has been replaced by a graft, is processed to identify the outline of the graft. The process includes the steps of: computationally extracting the boundary of the cornea including the graft; computationally detecting the corners of the graft; computationally extracting points on the boundary between the graft and the original cornea; and computationally fitting the points on the boundary between the graft and the original cornea smoothly into a curve. The outline of the graft is then displayed. A graft profile may be generated, indicating the thickness of the graft at each point along its length. | 09-26-2013 |
20150125052 | DRUSEN LESION IMAGE DETECTION SYSTEM - A method is proposed for automatically analysing a retina image, to identify the presence of drusen which is indicative of age-related macular degeneration. The method proposes dividing a region of interest including the macula centre into patches, obtaining a local descriptor of each of the patches, reducing the dimensionality of the local descriptor by comparing the local descriptor to a tree-like clustering model and obtaining transformed data indicating the identity of the cluster. The transformed data is fed into an adaptive model which generates data indicative of the presence of drusen in the retinal image. Furthermore, the trans formed data can be used to obtain the location of the drusen within the image. | 05-07-2015 |
20150161785 | METHODS AND SYSTEMS FOR CHARACTERIZING ANGLE CLOSURE GLAUCOMA FOR RISK ASSESSMENT OR SCREENING - A method is proposed for analysing an optical coherence tomography (OCT) image of the anterior segment (AS) of a subject's eye. A region of interest is defined which is a region of the image containing the junction of the cornea and iris, and an estimated position the junction within the region of interest is derived. Using this a second region of the image is obtained, which is a part of the image containing the estimated position of the junction. Features of the second region are obtained, and those features are input to an adaptive model to generate data characterizing the junction. | 06-11-2015 |
Patent application number | Description | Published |
20090146181 | INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS - An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer. | 06-11-2009 |
20090194788 | STRAINED CHANNEL TRANSISTOR STRUCTURE AND METHOD - A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate. | 08-06-2009 |
20100109045 | INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS-ENGINEERED LAYERS - An integrated circuit system that includes: providing a substrate including an active device; forming a trench within the substrate adjacent the active device; forming a first layer with a first lattice constant within the trench; and forming a second layer with a second lattice constant over the first layer, the second lattice constant differing from the first lattice constant. | 05-06-2010 |
20100308374 | STRAINED CHANNEL TRANSISTOR STRUCTURE AND METHOD - A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate. | 12-09-2010 |
Patent application number | Description | Published |
20080298041 | ELECTROMAGNETIC RADIATION SHIELD FOR AN OPTICAL SUBASSEMBLY - In one example embodiment, an electromagnetic radiation (EMR) shield includes a central portion, an opening defined in the central portion, a wing attached to and extending outward from the central portion, and a protrusion defined in the wing. The perimeter of the EMR shield is approximately the same size and shape as that of a portion of an associated optical subassembly (OSA). | 12-04-2008 |
20090047027 | Optical Network Unit Transceiver Module Having Direct Connect RF Pin Configuration - Systems and method for using a direct connect RF pin configuration for an ONU transceiver module to connect directly to an external component. The ONU module communicates with an optical network. The ONU module further includes an RF interface and a direct connect RF pin configuration to communicate using RF signals. In one embodiment, the direct connect RF pin configuration includes two ground pins and a data pin which are spaced apart and directly connected to a PCB of the ONU. The opposing ends of the pins are directly connected to a PCB of an external component, such as an ONU host box. The pins are thus spaced apart such that they do not impede each others' function and available for direct connection to the external component. | 02-19-2009 |
20100045345 | AC DIFFERENTIAL CONNECTION ASSEMBLY BETWEEN A TRANS-IMPEDANCE AMPLIFIER AND A POST AMPLIFIER FOR BURST MODE RECEIVING - An AC differential connection assembly between a trans-impedance amplifier and a post amplifier for burst mode receiving comprising means for coupling a differential output of the trans-impedance amplifier to a differential input of the post amplifier, the means for coupling comprises a coupling capacitor assembly; and a switching circuit coupled across the differential input of the post amplifier, the switching circuit having an ‘on’ state with low impedance and an ‘off’ state with high impedance; wherein during burst mode receiving, the switching circuit is in the ‘off’ state and the coupling capacitor assembly having a time constant to maintain a stable DC level such that a payload is received accurately by the differential input of the post amplifier; and during an idle period, the switching circuit is in the ‘on’ state and the coupling capacitor assembly having a time constant to recover a DC level of the differential output of the trans-impedance amplifier. | 02-25-2010 |
20100132999 | ELECTROMAGNETIC SHIELDING CONFIGURATION - An electromagnetic shielding configuration comprising a first electrically conductive wall having a first surface and a second electrically conductive wall having a second surface. The first surface is oppositely disposed from the second surface, wherein interfacing of the first conductive wall and the second conductive wall forms an enclosure wall. The first surface comprises at least one stepped edge forming a plurality of surfaces of unequal lateral displacement, and a corrugated surface on at least one of the plurality of surfaces, the corrugated surface formed by a series of apices extending radially from the first surface. The second surface is substantially a conjugate of the first surface. | 06-03-2010 |
20120183300 | OPTICAL NETWORK UNIT TRANSCEIVER MODULE HAVING DIRECT CONNECT RF PIN CONFIGURATION - Methods for providing a direct connect RF pin configuration for an ONU transceiver module to connect directly to an external component. The ONU module communicates with an optical network. The ONU module further includes an RF interface and a direct connect RF pin configuration to communicate using RF signals. In one embodiment, the direct connect RF pin configuration includes two ground pins and a data pin which are spaced apart and directly connected to a PCB of the ONU. The opposing ends of the pins are directly connected to a PCB of an external component, such as an ONU host box. The pins are thus spaced apart such that they do not impede each others' function and available for direct connection to the external component. | 07-19-2012 |
20120318573 | ELECTROMAGNETIC SHIELDING CONFIGURATION - An electromagnetic shielding configuration comprising a first electrically conductive wall having a first surface and a second electrically conductive wall having a second surface. The first surface is oppositely disposed from the second surface, wherein interfacing of the first conductive wall and the second conductive wall forms an enclosure wall. The first surface comprises at least one stepped edge forming a plurality of surfaces of unequal lateral displacement, and a corrugated surface on at least one of the plurality of surfaces, the corrugated surface formed by a series of apices extending radially from the first surface. The second surface is substantially a conjugate of the first surface. | 12-20-2012 |
Patent application number | Description | Published |
20090258828 | INVESTIGATION OF MUCOSA DRYNESS CONDITIONS - The present invention relates to diagnosis and/or treatment of medical conditions. The present invention relates to new method of diagnosing dry mucosa condition in a subject. The condition may be dry eye. The present invention also provides a method to monitor the efficacy of a treatment of a dry mucosa condition, a method of treating a dry mucosa condition and/or a diagnostic kit for a dry mucosa condition. | 10-15-2009 |
20100048469 | ANTIMICROBIAL PEPTIDES - There is provided at least one isolated antimicrobial peptide, wherein the peptide is a linear analog of hBD3 or a fragment thereof. In particular, there is provided a linear analog of hBD3 wherein the peptide has a reduced cytotoxicity to at least one cell compared to the wild type hBD3. | 02-25-2010 |
20110039760 | MULTIMERIC FORMS OF ANTIMICROBIAL PEPTIDES - The invention relates to multimeric forms of antimicrobial peptides, for example, defensin peptides. The multimeric forms of defensin peptides possesses antimicrobial activity and may be formulated into antimicrobial compositions, pharmaceutical compositions, eyedrop composition, contact lens solution compositions for coating medical devices and the like. The invention also relates to the use of these multimeric forms of peptides, e.g. multimeric forms of defensin peptides for inhibiting and/or reducing the growth of microorganisms in general, including in a host. The invention further relates to a method of preparing multimers of peptides derived from defensins, for example hBD3. | 02-17-2011 |
20140142027 | MULTIMERIC FORMS OF ANTIMICROBIAL PEPTIDES - The invention relates to multimeric forms of antimicrobial peptides, for example, defensin peptides. The multimeric forms of defensin peptides possesses antimicrobial activity and may be formulated into antimicrobial compositions, pharmaceutical compositions, eyedrop composition, contact lens solution compositions for coating medical devices and the like. The invention also relates to the use of these multimeric forms of peptides, e.g. multimeric forms of defensin peptides for inhibiting and/or reducing the growth of microorganisms in general, including in a host. The invention further relates to a method of preparing multimers of peptides derived from defensins, for example hBD3. The method includes a composition or combination comprising the multimeric antimicrobial peptides and at least one active pharmaceutical ingredient. | 05-22-2014 |
20140349918 | DERIVATIVES OF XANTHONE COMPOUNDS - The present invention relates to xanthone analogs. Such compounds may be used in the treatment of bacterial infections. | 11-27-2014 |
Patent application number | Description | Published |
20120241710 | Fabrication of RRAM Cell Using CMOS Compatible Processes - Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode. A method of making a resistance random access memory device is disclosed that includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device. | 09-27-2012 |
20140077148 | RRAM CELL WITH BOTTOM ELECTRODE(S) POSITIONED IN A SEMICONDUCTOR SUBSTRATE - Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode. A method of making a resistance random access memory device is disclosed that includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device. | 03-20-2014 |
Patent application number | Description | Published |
20100075865 | MICROARRAY SYSTEM AND A PROCESS FOR PRODUCING MICROARRAYS - A process for making a micro-array. The process comprises the step of depositing a population of microbeads on a substrate having at least one fiducial. The population being comprised of at least two sub-populations, preferably multiple sub-populations, each comprising a known active agent capable of specific binding with at least one target analyte. The said subpopulations are deposited sequentially and at discrete periods of each other. The process also comprises the step of making images of the substrate after deposition of each subpopulation. The images are then compared using the fiducial as a reference to thereby determine the location of each microbead and to identify the subpopulation, and its known active agent, based on differences between each image. Also disclosed in a system for using the microarray. | 03-25-2010 |
20100112563 | MULTIPLEX ANALYSIS OF NUCLEIC ACIDS - A method for identifying target nucleic acids includes the steps of contacting a sample containing a plurality of target nucleic acids with at least one series of nucleotide primers under conditions that allow binding of said primers to at least one of said target nucleic acids and labeling of said bound primers with a detectable signal, wherein one member within each series has a lower level of specificity than other members of the series; and measuring said detectable signal of each labeled primer to determine the identity of said target nucleic acids. | 05-06-2010 |
20100288689 | MICROFLUIDIC FILTRATION UNIT, DEVICE AND METHODS THEREOF - A microfluidic filtration unit for trapping particles of a predetermined nominal size present in a fluid is provided. The unit comprises a fluid chamber connected to an inlet for introducing the fluid to be filtered and an outlet for discharging filtered fluid, a filtration barrier arranged within the fluid chamber, said filtration barrier comprising a plurality of pillars arranged substantially perpendicular to the path of fluid flow when fluid is introduced into the fluid chamber, said pillars being aligned to form at least one row extending across said path of fluid flow, wherein each of said at least one row of pillars in the filtration barrier comprises at least one fine filtration section comprising a group of pillars that are spaced apart to prevent particles to be filtered from the fluid from moving between adjacent pillars, and at least one coarse filtration section comprising a group of pillars that are spaced apart to permit the movement of particles between adjacent pillars. | 11-18-2010 |
20100300978 | DEVICE, SYSTEM AND METHOD FOR WASHING AND ISOLATING MAGNETIC PARTICLES IN A CONTINOUS FLUID FLOW - A device for washing and isolating magnetic particles from a continuous fluid flow in at least one fluidic channel having an inlet at one end and an outlet at another end, said device comprising at least one magnetic source carrier arranged proximate to the at least one fluidic channel. The at least one magnetic source carrier is moveable between a first position and a second position. The at least one magnetic source carrier comprises at least one first magnetic source, wherein a movement of the at least one magnetic source carrier to the first position places the at least one first magnetic source at a first spatial location along the at least one fluidic channel such that said at least one first magnetic source generates a maxima magnetic field at said first spatial location that attracts the magnetic particles from the continuous fluid flow and assembles said magnetic particles at said first spatial location. A movement of the at least one magnetic source carrier to the second position places the at least one first magnetic source distal from the first spatial location such that said magnetic field at said first spatial location is at a minima and the magnetic particles disperse from said first spatial location. | 12-02-2010 |
20140045721 | Microarray System and a Process for Producing Microarrays - A process for making a micro-array. The process comprises the step of depositing a population of microbeads on a substrate having at least one fiducial. The population being comprised of at least two sub-populations, preferably multiple sub-populations, each comprising a known active agent capable of specific binding with at least one target analyte. The said subpopulations are deposited sequentially and at discrete periods of each other. The process also comprises the step of making images of the substrate after deposition of each subpopulation. The images are then compared using the fiducial as a reference to thereby determine the location of each microbead and to identify the subpopulation, and its known active agent, based on differences between each image. Also disclosed in a system for using the microarray. | 02-13-2014 |
Patent application number | Description | Published |
20080230907 | INTEGRATED CIRCUIT SYSTEM WITH CARBON ENHANCEMENT - An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; forming a via opening through the low-K dielectric layer to the interconnect layer; and forming a carbon implant region around the via opening, a trench opening, or a combination thereof, for protecting the low-K dielectric layer. | 09-25-2008 |
20080258308 | Method of controlled low-k via etch for Cu interconnections - An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer. | 10-23-2008 |
20080265409 | INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM - An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer. | 10-30-2008 |
20100013104 | INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM - An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening. | 01-21-2010 |
20100109155 | RELIABLE INTERCONNECT INTEGRATION - A semiconductor device includes a dielectric layer in which an upper portion is densified. An interconnection is disposed in the dielectric layer. The densified portion reduces undercut during subsequent processing, improving reliability of the interconnection. | 05-06-2010 |
20100314763 | INTEGRATED CIRCUIT SYSTEM EMPLOYING LOW-K DIELECTRICS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process. | 12-16-2010 |
Patent application number | Description | Published |
20090233444 | POLISHING METHOD WITH INERT GAS INJECTION - A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process. | 09-17-2009 |
20090239369 | Method of Forming Electrical Interconnects within Insulating Layers that Form Consecutive Sidewalls - Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect. | 09-24-2009 |
20100052184 | INTERCONNECTS WITH IMPROVED TDDB - A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material. | 03-04-2010 |
20120043659 | INTERCONNECTS WITH IMPROVED TDDB - A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material. | 02-23-2012 |
Patent application number | Description | Published |
20100068517 | ENHANCED SILK PROTEIN MATERIAL HAVING IMPROVED MECHANICAL PERFORMANCE AND METHOD OF FORMING THE SAME - The invention provides an enhanced silk fiber rivaling spider silk in mechanical performance, in combination with a very low-cost method for producing it from the usual silkworms. The method provides for the simple application of an electric field which results in an enhancement of over (?) 40% in the strength, and of 200% in the breaking energy with respect to ordinary silkworm silk. The critical elasticity is enhanced to the level of the dragline spider silk. The provided enhanced silk protein material has the same protein primary structure, fiber diameter and length of the customary silk. The method of formation offers the following advantages in comparison to other methods available in the prior art. Industrial scale production can be readily and cost-effectively achieved, given the wide-range availability of silkworms. The provided method relies largely on the present standard production processes of silkworm silk, and hence a low level of investment is required. Since no additional chemicals are required, the provided method is environmentally friendly. | 03-18-2010 |
20120039813 | INTRINSICALLY COLORED, LUMINESCENT SILK FIBROIN AND A METHOD OF PRODUCING THE SAME - This present invention proposes a method of producing intrinsically colored, luminescent silk fibroin by feeding silkworms with feed comprising the luminescent dyes as well as the appropriate degumming process to remove sericin while retaining the dyes in silk fibroin are also described. Luminescent and functional molecular organic dyes with balanced hydrophobic/hydrophobic properties that can be effectively absorbed into silk glands of the silkworm are also described. | 02-16-2012 |
20150176157 | ENHANCED SILK PROTEIN MATERIAL HAVING IMPROVED MECHANICAL PERFORMANCE AND METHOD OF FORMING THE SAME - The invention provides an enhanced silk fiber rivaling spider silk in mechanical performance, in combination with a very low-cost method for producing it from the usual silkworms. The method provides for the simple application of an electric field which results in an enhancement of over (?) 40% in the strength, and of 200% in the breaking energy with respect to ordinary silkworm silk. The critical elasticity is enhanced to the level of the dragline spider silk. The provided enhanced silk protein material has the same protein primary structure, fiber diameter and length of the customary silk. The method of formation offers the following advantages in comparison to other methods available in the prior art. Industrial scale production can be readily and cost-effectively achieved, given the wide-range availability of silkworms. The provided method relies largely on the present standard production processes of silkworm silk, and hence a low level of investment is required. Since no additional chemicals are required, the provided method is environmentally friendly. | 06-25-2015 |
Patent application number | Description | Published |
20080284074 | Shock Absorber Capable of Damping Vibration - A shock absorber is provided that also includes vibration damping. The shock absorber includes at least one shock absorbing frame member that partially surrounds an electronic device enclosure. The shock absorber also includes at least two protrusions that protrude from the at least one shock absorbing frame member. Each protrusion extends beyond the at least one shock absorbing frame member from a recessed surface recessed into the at least one shock absorbing frame member. | 11-20-2008 |
20080304172 | DATA STORAGE MEDIUM HAVING SYSTEM DATA STORED IN A GUARD BAND BETWEEN ZONES OF CONSECUTIVE DATA STORAGE TRACKS - A storage medium format is provided having a first band of a plurality of consecutive data storage tracks having user data stored thereto, a second band of a plurality of consecutive data storage tracks having other user data stored thereto, and a guard track medially disposed therebetween the first band and the second band and having system data stored thereto. | 12-11-2008 |
20090027798 | IMPACT PROTECTION FOR A RETRACTABLE CONTROL OBJECT - Various embodiments of the present invention are generally directed to protecting a device from damage due to an impact event at the conclusion of a free fall condition through the use of a biasing signal that maintains a retention force until the impact event is completed. | 01-29-2009 |
20090031815 | MULTI-AXIS VIBRATION METHOD AND APPARATUS - A vibration test apparatus is disclosed. The vibration test apparatus includes a platform assembly, which receives a vibration input from a vibration source and imparts a multi-axial vibration to a test specimen on the platform assembly. In illustrated embodiments the platform assembly includes one or more platforms having an adjustable incline angle. The incline angle is adjusted to provide the desired output vibration based upon a measured or determined vibration profile and the input vibration from the vibration source. | 02-05-2009 |
20110255190 | Limiting Disc Deflection - A data storage apparatus and associated method is provided involving a data storage disc that is rotatable around a first axis. An actuator is rotatable around a second axis to operably position a data transfer member between an innermost radial location of the data storage disc and an outermost radial storage location of the data storage disc. A snubber is supported by the actuator and has a distal edge configured as being, in relation to a reference plane including the first axis and the second axis when the actuator is rotated to position the data transfer member at the innermost radial location, arcuate along a first radius on one side of the reference plane and arcuate along a second radius different than the first radius on the other side of the reference plane. | 10-20-2011 |
20110286131 | DIRECTING WINDAGE ESTABLISHED BY A ROTATING DISC - An apparatus and associated method for directing windage involves a body defining an aperture. A fastener is operably disposed in the aperture and is selectively engageable with a fixed support member between a first mode permitting rotation of the body around the fastener longitudinal axis, and a second mode affixing the body in place to the support member at a desired rotational orientation. A shroud depends from the body and is sized at a distal end for an operable mating relationship adjacent an arcuate edge of a disc that is rotatable around a disc axis. The shroud distal end is operably disposed a first distance from the fastener longitudinal axis in a direction of a plane including the fastener longitudinal axis and the disc axis. A leading edge of the shroud, with respect to a direction of windage established by disc rotation, is disposed a second distance from the fastener longitudinal axis that is the same or less than the first distance from the fastener longitudinal axis. | 11-24-2011 |
20140078616 | FLUID DYNAMIC MOTOR WITH REDUCED VIBRATIONS - An apparatus includes a hub, a first disk, a second disk, and a spacer. The hub is supported for relative rotation about a stationary component. The first disk is mounted to the hub with a first dynamic resonance mode associated therewith. The second disk is mounted to the hub with a second dynamic resonance mode associated therewith. The spacer is positioned between the first disk and the second disk, wherein the spacer is operable to cause the first dynamic resonance mode to be different from the second dynamic resonance mode. | 03-20-2014 |
20150147592 | STORAGE MEDIUM WITH LAYER(S) FOR ENHANCED HEATING - An apparatus that includes a storage layer and a heating assistance element. The heating assistance element is adjacent to the storage layer or doped into the storage layer. The heating assistance element is configured to enhance spatial confinement of energy from a field to an area of the storage layer to which the field is applied. | 05-28-2015 |
Patent application number | Description | Published |
20120168938 | PLASMA TREATMENT ON SEMICONDUCTOR WAFERS - A semiconductor wafer has integrated circuits formed thereon and a top passivation layer applied. The passivation layer is patterned and selectively etched to expose contact pads on each semiconductor die. The wafer is exposed to ionized gas causing the upper surface of passivation layer to roughen and to slightly roughen the upper surface of the contact pads. The wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer and a reconstituted wafer formed. Redistribution layers are formed to complete the semiconductor package having electrical contacts for establishing electrical connections external to the semiconductor package, after which the wafer is singulated to separate the dice. | 07-05-2012 |
20120168942 | THROUGH HOLE VIA FILLING USING ELECTROLESS PLATING - An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating. | 07-05-2012 |
20120168943 | PLASMA TREATMENT ON SEMICONDUCTOR WAFERS - A semiconductor package and method of forming the same is described. The semiconductor package is formed from a semiconductor die cut from a semiconductor wafer that has a passivation layer. The semiconductor wafer is exposed to ionized gas causing the passivation layer to roughen. The semiconductor wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer to form a reconstituted wafer, and an encapsulation layer is formed enclosing the adhesive layer and the plurality of semiconductor dies. The passivation layer is removed and the semiconductor package formed includes electrical contacts for establishing electrical connections external to the semiconductor package. | 07-05-2012 |
20120168944 | THROUGH HOLE VIA FILLING USING ELECTROLESS PLATING - An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating. | 07-05-2012 |
20120282767 | METHOD FOR PRODUCING A TWO-SIDED FAN-OUT WAFER LEVEL PACKAGE WITH ELECTRICALLY CONDUCTIVE INTERCONNECTS, AND A CORRESPONDING SEMICONDUCTOR PACKAGE - A semiconductor packaging process includes drilling apertures in a reconstituted wafer, then filling the apertures with conductive paste by wiping a quantity of the paste across a back surface of the wafer so that paste is forced into the apertures. The paste is cured to form conductive posts. The wafer is thinned, and redistribution layers are formed on front and back surfaces of the wafer, with the posts acting as interconnections between the redistribution layers. In an alternative process, blind apertures are drilled. A dry film resist is applied to the front surface of the wafer, and patterned to expose the apertures. Conductive paste is applied from the front. To prevent paste from trapping air pockets in the apertures, the wiping process is performed under vacuum. After curing the paste, the wafer is thinned to expose the cured paste in the apertures, and redistribution layers are formed. | 11-08-2012 |
20130168858 | EMBEDDED WAFER LEVEL BALL GRID ARRAY BAR SYSTEMS AND METHODS - A bar formed from a reconstituted wafer and containing one or more conductive material filled voids is used to electrically and physically connect the top and bottom packages in a package-on-package (PoP) package. The bar is disposed in the fan out area of the lower package forming the PoP package. | 07-04-2013 |
20140057394 | METHOD FOR MAKING A DOUBLE-SIDED FANOUT SEMICONDUCTOR PACKAGE WITH EMBEDDED SURFACE MOUNT DEVICES, AND PRODUCT MADE - A manufacturing process includes forming a reconstituted wafer, including embedding semiconductor dice in a molding compound layer and forming through-wafer vias in the layer. A fan-out redistribution layer is formed on a front side of the wafer, with electrical traces interconnecting the dice, through-wafer vias, and contact pads positioned on the redistribution layer. Solder balls are positioned on the contact pads and a molding compound layer is formed on the redistribution layer, reinforcing the solder balls. A second fan-out redistribution layer is formed on a back side of the wafer, with electrical traces interconnecting back ends of the through-wafer vias and contact pads positioned on a back face of the second redistribution layer. Flip-chips and/or surface-mounted devices are coupled to the contact pads of the second redistribution layer and encapsulated in an underfill layer formed on the back face of the second redistribution layer. | 02-27-2014 |
20140175649 | ELECTRONIC DEVICE INCLUDING ELECTRICALLY CONDUCTIVE VIAS HAVING DIFFERENT CROSS-SECTIONAL AREAS AND RELATED METHODS - An electronic device may include a bottom interconnect layer having a first electrically conductive via therein. The electronic device may also include an integrated circuit (IC) carried by said bottom interconnect layer, and an encapsulation material on the bottom interconnect layer and surrounding the IC. The encapsulation layer may have a second electrically conductive via therein aligned with the first electrically conductive via. The second electrically conductive via may have a cross-sectional area larger than a cross-sectional area of the first electrically conductive via. | 06-26-2014 |
Patent application number | Description | Published |
20100250244 | ENCODER AND DECODER - There is provided an encoder capable of improving inter-channel prediction (ICP) performance in scalable stereo sound encoding using an ICP. In the encoder, ICP analysis units ( | 09-30-2010 |
20110046946 | ENCODER, DECODER, AND THE METHODS THEREFOR - Provided is an encoder which can decode a high-quality stereo signal while keeping the amount of information in the bit allocation information to a minimum when a scalable coding technique is used for a stereo signal. In the encoder, a principal component analysis (PCA) converter ( | 02-24-2011 |
20110288872 | STEREO ACOUSTIC SIGNAL ENCODING APPARATUS, STEREO ACOUSTIC SIGNAL DECODING APPARATUS, AND METHODS FOR THE SAME - Disclosed is a stereo acoustic signal encoding apparatus in which the signal quality does not deteriorate if there are a plurality of sound sources. A peak tracing unit ( | 11-24-2011 |
20120215526 | ENCODER, DECODER AND METHODS THEREOF - An encoder whereby the bit efficiency of encoding can be improved, thereby improving the qualities of signals as decoded. In the encoder: a time-frequency converting unit ( | 08-23-2012 |
20120259622 | AUDIO ENCODING DEVICE AND AUDIO ENCODING METHOD - Disclosed is an audio encoding device which removes unnecessary inter-channel parameters from the subject to be encoded, improving the encoding efficiency thereby. In this audio encoding device, a principal component analysis unit ( | 10-11-2012 |
20130030796 | AUDIO ENCODING APPARATUS AND AUDIO ENCODING METHOD - An audio encoding apparatus that allows a decoded signal exhibiting an excellent sound quality to be obtained on a decoding side. In the audio encoding apparatus ( | 01-31-2013 |
20130103394 | DEVICE AND METHOD FOR EFFICIENTLY ENCODING QUANTIZATION PARAMETERS OF SPECTRAL COEFFICIENT CODING - This invention introduces apparatus and methods to efficiently encode the quantization parameters of split multi-rate lattice vector quantization. In this invention, by doing spectral analysis on the split multi-rate vector quantized spectrum, the spectrum is split to null vectors region and non-null vectors region. For the null vectors region, instead of transmitting series of indication for null vectors, an indication of null vectors region and the quantized value of index of the ending vector in the null vectors region (or the number of the null vectors in the null vectors region) are transmitted. The indication of null vectors region can be designed in many ways, the only requirement is the indication should be distinguishable in the decoder side. The ending index or the number of null vectors can be quantized by an adaptively designed codebook. By applying of the invented method, some bits can be saved from the codebook indications. | 04-25-2013 |
20130173275 | AUDIO ENCODING DEVICE AND AUDIO DECODING DEVICE - Provided is an audio encoding device that can suppress degradation of audio quality. Spectral coefficients of synthesized signal from CELP core layer are utilized to fulfill spectral gaps in error signal spectrum coefficients from a transform coding layer. By both spectral coefficients, decoded signal spectral coefficients are generated. The decoded signal spectral coefficients and the input signal spectral coefficients are divided into a plurality of sub bands. In each sub band, the energy of the input signal spectral coefficient corresponding to a zero decoded error signal spectral coefficient is calculated, and the energy of the decoded signal spectral coefficient corresponding to the zero decoding error signal spectral coefficient is calculated, and their energy ratio is calculated and is quantized and transmitted. | 07-04-2013 |
20140114651 | DEVICE AND METHOD FOR EXECUTION OF HUFFMAN CODING - In this invention, the design of the Huffman table can be done offline with a large input sequence database. The range of the quantization indices (or differential indices) for Huffman coding is identified. For each value of range, all the input signal which have the same range will be gathered and the probability distribution of each value of the quantization indices (or differential indices) within the range is calculated. For each value of range, one Huffman table is designed according to the probability. And in order to improve the bits efficiency of the Huffman coding, apparatus and methods to reduce the range of the quantization indices (or differential indices) are also introduced. | 04-24-2014 |
20140249806 | AUDIO ENCODING APPARATUS, AUDIO DECODING APPARATUS, AUDIO ENCODING METHOD, AND AUDIO DECODING METHOD - An audio encoding apparatus capable of reducing the bit rate even if a codebook having a larger codebook number is selected in a split multi-rate lattice vector quantization is provided. Sub-vector determining unit ( | 09-04-2014 |
20150025879 | AUDIO AND SPEECH CODING DEVICE, AUDIO AND SPEECH DECODING DEVICE, METHOD FOR CODING AUDIO AND SPEECH, AND METHOD FOR DECODING AUDIO AND SPEECH - This invention introduces audio/speech encoding apparatus audio/speech decoding apparatus, audio/speech encoding method and audio/speech decoding method to efficiently encode the quantization parameters of split multi-rate lattice vector quantization. In this invention, the position of the sub-vector whose codebook indication consumes the most bits is firstly located, and then the value of the codebook is estimated based on the total number of bits available and the bits usage information for other sub-vectors. The difference value is calculated between the actual value and estimated value. Finally, instead of transmitting the codebook indication which consumes the most bits, the position of the sub-vector whose codebook indication consumes the most bits and the difference value between the actual value and the estimated value are transmitted. By applying of the invented method, bits can be saved by the codebook indications. | 01-22-2015 |