Patent application number | Description | Published |
20090258616 | MULTISYSTEM WIRELESS COMMUNICATION APPARATUS - A wireless communication apparatus capable of being communicated by employing communication systems is provided with: communication units containing a system-A communication unit for performing a communication operation by a wireless signal using a GSM communication system, and a system-B communication unit for performing a communication operation by an wireless signal using a UMTS communication system; a power supply voltage detecting unit for detecting a voltage of a power supply applied to the communication units in a predetermined time period; and a power supply control unit operated in such a control manner that when the power supply voltage is lower than, or equal to the final voltage of the GSM communication system, the communication operation by the system-A communication unit is stopped, whereas the power supply voltage is higher than the final voltage of the UMTS communication system, the communication operation by the system-B communication unit is continuously carried out. | 10-15-2009 |
20110072320 | CACHE SYSTEM AND CONTROL METHOD THEREOF, AND MULTIPROCESSOR SYSTEM - According to the embodiments, a cache system includes a cache-data storing unit and a failure detecting unit. The failure detecting unit detects failure in units of cache line by determining whether instruction data prefetched from a lower layer memory matches cache data read out from the cache-data storing unit. A cache line in which failure is detected is invalidated. | 03-24-2011 |
20110078324 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - There is provided an information processing apparatus including a communication unit which communicates with a distribution server that contains content data for streaming delivery, a buffer unit which temporarily stores stream data obtained from the distribution server, a storage unit which stores an inserting content, a reproduction unit which reproduces the content inserted by the storage unit, and a control unit which measures a bandwidth of the network, determines whether it is possible to reproduce until the end of a next chapter defined by a chapter point set in the content based on a buffer volume of the buffer unit and the bandwidth, and when determined it is impossible, switches the content to be produced by the reproduction unit to the inserting content. | 03-31-2011 |
20110117960 | ELECTRONIC DEVICE AND IMAGING METHOD - Provided are an electronic device and an imaging method which improve the zoom operability. A mobile telephone ( | 05-19-2011 |
20110213936 | PROCESSOR, MULTIPROCESSOR SYSTEM, AND METHOD OF DETECTING ILLEGAL MEMORY ACCESS - A processor included in a multiprocessor system including a shared memory, the processor according to an embodiment of the present invention comprises: a storing unit that stores a break occurrence memory area that is address information of the shared memory; and a break generator that causes memory access break when the break occurrence memory area is accessed and puts the processor to a debug state. The break occurrence memory area includes address information of the shared memory in another processor included in the multiprocessor system. | 09-01-2011 |
20120331448 | COVERAGE MEASUREMENT APPARATUS AND METHOD AND MEDIUM - According to one embodiment, a coverage measurement apparatus includes a compiler unit, an execution environment unit, and a coverage calculation unit. The compiler unit produces a first object code from a program to be subjected to coverage measurement, and inserts an instruction to switch to a code rewriting process into the first object code, the code rewriting process being such that when the instruction is executed, the instruction is rewritten into a no-operation instruction. The execution environment unit executes the first object code, thereby producing a second object code. The coverage calculation unit calculates, based on the first and second object codes, the coverage of the program to be subjected to the coverage measurement. | 12-27-2012 |
Patent application number | Description | Published |
20080320227 | Cache memory device and cache memory control method - A cache memory device that includes a cache which stores data and tag information specifying an address of stored data, includes a detection unit that detects an error by reading out the tag information when a writing/readout request of desired data occurs to the cache, a search unit that searches the tag information for an address of the desired data when no error is detected in the tag information as a result of error detection by the detection unit, a memory unit that stores an address of data that is to be replaced by the desired data, the address being contained in the tag information, when the address of the desired data is not contained in the tag information as a result of search by the search unit, and a control unit that requests an external unit to replace data with a use of the address stored by the memory unit. | 12-25-2008 |
20090031188 | ERROR CORRECTING CODE GENERATION METHOD AND MEMORY CONTROL APPARATUS - An objective of the present invention is to make it possible to appropriately correct an error of data in a cache memory. A store processing unit generates an nt-ECC on the basis of data stored in a non-target area that was read out from a cache memory with a search of the cache memory, and generates t-ECC on the basis of the data to be stored in the buffer. | 01-29-2009 |
20100107038 | Cache controller and cache controlling method - A cache memory controlling unit includes a plurality of STBs for maintaining 8-byte store data received from an execution unit, a plurality of WBs, a DATA-RAM, an FCDR, and an ECC-RAM. The cache memory controlling unit having such a structure obtains data-not-to-be-stored from the DATA-RAM, stores the obtained data in the FCDR, and merges the stored data with data-to-be-stored in the store data output from the execution unit and stored in the STBs or the WBs to generate new store data. The cache memory controlling unit then writes the generated new store data in the DATA-RAM, generates an ECC from the new store data, and writes the ECC in the ECC-RAM. | 04-29-2010 |
20140136796 | ARITHMETIC PROCESSING DEVICE AND METHOD FOR CONTROLLING THE SAME - An arithmetic processing device includes a cache memory, a first controller configured to control the cache memory and a second controller assigned a non-cache space to be accessed without use of the cache memory, wherein, when a condition, that out-of-order processing of a first and a second access requests for the non-cache space is possible and access targets of the first and second access requests are the same, is satisfied, the first controller issues the second access request to the second controller without waiting for a completion notification from the second controller with respect to the first access request previously issued to the second controller, and when the condition is not satisfied, the first controller issues the second access request to the second controller after waiting for a completion notification from the second controller with respect to first access request previously issued to the second controller. | 05-15-2014 |
Patent application number | Description | Published |
20090083682 | SIMULATION APPARATUS AND CONTROL METHOD OF SIMULATION - A simulation apparatus, including a first simulator assigning an operating cycle number, a second simulator assigning an operating cycle number, and a control portion for synchronously controlling the first simulator and the second simulator, the control portion causing communication between the first simulator and the second simulator so as to control control-information and synchronous-information of the first simulator and the second simulator, the control-information controlling operations of the first simulator and the second simulator, wherein the control portion sets up the operating cycle numbers of the first simulator and the second simulator at a first cycle value when a synchronous condition of the synchronous-information is established, the control portion sets up at least one of the operating cycle numbers of the first simulator and the second simulator at a second cycle value being larger than the first cycle value when the synchronous condition of the synchronous-information is not established. | 03-26-2009 |
20090204384 | DEBUGGING DEVICE, DEBUGGING METHOD AND HARDWARE EMULATOR - A hardware emulator having: a verification target circuit that includes a CPU in which progress of instruction execution is controlled by a program counter, and a circuit that operates according to the instruction execution by the CPU; at least one replica circuit that is formed by replication of the verification target circuit; a debug controller that starts operation of the verification target circuit upon receipt of an operation start signal from an outside of the hardware emulator, and that stops operation of the verification target circuit and the replica circuit when a value of the program counter of the verification target circuit reaches a predetermined breakpoint; an execution start delaying portion that causes the replica circuit to start execution of an instruction with a delay equivalent to a predetermined number of instructions after the verification target circuit starts execution of the same instruction; a program counter controller that performs control so that the value of the program counter of the verification target circuit and a value of a program counter of the replica circuit are simultaneously updated when both of the verification target circuit and the replica circuit complete the execution of their respective running instructions; and an output portion that sends an output from any one of the verification target circuit and the replica circuit to the outside of the hardware emulator in response to a request from the outside of the hardware emulator. | 08-13-2009 |
20090319994 | SYSTEM FOR DEBUGGING COMPUTER PROGRAM - First tag addresses and data are stored in association with first index addresses in a memory cell unit provided in a cache memory. The first tag addresses and the first index addresses are configured based on address information respectively. Designation address information is provided to designate an address to read one of the stored data. The designation address information is converted to a second index address and second tag address by an address converter, in order to read the one of the stored data according to the designation address information. The memory cell unit is accessed according to the obtained second index address. When one of the first tag addresses matches the second tag address, the one of the data corresponding to the one of the first tag addresses is read. The designation address information and the one of the data are displayed in a cache memory display unit. | 12-24-2009 |