Patent application number | Description | Published |
20090170254 | Method of Manufacturing a Semiconductor Device - In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are formed in the first area of the substrate adjacent the first gate electrode. A layer having a first stress is formed on the substrate and the first and the second gate electrodes. A mask is formed on a first portion of the layer in the first area of the substrate to expose a second portion of the layer in the second area. The second portion is etched to form a sacrificial spacer on a sidewall of the second gate electrode. The second area of the substrate is partially etched using the mask, the second gate electrode and the sacrificial spacer, to form recesses in the second area of the substrate adjacent the second gate electrode. Patterns having a second stress are formed in the recesses. | 07-02-2009 |
20100006906 | Semiconductor device, single crystalline silicon wafer, and single crystalline silicon ingot - A semiconductor device includes a single crystalline substrate and an active region defined in the single crystalline substrate, wherein a major axis direction of the active region is aligned with a <0,1,1> family direction. | 01-14-2010 |
20100171181 | METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL SOURCE/DRAIN - A method of forming a semiconductor device includes forming a device isolation region in a silicon substrate to define an nMOS region and a pMOS region. A p-well is formed in the nMOS region and an n-well in the pMOS region. Gate structures are formed over the p-well and n-well, each gate structure including a stacked structure comprising a gate insulating layer and a gate electrode. A resist mask covers the nMOS region and exposes the pMOS region. Trenches are formed in the substrate on opposite sides of the gate structures of the pMOS region. SiGe layers are grown in the trenches of the pMOS region. The resist mask is removed from the nMOS region. Carbon is implanted to an implantation depth simultaneously on both the nMOS region and the pMOS region to form SiC on the nMOS region and SiGe on the pMOS region. | 07-08-2010 |
20100233864 | Methods of fabricating a semiconductor device - Methods of fabricating a semiconductor device are provided, the methods include forming a gate stack on a substrate, forming an insulation layer on the substrate to cover the gate stack, forming a spacer at both side walls of the gate stack by etching the insulation layer, and ion implanting impurities in the spacer or the insulation layer. | 09-16-2010 |
20100304543 | SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME - A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern. | 12-02-2010 |
20110136311 | SEMICONDUCTOR DEVICE HAVING A LOCALLY BURIED INSULATION LAYER AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device having a locally buried insulation layer and a method of manufacturing a semiconductor device having the same are provided, in which a gate electrode is formed on a substrate, and oxygen ions are implanted into an active region to form a locally buried insulation layer. An impurity layer is formed on the locally buried insulation layer to form a source/drain. A silicide layer is formed on the source/drain and on the gate electrode. The locally buried insulation layer can prevent junction leakage, decrease junction capacitance and prevent a critical voltage of an MOS transistor from increasing due to body bias, thereby to improve characteristics of the device. | 06-09-2011 |
20110201166 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming a gate electrode on a semiconductor substrate and a sidewall spacer on the gate electrode. Then, a portion of the semiconductor substrate at both sides of the sidewall spacer is partially etched to form a trench. A SiGe mixed crystal layer is formed in the trench. A silicon layer is formed on the SiGe mixed crystal layer. A portion of the silicon layer is partially etched using an etching solution having different etching rates in accordance with a crystal direction of a face of the silicon layer to form a capping layer including a silicon facet having an (111) inclined face. | 08-18-2011 |
20110230027 | Methods of Forming Semiconductor Devices Having Faceted Semiconductor Patterns - Provided are methods of forming semiconductor devices. A method may include preparing a semiconductor substrate including a first region and a second region adjacent the first region. The method may also include forming sacrificial pattern covering the second region and exposing the first region. The method may further include forming a capping layer including a faceted sidewall on the first region using selective epitaxial growth (SEG). The faceted sidewall may be separate from the sacrificial pattern. The sacrificial pattern may be removed. Impurity ions may be implanted into the semiconductor substrate. | 09-22-2011 |
20120021537 | METHODS OF EVALUATING EPITAXIAL GROWTH AND METHODS OF FORMING AN EPITAXIAL LAYER - A method of evaluating an epitaxial growing process includes forming a mold layer on each of a plurality of substrates, forming a photoresist pattern on each mold layer, the photoresist pattern having opening portions, a total area of a bottom portion of the opening portions being different for each substrate, patterning each mold layer to expose a surface portion of the substrate to form an evaluation pattern on each substrate, evaluation patterns including opening portions corresponding to the opening portion in the photoresist pattern, determining substrate opening ratios for each substrate based on the opening portions in the evaluation pattern thereon, the substrate opening ratios being different for each substrate, performing a selective epitaxial process on each substrate to form an epitaxial layer, and evaluating characteristics of the epitaxial layer for each substrate to determine an optimal substrate opening ratio. | 01-26-2012 |
20120223364 | TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer. | 09-06-2012 |
20130161751 | SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS - A semiconductor device includes a substrate having a channel region, a gate insulation layer on the channel region, a gate electrode on the gate insulation layer, and source and drain regions in recesses in the substrate on both sides of the channel region, respectively. The source and drain regions include a lower main layer whose bottom surface is located at level above the bottom of a recess and lower than that of the bottom surface of the gate insulation layer, and a top surface no higher than the level of the bottom surface of the gate insulation layer, and an upper main layer contacting the lower main layer and whose top surface extends to a level higher than that of the bottom surface of the gate insulation layer, and in which the lower layer has a Ge content higher than that of the upper layer. | 06-27-2013 |
20130320434 | SEMICONDUCTOR DEVICE HAVING EMBEDDED STRAIN-INDUCING PATTERN AND METHOD OF FORMING THE SAME - In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm. | 12-05-2013 |
20150064870 | SEMICONDUCTOR DEVICE HAVING EMBEDDED STRAIN-INDUCING PATTERN AND METHOD OF FORMING THE SAME - In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm. | 03-05-2015 |
20150145088 | IMAGE SENSOR AND FABRICATING METHOD THEREOF - A method of fabricating an image sensor is provided. The method may include preparing a substrate with first to third pixel regions, coating a first color filter layer on the substrate, sequentially forming a first sacrificial layer and a first protection layer to cover the first color filter layer, forming a first photoresist pattern on the first protection layer to be overlapped with the first pixel region, performing a first dry etching process using the first photoresist pattern as an etch mask to the first sacrificial layer and the first protection layer to form a first color filter, a first sacrificial pattern, and a first protection pattern sequentially stacked on the first pixel region, and selectively removing the first sacrificial pattern to separate the first protection pattern from the first color filter. | 05-28-2015 |
Patent application number | Description | Published |
20090096037 | SEMICONDUCTOR DEVICE HAVING RECESSED FIELD REGION AND FABRICATION METHOD THEREOF - A semiconductor device including an active region formed on a semiconductor substrate, and a field region adjacent to the active region, which is able to increase a width of the active region through use of a field recess portion at one surface side of the field region. The field recess portion may be laterally adjacent to a portion of the active region, thereby resulting in an increase of a width of the active region. A gate insulating film and a gate electrode may be formed on the field region and the active region, the gate insulating film and the gate electrode being formed in the field recess portion. The width of the active region may be a channel width. | 04-16-2009 |
20090258463 | METHODS OF FABRICATING DIFFERENT THICKNESS SILICON-GERMANIUM LAYERS ON SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES FABRICATED THEREBY - Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas. | 10-15-2009 |
20120196772 | COMPOUND SYNTHESIS METHOD, MICROARRAY, ACID-TRANSFER COMPOSITION, AND BIOCHIP COMPOSITION - A compound synthesis method includes bonding a first compound to a substrate to form a first film. A second film is formed on the first film using an acid-transfer composition including (A) a polymer that includes a structural unit shown by a following formula (1) and a structural unit shown by a following formula (2), (B) a photoacid generator shown by a following formula (3), and (C) a sensitizer shown by a following formula (4). The second film is exposed to remove the protecting group from the first compound under an exposed are of the second film. An acid generated in the exposed area of the second film is transferred to the first film. The second film after being exposed is removed. A second compound is bonded to the first compound from which the protecting group has been removed. | 08-02-2012 |
20120228720 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES HAVING DIFFERENT THICKNESS SILICON-GERMANIUM LAYERS - Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas. | 09-13-2012 |
20140372726 | MEMORY MANAGEMENT METHOD AND APPARATUS - A method for managing memory using a virtual memory manager includes receiving a memory allocation request, allocating memory of a physical address space in response to the memory allocation request, mapping an address value of the memory allocated in the physical address space to consecutive primary virtual address space, and mapping the address value of the primary virtual address space to one of a first and second secondary virtual address spaces to process a new memory allocation request in a situation where memory a fragmentation occurs. Other embodiments are also disclosed. The methods and apparatuses of the present disclosure are capable of moving active memory blocks of the fragmented virtual memory space to another virtual memory space to resolve the memory fragmentation even when a memory fragmentation occurs. | 12-18-2014 |
20150024587 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. An etch-target layer is formed on a substrate. A photoresist layer is formed on the etch-target layer. A first exposure process is performed using a first photo mask to form a plurality of first-irradiated patterns in the photoresist layer. The first photo mask includes a plurality of first transmission regions. Each first transmission region has different optical transmittance. A second exposure process is performed using a second photo mask to form a plurality of second-irradiated patterns in the photoresist layer. The second photo mask includes a plurality of second transmission regions. Each second transmission region has different optical transmittance. A photoresist pattern is formed from the photoresist layer by removing the plurality of first-irradiated and second-irradiated patterns from the photoresist layer. A lower structure is formed from the etch-target layer by etching the etch-target layer using the photoresist pattern. | 01-22-2015 |
Patent application number | Description | Published |
20080305636 | METHOD OF FORMING FINE PATTERN EMPLOYING SELF-ALIGNED DOUBLE PATTERNING - There are provided a method of forming a fine pattern employing self-aligned double patterning. The method includes providing a substrate. First mask patterns are formed on the substrate. A reactive layer is formed on the substrate having the first mask patterns. The reactive layer adjacent to the first mask patterns is reacted using a chemical attachment process, thereby forming sacrificial layers along outer walls of the first mask patterns. The reactive layer that is not reacted is removed to expose the sacrificial layers. Second mask patterns are formed between the sacrificial layers adjacent to sidewalls of the first mask patterns facing each other. The sacrificial layers are removed to expose the first and second mask patterns and the substrate exposed between the first and second mask patterns. The substrate is etched using the first and second mask patterns as an etching mask. | 12-11-2008 |
20110189608 | PHOTORESIST COMPOSITION FOR FABRICATING PROBE ARRAY, METHOD OF FABRICATING PROBE ARRAY USING THE PHOTORESIST COMPOSITION, COMPOSITION FOR PHOTOSENSITIVE TYPE DEVELOPED BOTTOM ANTI-REFLECTIVE COATING, FABRICATING METHOD OF PATTERNS USING THE SAME AND FABRICATING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME - A photoresist composition for fabricating a probe array is provided. The photoresist composition includes a photoacid generator having an onium salt and an i-line reactive sensitizer. | 08-04-2011 |
20110244397 | Methods of Fabricating a Microarray - A method of fabricating a microarray is provided, which includes providing a substrate having a surface that is protected by an acid labile protective group that includes an acetal group represented by formula (1) and has a functional group that can be coupled with a monomer of a probe; applying a photoresist including a photo acid generator to the substrate; selectively exposing the photoresist to deprotect the acid labile protective group that corresponds to an exposed region; removing the photoresist; and coupling the monomer that is combined with the acid labile protective group with the deprotected functional group. Formula (1) has the following structure: | 10-06-2011 |
20120224028 | METHOD OF FABRICATING MICROLENS, AND DEPTH SENSOR INCLUDING MICROLENS - A method of fabricating a microlens includes forming layer of photoresist on a substrate, patterning the layer of photoresist, and then reflowing the photoresist pattern. The layer of photoresist is formed by coating the substrate with liquid photoresist whose viscosity is 150 to 250 cp. A depth sensor includes a substrate and photoelectric conversion elements at an upper portion of the substrate, a metal wiring section disposed on the substrate, an array of the microlenses for focusing incident light as beams onto the photoelectric conversion elements and which beams avoid the wirings of the metal wiring section. The depths sensor also includes a layer presenting a flat upper surface on which the microlenses are formed. The layer may be a dedicated planarization layer or an IR filter, interposed between the microlenses and the metal wiring section. | 09-06-2012 |