Won Hyung
Won Hyung Cho, Seoul KR
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20110129125 | BIOCHIP DETECTION SYSTEM WITH IMAGE CORRECTION UNIT AND DISTORTED IMAGE CORRECTING METHOD USING THE SAME - The present disclosure relates to a biochip detection system capable of correcting a distorted part of detection data acquired by a detection stage rotated at high speed for detecting bio-information of the biochip, and a method of correcting the distorted image of the detection data using the same. The biochip detection system with a rotatable detection stage capable of loading at least one biochip thereon to detect information of the biochip by emitting light includes a detector detecting and converting light reflected from the biochip into a detection signal, an image data unit converting the detection signal into image data, and an image correction unit correcting a distorted image of the detection signal. The biochip detection system can correct an image, which is distorted during detection of the high-speed rotatable detection stage, into an orthogonal image, so that more accurate and reliable bio-information can be quickly acquired. | 06-02-2011 |
Won Hyung Lee, Daejeon KR
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20150376173 | SPHINGOSINE-1-PHOSPHATE RECEPTOR AGONISTS, METHODS OF PREPARING THE SAME, AND PHARMACEUTICAL COMPOSITIONS CONTAINING THE SAME AS AN ACTIVE AGENT - The present invention relates to novel compounds of Formula 1 as sphingosine-1-phosphate receptor agonists which can be effectively used for the treatment of autoimmune diseases, a method for preparing the same, and a pharmaceutical composition comprising the same as an active component. The compounds according to the present invention are effective on extensive autoimmune diseases and chronic inflammatory diseases including relapsing-remitting multiple sclerosis, and can also be used for treating or preventing immunoregulation disorders. | 12-31-2015 |
Won Hyung Park, Busan KR
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20110247858 | Printed Circuit Board and Method Of Manufacturing The Same - Disclosed herein is a printed circuit board, including: a substrate; a first circuit layer formed on the substrate; a first insulation layer formed on the first circuit layer and having a pattern corresponding to that of the first circuit layer; and a second insulation layer formed on the substrate such that the second insulation layer surrounds the first circuit layer and the first insulation layer formed on the first circuit layer. The printed circuit board is advantageous in that process time and process cost can be reduced because a first insulation layer is used as an etching resist and is included as a part of a printed circuit board even after etching. | 10-13-2011 |
20120171432 | Substrate structure and method of manufacturing the same - Provided is a substrate structure including: a base substrate on which a conductive pattern is formed; a first plating layer covering the conductive pattern; and a second plating layer covering the first plating layer, wherein the first plating layer includes an electroless reduction plating layer. | 07-05-2012 |
20140110023 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a method of manufacturing a printed circuit board, including the steps of providing a substrate including a first metal layer formed thereon, and forming a patterned first insulation layer on the first metal layer. The method further includes patterning the first metal layer to allow the first metal layer to have a pattern corresponding to that of the first insulation layer, thus forming a first circuit layer, and forming a second insulation layer on the substrate such that the second insulation layer surrounds the first circuit layer and the first insulation layer formed on the first circuit layer. The printed circuit board is advantageous in that process time and process cost can be reduced because a first insulation layer is used as an etching resist and is included as a part of a printed circuit board even after etching. | 04-24-2014 |
Won Hyung Yoo, Seoul KR
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20090258451 | Liquid crystal display device - An LCD device is disclosed in which column spacers for a cell gap are arranged between gate and common lines to reduce a contact area between the column spacers and an opposing substrate, and a stable cell gap is maintained over the whole panel by reducing variation of a thickness per area of a thin film transistor (TFT) substrate corresponding to the column spacers. The LCD device includes first and second substrates facing each other, gate and data lines formed on the first substrate to cross each other, and pixel regions, a thin film transistor formed in each portion where the gate and data lines cross, common and pixel electrodes alternately formed in the pixel regions, common lines formed adjacent to the gate lines substantially parallel to the gate lines, a first column spacer formed on the second substrate corresponding to a portion between the gate line and the common line, and a liquid crystal layer filled between the first and second substrates. | 10-15-2009 |
20130033654 | IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device includes first and second substrates and a liquid crystal layer interposed therebetween; a gate line, a data line and a common line over the first substrate in the display area; a thin film transistor connected to the gate line and the data line; a color filter layer over the thin film transistor; a first passivation layer over the color filter layer; an auxiliary common line, inner common electrodes and pixel electrodes over the first passivation layer, wherein the auxiliary common line includes a vertical portion and a horizontal portion, the inner common electrodes extend from the horizontal portion, and the pixel electrodes alternate the inner common electrodes; a light blocking pattern in the non-display area, wherein the light blocking pattern includes the same materials as the color filter layer. | 02-07-2013 |
Won-Hyung Cho, Seongnam-Si KR
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20150189164 | ELECTRONIC APPARATUS HAVING A PHOTOGRAPHING FUNCTION AND METHOD OF CONTROLLING THE SAME - In an electronic apparatus having a photographing function and a method of controlling the same, a qualitative description and a quantitative setting link with each other flexibly so as to provide a mixed linkage guide so that the qualitative description and the quantitative setting may be reused, and a qualitative description and a quantitative setting which will be added later may link with each other freely. | 07-02-2015 |
Won-Hyung Lee, Seoul KR
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20140188584 | PRODUCT PRICING SYSTEM ON ELECTRONIC COMMERCE USING THE INTERNET - In one embodiment, the product pricing system in e-commerce using the internet, comprises a sale condition management module receiving a sale condition information entered from a seller that includes a lowest set price, a customer price and a prepared number of a product, wherein the lowest set price for a product is determined according to whole sale of the prepared number of a product; a purchase condition management module generating purchase group information by counting a purchased number for each bid price through a product bid price and a purchased number of a product entered from a customer; a status management module generating discount information according to a purchased number of a product based on the sale condition information, and generating varying price information by adding the discount information and the purchase group information; and a pricing module generating a pricing information by setting a price of the product, wherein the price of the product set at the value where the purchase group information matches with the discount information. | 07-03-2014 |
Won-Hyung Moon, Seoul KR
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20120195441 | METHOD OF OUTPUTTING AUDIO SIGNAL AND AUDIO SIGNAL OUTPUT APPARATUS USING THE METHOD - An audio signal output apparatus includes a modulation signal generator for generating a first modulation signal by pulse-modulating an input audio signal of one channel using a first carrier signal or a first sampling clock, which has a first frequency; a vacuum tube filter unit comprising a vacuum tube and for generating a vacuum tube signal by allowing the first modulation signal to pass through the vacuum tube; a frequency modulation unit for generating a second modulation signal by pulse-modulating the vacuum tube signal; and a power switching amplifier for outputting an amplification signal corresponding to the second modulation signal. | 08-02-2012 |
20130094673 | METHOD AND APPARATUS FOR OUTPUTTING AUDIO SIGNAL - An apparatus for outputting an audio signal with improved sound quality is provided. The apparatus includes a modulation and amplification unit for pulse modulation and switching amplification of an input audio signal and generating an amplified signal which corresponds to the input audio signal; and a vacuum tube amplification unit for inputting a vacuum tube signal generated by attenuating the amplified signal and adding harmonics of a vacuum tube to the amplified signal, to the modulation and amplification unit to provide a mellow sound. | 04-18-2013 |
Won-Hyung Song, Osan-Si KR
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20120250434 | METHOD OF ACCELERATING WRITE TIMING CALIBRATION AND WRITE TIMING CALIBRATION ACCELERATION CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE - A method of accelerating write timing calibration and a write timing calibration acceleration circuit in a semiconductor memory device are disclosed. The write timing calibration acceleration circuit includes a phase difference detection unit and a detection data output unit. The phase difference detection unit detects a phase difference between a first signal and a second signal applied for a write timing calibration. The detection data output unit outputs detection data corresponding to the detected phase difference through a data output line. According to the write timing calibration acceleration circuit of the inventive concept, a time taken to perform a write timing calibration is reduced, thereby minimizing boot up time and power consumption. | 10-04-2012 |
20130002277 | SEMICONDUCTOR MODULE, TEST SYSTEM AND METHOD EMPLOYING THE SAME - A semiconductor module includes a plurality of module pins and a semiconductor device. Module pins receive an identification pattern signal having M bits and outputs a test identification pattern, where M is a positive integer. The semiconductor device includes device pins, and outputs the identification pattern signal through the device pins in response to a connection identification control signal for identifying a configuration of pin connections between the module pins and the device pins. The semiconductor module effectively identifies a configuration of pin connections between the module pins and the device pins. | 01-03-2013 |
20140131895 | MEMORY MODULE AND MEMORY SYSTEM - A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal. | 05-15-2014 |
20140219044 | MEMORY MODULE AND MEMORY SYSTEM COMPRISING SAME - A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (MRS) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an MRS command received from a command decoder, and an address buffer configured to store a predetermined address signal, to receive an address signal and corresponding data from an external device, and to compare the address signal received with the predetermined address signal in response to the enable signal. As a consequence of determining that the address signal received from the external device is the same as the predetermined address signal stored in the address buffer, data different from the corresponding data received from the external device is written to a memory cell corresponding to the predetermined address signal. | 08-07-2014 |
20150016047 | MEMORY MODULE - A memory module that includes: a printed circuit board having a connecting terminal; memory chips arranged on the printed circuit board; data buffers disposed on a first surface of the printed circuit board and corresponding to the memory chips; and resistance units disposed on a second surface of the printed circuit board and corresponding to the data buffers. | 01-15-2015 |
20150262620 | MEMORY MODULE AND MEMORY SYSTEM - A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal. | 09-17-2015 |
Won-Hyung Song, Seoul KR
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20110310685 | MEMORY MODULE INCLUDING PARALLEL TEST APPARATUS - A memory module including a plurality of ranks. Each of the ranks includes a parallel test apparatus for simultaneous testing and a parallel test control unit. In response to a parallel test mode control signal, the parallel test apparatus generates first parity data for write data including a plurality of bits and generating first data obtained by replacing a bit value of at least one bit of the plurality of bits of the write data with the first parity data during a write operation, and generates second parity data for the first data and transmitting the second parity data as read data during a read operation. The parallel test control unit controls the write operation and the read operation in a parallel test mode by generating the parallel test mode control signal. Combinations of read data from the plurality of ranks correspond to different bits of the write data. | 12-22-2011 |