Patent application number | Description | Published |
20110204393 | LED LAMP - An LED lamp (A | 08-25-2011 |
20110216536 | ILLUMINATION DEVICE - An illumination device that includes a plurality of LED chips and a heat-dissipating unit including a fan configured to ventilate air. The plurality of LED chips are cooled as heat generated in the plurality of LED chips is transferred to the air ventilated by the fan. | 09-08-2011 |
20120182734 | LED ILLUMINATION UNIT, LED ILLUMINATION DEVICE, AND LED ILLUMINATION SYSTEM - The present invention provides an LED (Light Emitting Diode) illumination unit, an LED illumination device, and an LED illumination system with better visual effect. The LED illumination unit includes: a substrate, having a carrying surface with an x direction as a length direction and a y direction as a width direction and facing a z direction; a plurality of LED chips, supported by the carrying surface of the substrate; a casing, allowing the light emitted from the LED chips to penetrate and covering the LED chips; and a heat dissipation component, having a pair of outside surfaces being planar, and mounted with the substrate and the casing, wherein the pair of outside surfaces is configured opposite and parallel to each other in the y direction at an interval, and is longer than the substrate in the x direction. | 07-19-2012 |
20130293118 | LIGHTING DEVICE AND LIGHTING SYSTEM - This lighting device comprises a light-emitting unit, a reception unit for receiving information from an adjacent lighting device, and a control unit for letting the light-emitting unit emit light according to the information received by the reception unit. | 11-07-2013 |
Patent application number | Description | Published |
20080270658 | PROCESSOR SYSTEM, BUS CONTROLLING METHOD, AND SEMICONDUCTOR DEVICE - Provided is a simply structured multiprocessor system which equally distributes access performance for accessing a shared memory among plural master units accessing the shared memory. The multiprocessor system includes plural master units PU | 10-30-2008 |
20090077318 | CACHE MEMORY - A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made. | 03-19-2009 |
20090094474 | INFORMATION PROCESSING DEVICE - An information processing device controls an access unit which accesses a memory corresponding to an address space where an address belongs, the address being generated using at least two pieces of address generation source information. The information processing device includes: a prediction unit which predicts one or more address spaces where the address to be accessed may potentially belong, using one piece of the address generation source information; an activation unit which activates accesses from the access unit to memories corresponding to all the address spaces predicted by the prediction unit; a determination unit which determines the address space where the address to be accessed belongs, the address being generated using the at least two pieces of the address generation source information; and an access stop unit which stops the accesses from the access unit, except for the access corresponding to the address space determined by the determination unit, out of the accesses activated under control of the activation unit. | 04-09-2009 |
20090100231 | CACHE MEMORY SYSTEM, AND CONTROL METHOD THEREFOR - A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory. | 04-16-2009 |
Patent application number | Description | Published |
20080203533 | SEMICONDUCTOR DEVICE - A semiconductor device includes a principal IGBT controllable in accordance with a gate voltage applied to a gate electrode thereof, a current detecting IGBT connected to the principal IGBT in parallel and a current detecting part including a detecting resistor capable of detecting a current passing through the current detecting IGBT. The base region of the current detecting IGBT and the emitter region of the principal IGBT are electrically connected to each other, and the emitter region of the current detecting IGBT and the emitter region of the principal IGBT are electrically connected to each other through the detecting resistor. | 08-28-2008 |
20090085060 | SEMICONDUCTOR DEVICE - In a high-voltage semiconductor switching element, in addition to a first emitter region that is necessary for switching operations, a second emitter region, which is electrically connected with the first emitter region through a detection resistor in current detection means and is electrically connected with the current detection means, is formed. No emitter electrode is formed on the second emitter region, while an emitter electrode is formed on a part of a base region that is adjacent to the second emitter region. | 04-02-2009 |
20110006340 | SEMICONDUCTOR DEVICE - In a high-voltage semiconductor switching element, in addition to a first emitter region that is necessary for switching operations, a second emitter region, which is electrically connected with the first emitter region through a detection resistor in current detection means and is electrically connected with the current detection means, is formed. No emitter electrode is formed on the second emitter region, while an emitter electrode is formed on a part of a base region that is adjacent to the second emitter region. | 01-13-2011 |
Patent application number | Description | Published |
20090206366 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed is a semiconductor device including: an N-type RESURF region formed in a P-type semiconductor substrate; a P-type base region formed in an upper portion of the semiconductor substrate so as to be adjacent to the RESURF region; an N-type emitter/source region formed in the base region so as to be apart from the RESURF region; a P-type base connection region formed in the base region so as to be adjacent to the emitter/source region; a gate insulating film and a gate electrode overlying the emitter/source region, the base region, and the RESURF region; and a P-type collector region formed in the RESURF region so as to be apart from the base region. Lattice defect is generated in the semiconductor substrate such that a resistance value of the semiconductor substrate is twice or more the resistance value of the semiconductor substrate that depends on the concentration of an impurity implanted in the semiconductor substrate. | 08-20-2009 |
20090257249 | SEMICONDUCTOR DEVICE, AND ENERGY TRANSMISSION DEVICE USING THE SAME - An energy transmission device includes: a semiconductor device formed on a first semiconductor substrate; a semiconductor integrated circuit including a reverse current preventing diode and a control circuit; a DC voltage source; and a transformer. The reverse current preventing diode includes a reverse current preventing layer of a second conductivity type formed at a surface of a second semiconductor substrate, and a well layer of a first conductivity type formed in the second semiconductor substrate and covering the reverse current preventing layer. The transformer includes a primary winding connected in series with the semiconductor device and the DC voltage source, and a first secondary winding connected to a load. The energy transmission device is configured so that electric power is supplied from the first secondary winding of the transformer to the load. A second drain electrode of the semiconductor device is electrically connected to the reverse current preventing layer. | 10-15-2009 |
20090262559 | SEMICONDUCTOR DEVICE, AND ENERGY TRANSMISSION DEVICE USING THE SAME - A semiconductor device includes: a high breakdown voltage semiconductor element including a switching element and a JFET element; and a sense element. The sense element includes a first drift region of a first conductivity type, a first base region of a second conductivity type, a first source region of a first conductivity type, a first gate insulating film, a first drain region of a first conductivity type, a sense electrode electrically connected to the first source region, a first gate electrode, and a first drain electrode electrically connected to the first drain region. The first gate electrode of the sense element and the second gate electrode of the switching element are connected to each other. The first drain electrode of the sense element and the electrode shared by the switching element and the JFET element are connected to each other. | 10-22-2009 |
20100001315 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first diffusion region of a second conductivity type formed in an upper portion of a semiconductor substrate of a first conductivity type, a second diffusion region formed in a surface portion of the first diffusion region, a third diffusion region of the second conductivity type formed a predetermined distance spaced apart from the second diffusion region in the surface portion of the semiconductor substrate, a fourth diffusion region of the first conductivity type formed adjacent to the third diffusion region and electrically connected to the third diffusion region, a gate electrode formed on a part between the first diffusion region and the third diffusion region, and an insulating film formed thereon. The impurity concentration of the first diffusion region is set higher than an impurity concentration at which a depletion region extending from an junction interface between the first diffusion region and the semiconductor substrate is formed in a part of the first diffusion region which is between the second diffusion region and the gate electrode when a voltage is applied to the second diffusion region. | 01-07-2010 |
20100301820 | HIGH WITHSTAND VOLTAGE SEMICONDUCTOR DEVICE AND CURRENT CONTROL DEVICE USING THE SAME - To provide a high withstand voltage semiconductor device capable of accurately detecting a switch between a MOS operation and an IGBT operation, and thereby achieving a low-loss drive, and a current control device using the same. The semiconductor device includes: an N-type resurf region | 12-02-2010 |