Kim, Ichon
Bo Kyeom Kim, Ichon KR
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20090019344 | APPARATUS AND METHOD FOR GENERATING ERROR DETECTION CODES - An apparatus for generating error detection codes can include an error detection code generation unit configured to generate virtual error detection codes using virtual DBI information and data, and an error detection code regeneration unit configured to generate error detection codes using even and odd number information which define whether the number of data associated with the generation of the error detection codes is even or odd, DBI information associated with the even and odd number information, and the virtual error detection codes. | 01-15-2009 |
Chang Ii Kim, Ichon KR
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20100271890 | DATA I/O CONTROL SIGNAL GENERATING CIRCUIT IN A SEMICONDUCTOR MEMORY APPARATUS - A circuit for generating a data I/O control signal used in a semiconductor memory apparatus comprises a delay block for generating a delay signal having a relatively short delay value and a delay signal having a relatively long delay values, and a selection block for selecting any one of the delay signals according to an operational mode. The selection block selects an output signal of the first delay unit in a high-speed operation mode and selects an output signal of the second delay unit in a low-speed operation mode. | 10-28-2010 |
Dong-Hwee Kim, Ichon KR
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20090091376 | INTERNAL VOLTAGE GENERATING CIRCUIT - Disclosed is an internal voltage generating circuit that pumps charge to generate an internal driving voltage. The internal voltage generating circuit includes: a first oscillation signal generating unit that provides a first oscillation signal in response to a detected internal voltage and a predetermined test mode signal; a second oscillation signal generating unit that divides an external clock to provide a second oscillation signal having a variable oscillation period; and a switching unit that selects the first oscillation signal or the second oscillation signal in response to the predetermined test mode signal and provides the selected signal as a pumping period signal. | 04-09-2009 |
Gyung Tae Kim, Ichon KR
Jee Yul Kim, Ichon KR
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20080279021 | MULTI-WORDLINE TEST CONTROL CIRCUIT AND CONTROLLING METHOD THEREOF - A multi-wordline test control circuit in a semiconductor integrated device for performing a multi-wordline test in a specified cell mat among a plurality of cell mats. The multi-wordline test control circuit comprises a multi-test control block for receiving a multi-wordline test signal and outputting a first test signal and a second test signal, and a multi-wordline test block for performing the multi-wordline test in a specified cell mat among a plurality of cell mats in response to the first test signal and the second test signal. | 11-13-2008 |
20090091348 | CIRCUIT FOR TESTING INTERNAL VOLTAGE OF SEMICONDUCTOR MEMORY APPARATUS - An internal voltage test circuit of a semiconductor memory apparatus includes a comparing unit for comparing a level of internal voltage with a level of external voltage to output a comparison result as an output signal during a test mode, and an output selecting unit for outputting the output signal to a data output pad during the test mode, and outputting a data signal to the data output pad during a normal operation mode. | 04-09-2009 |
20100090750 | TRIMMING CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND TRIMMING METHOD THEREOF - A trimming circuit for a semiconductor memory apparatus includes a trimming code generator configured to provide a trimming code signal group by performing one of addition and subtraction using a test mode signal and a fuse coding signal, and an internal voltage generator configured to provide trimmed voltage in response to the trimming code signal group as output voltage. | 04-15-2010 |
Jong Sam Kim, Ichon KR
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20090179654 | TEST APPARATUS OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD USING THE SAME - A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse signals according to a fuse cutting after a termination of the test time, a combination signal generating unit for storing a test signal and inactivating a combination signal when the test mode signal is inactivate and for outputting the stored test signal as the combination signal when the test mode signal is activate, and a code signal generating unit for activating a test code signal when one of the test fuse signal and the combination signal is activated. | 07-16-2009 |
20090231022 | PUMPING VOLTAGE GENERATING CIRCUIT - A pumping voltage generating circuit of a semiconductor memory apparatus, the pumping voltage generating circuit includes a detecting unit configured to compare a level of a pumping voltage with a level of a reference voltage to generate a detection signal, an oscillating signal generator configured to sequentially generate a first oscillating signal and a second oscillating signal in response to the detection signal, and to elevate frequencies of the first and second oscillating signals when the second oscillating signal is generated, a first pump configured to perform a pumping operation in response to the first oscillating signal, and a second pump configured to perform a pumping operation in response to the second oscillating signal, wherein output terminals of the first pump and the second pump are commonly connected, and the pumping voltage is output at the output terminals of the first pump and the second pump. | 09-17-2009 |
20110050271 | TEST APPARATUS OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD USING THE SAME - A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse signals according to a fuse cutting after a termination of the test time, a combination signal generating unit for storing a test signal and inactivating a combination signal when the test mode signal is inactivate and for outputting the stored test signal as the combination signal when the test mode signal is activate, and a code signal generating unit for activating a test code signal when one of the test fuse signal and the combination signal is activated. | 03-03-2011 |
Jong-Su Kim, Ichon KR
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20090152613 | SEMICONDUCTOR MEMORY DEVICE HAVING A FLOATING BODY CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device having a floating body capacitor. The semiconductor memory device can perform a memory operation using the floating body capacitor. The semiconductor memory device includes an SOI substrate having a staked structure in which a base substrate having a conducting surface, a buried insulating layer and a device-forming layer are staked, a transistor formed in a portion of the device-forming layer, having a gate, a source region and a drain region, and a capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes generated in the device-forming layer when the transistor is driven. | 06-18-2009 |
Keun Kook Kim, Ichon KR
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20090045849 | DATA BUS SENSE AMPLIFIER CIRCUIT - A data bus sense amplifier circuit can include a first sense amplifier block configured to provide first amplified signals by sensing inputted signals, a second sense amplifier block configured to provide second amplified signals by sensing the first amplified signals, and a sense amplifier control unit configured to provide first and second enable signals which control activations of the first and second sense amplifier blocks, respectively, wherein the sense amplifier control unit controls the first enable signal to be synchronized with the second enable signal so that the first enable signal is inactivated. | 02-19-2009 |
20090059709 | ADDRESS REPLACING CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME - An address replacing circuit includes a sub-bank region selecting unit that allows a first sub-bank region or a second sub-bank region to be selectively activated, in response to a row address and first and second bits of a column address in accordance with operation modes a first column region activating unit that generates a first column region activating address and a second column region activating address from the first bit of the column address, a second column region activating unit that generates a third column region activating address and a fourth column region activating address from the second bit of the column address, and a column region selecting unit that allows at least one of first to fourth column regions of the first sub-bank region and first to fourth column regions of the second sub-bank region to be selectively activated, in response to the first to fourth column region activating addresses. | 03-05-2009 |
Ki Tae Kim, Ichon KR
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20090316493 | SEMICONDUCTOR INTEGRATED CIRCUIT FOR GENERATING CLOCK SIGNALS - A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write clock control signal at a deactivation state in response to one of an idle mode and a refresh operational mode, and a clock buffer that generates a read clock signal and a write clock signal in response to a clock signal, the read clock control signal, and the write clock control signal. | 12-24-2009 |
20110286285 | SEMICONDUCTOR INTEGRATED CIRCUIT FOR GENERATING CLOCK SIGNALS - A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write clock control signal at a deactivation state in response to one of an idle mode and a refresh operational mode, and a clock buffer that generates a read clock signal and a write clock signal in response to a clock signal, the read clock control signal, and the write clock control signal. | 11-24-2011 |
20110286286 | SEMICONDUCTOR INTEGRATED CIRCUIT FOR GENERATING CLOCK SIGNALS - A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write clock control signal at a deactivation state in response to one of an idle mode and a refresh operational mode, and a clock buffer that generates a read clock signal and a write clock signal in response to a clock signal, the read clock control signal, and the write clock control signal. | 11-24-2011 |
Kwan Dong Kim, Ichon KR
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20100062720 | SIGNAL TRANSMISSION SYSTEM AND SIGNAL TRANSMISSION METHOD THEREOF - A signal transmission system includes a transmitting unit configured to drive an input signal and to transmit the input signal, a pre-emphasis unit configured to detect a change in a voltage level of the input signal and to amplify a voltage of an output signal of the transmitting unit for a predetermined time, and a receiving unit configured to receive the output signal from the transmitting unit. | 03-11-2010 |
Kwang Hyun Kim, Ichon KR
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20080285364 | DATA INPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND DATA INPUT METHOD USING THE SAME - A data input circuit of a semiconductor memory apparatus includes a plurality of data input sense amplifiers, each of which amplifies input data in response to a data input strobe signal and generates amplified data, and a data selecting block that selectively outputs a plurality of amplified data in response to starting addresses. | 11-20-2008 |
Kyung Whan Kim, Ichon KR
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20090231930 | INTERNAL VOLTAGE GENERATING CIRCUIT HAVING SELECTIVELY DRIVEN DRIVERS IN SEMICONDUCTOR MEMORY APPARATUS - An internal voltage generating circuit of a semiconductor memory apparatus includes a first voltage generating unit to output a first output voltage to a common node, the first output voltage is generated in response to a first reference voltage, and a second voltage generating unit to output a second output voltage to the common node, the second output voltage is generated in response to a second reference voltage. | 09-17-2009 |
Myung-Jin Kim, Ichon KR
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20090091376 | INTERNAL VOLTAGE GENERATING CIRCUIT - Disclosed is an internal voltage generating circuit that pumps charge to generate an internal driving voltage. The internal voltage generating circuit includes: a first oscillation signal generating unit that provides a first oscillation signal in response to a detected internal voltage and a predetermined test mode signal; a second oscillation signal generating unit that divides an external clock to provide a second oscillation signal having a variable oscillation period; and a switching unit that selects the first oscillation signal or the second oscillation signal in response to the predetermined test mode signal and provides the selected signal as a pumping period signal. | 04-09-2009 |
Seung Bong Kim, Ichon KR
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20090039932 | DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A delay circuit of a semiconductor memory apparatus can include a clock period sensing unit for generating a sensing signal in response to a clock frequency, and a selective delay unit for delaying an input signal for a delay time and then output the input signal as an output signal, wherein the delay time can be one selected from a plurality of delay times according to the sensing signal. The delay time can be selectively determined according to a clock frequency used in a semiconductor memory apparatus. | 02-12-2009 |
20090303818 | TEST CIRCUIT DEVICE FOR SEMICONDUCTOR MEMORY APPARATUS - A test circuit device for a semiconductor memory device includes a main word line driving unit that generates a signal that swings between a driving voltage and one of a first voltage and a second voltage in response to a main decoding signal and a test mode signal, a local driving unit that generates a signal that swings between the driving voltage and one of the first voltage and the second voltage in response to a local decoding signal and the test mode signal, a driving voltage supplying unit that receives an output of the local driving unit and the test mode signal to supply a voltage that swings between the driving voltage and the first voltage, and a sub-word line driver that receives an output of the main word line driving unit and an output of the driving voltage supplying unit to determine whether the sub-word line is enabled or not. | 12-10-2009 |
Taek Seung Kim, Ichon KR
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20090185436 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING WRITE CONTROLLING CIRCUIT - A semiconductor integrated circuit includes a write controlling circuit configured to selectively provide a fixed pulse or a variable pulse according to a level of a test mode signal in a write operation mode, thereby adjusting a pulse width of an internal write pulse that is a current pulse driving an internal memory cell in response to the fixed pulse or the variable pulse. | 07-23-2009 |
20090231901 | SEMICONDUCTOR INTEGRATED CIRCUIT FOR SUPPORTING A TEST MODE - A semiconductor integrated circuit for supporting a test mode includes a program region including at least one One Time Programmable Cell Array, and a program region control unit configured to activate the program region in response to an enabled fuse signal of a fuse corresponding to the program region, and to activate the program region in response to a test mode signal of the program region. | 09-17-2009 |
Yeon Uk Kim, Ichon KR
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20100019810 | CIRCUIT FOR GENERATING NEGATIVE VOLTAGE AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A circuit for generating negative voltage of a semiconductor memory apparatus includes a first detecting unit configured to generate a first detecting signal by detecting a first negative voltage level, a first negative voltage generating unit configured to generate the first negative voltage in response to the first detecting signal, a second detecting unit configured to generate a second detecting signal by detecting the second negative voltage level, a timing controlling unit configured to output the second detecting signal as an enable signal when a power up signal is enabled and the first detecting signal is disabled, and a second negative voltage generating unit configured to generate the second negative voltage in response to the enable signal. | 01-28-2010 |
Yong Hoon Kim, Ichon KR
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20090256598 | POWER-UP SIGNAL GENERATOR OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR CONTROLLING THE SAME - A power-up signal generator of a semiconductor memory apparatus includes a power-up signal generating unit that includes a MOS transistor having a gate receiving a divided voltage of an external supply voltage, the power-up signal generating unit determining a level of a power-up signal according to a turn-ON state of the MOS transistor, and a bulk bias voltage generating unit that applies a bulk bias voltage to a bulk of the MOS transistor to adjust a threshold voltage of the MOS transistor, wherein the bulk bias voltage varies according to a temperature of the semiconductor memory device. | 10-15-2009 |
Yong Mi Kim, Ichon KR
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20090091363 | DLL CIRCUIT - A DLL circuit including a first clock signal dividing block configured to selectively divide a frequency of a reference clock signal according to whether a lock completion signal is enabled, a phase comparing block configured to generate a phase comparison signal by comparing phases of a clock signal transmitted from the first clock signal dividing block with a feedback clock signal, and an operation mode setting block configured to generate the lock completion signal in response to the phase comparison signal is described herein. | 04-09-2009 |
Youk Hee Kim, Ichon KR
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20090002029 | TEST CONTROL CIRCUIT AND REFERENCE VOLTAGE GENERATING CIRCUIT HAVING THE SAME - A test control circuit according to an embodiment of the invention includes a test mode control unit that outputs a control signal according to a voltage trimming test signal, a decoding portion that receives the control signal and outputs a decoding signal, and a trimming signal adjusting portion that receives the decoding signal and outputs a trimming signal adjusted by a low level test signal. | 01-01-2009 |
20090046525 | WAFER BURN-IN TEST CIRCUIT - A wafer burn-in test circuit includes an address toggle signal generating unit for generating an address toggle signal in response to address signals having a constant time period, a reset signal generating unit for receiving a wafer burn-in mode activation signal, the address signals, and a reset determination signal among the address signals and then generating a reset signal, a refresh test mode signal generating unit for receiving the address toggle signal and the reset signal and then generating a refresh test mode signal, and a refresh period signal generating unit for receiving the address toggle signal and the refresh test mode signal and then generating a refresh period signal. | 02-19-2009 |