Patent application number | Description | Published |
20080225380 | Delay line interferometer having a movable mirror - An optical receiver apparatus and methods for mitigating intersymbol interference (ISI) in a differentially-encoded modulation transmission system by controlling constructive and destructive transfer functions. The receiver includes a bandwidth control element for controlling transfer function bandwidth, a transfer phase controller for controlling transfer function phase and/or an imbalancer for imbalancing the transfer functions for compensating for intersymbol interference and optimizing the quality of the received optical signal. | 09-18-2008 |
20080225381 | Delay line interferometer having a stepped delay element - An optical receiver apparatus and methods for mitigating intersymbol interference (ISI) in a differentially-encoded modulation transmission system by controlling constructive and destructive transfer functions. The receiver includes a bandwidth control element for controlling transfer function bandwidth, a transfer phase controller for controlling transfer function phase and/or an imbalancer for imbalancing the transfer functions for compensating for intersymbol interference and optimizing the quality of the received optical signal. | 09-18-2008 |
20080226306 | GT decoder having bandwidth control for ISI compensation - An optical receiver apparatus and methods for mitigating intersymbol interference (ISI) in a differentially-encoded modulation transmission system by controlling constructive and destructive transfer functions. The receiver includes a bandwidth control element for controlling transfer function bandwidth, a transfer phase controller for controlling transfer function phase and/or an imbalancer for imbalancing the transfer functions for compensating for intersymbol interference and optimizing the quality of the received optical signal. | 09-18-2008 |
20080231941 | Optical receiver having FSR phase compensation - An optical receiver apparatus and methods for mitigating intersymbol interference (ISI) in a differentially-encoded modulation transmission system by controlling constructive and destructive transfer functions. The receiver includes a bandwidth control element for controlling transfer function bandwidth, a transfer phase controller for controlling transfer function phase and/or an imbalancer for imbalancing the transfer functions for compensating for intersymbol interference and optimizing the quality of the received optical signal. | 09-25-2008 |
20080232821 | Optical receiver having transfer function bandwidth selection - An optical receiver apparatus and methods for mitigating intersymbol interference (ISI) in a differentially-encoded modulation transmission system by controlling constructive and destructive transfer functions. The receiver includes a bandwidth control element for controlling transfer function bandwidth, a transfer phase controller for controlling transfer function phase and/or an imbalancer for imbalancing the transfer functions for compensating for intersymbol interference and optimizing the quality of the received optical signal. | 09-25-2008 |
20090116851 | Optical Receiver Having Bandwidth Control For Intersymbol Interference Compensation - Apparatus and techniques for receiving and processing an optical signal. In one implementation, an optical receiver is provided to include a delay line interferometer, an etalon, and a data estimator for estimating the data carried on a differentially modulated optical input signal. The delay line interferometer receives the input signal and issues differentially decoded constructive and destructive signals. The etalon filters the constructive signal with a transmission stopband imposed over the passband of the constructive signal. The bandwidth of the etalon stopband is selected based on the bandwidth of the modulation of the input signal in order to maximize received signal quality. The data estimator uses a difference between signals derived from the filtered constructive signal and the destructive signal for estimating data. | 05-07-2009 |
20100284702 | Optical Receivers with Controllable Transfer Function Bandwidth and Gain Imbalance - Techniques, devices and systems based on optical receivers with controllable transfer function bandwidth and gain imbalance. | 11-11-2010 |
Patent application number | Description | Published |
20080296042 | Profiled insulation and method for making the same - A wire has a conductor and an insulation extruded onto the conductor. The insulation has a plurality of alternating crests and crevasses, where the ratio of the distance from the conductor to a top of the crest to the distance from the conductor to a lowest point in the adjacent crevasse is at least 1.1 and where the ratio is sustained within a tolerance variation of not more than 15% along the length of the wire. | 12-04-2008 |
20090018225 | High processing tepmerature foaming polymer composition - A foaming composition includes a polymer having a melting temperature above 250° C., and an organic salt as chemical foaming agent having a decomposition temperature above the melting point of the polymer, where the organic salt is selected from the group of citrate derivatives and tartrate derivatives, or a mixture thereof. | 01-15-2009 |
20100276178 | PROFILED INSULATION AND METHOD FOR MAKING THE SAME - A wire, having a conductor and an insulation, extruded onto the conductor. The insulation has a plurality of alternating plateaus and valleys thrilling a profile along the outer circumference, where a circumference ratio of an outer circumference of the insulation at the full thickness of the plateaus relative to the portion of the outer circumference of the insulation that is at the reduced thickness of valleys is substantially 1.5 or greater. | 11-04-2010 |
20130126209 | FORWARD TWISTED PROFILED INSULATION FOR LAN CABLES - The present arrangement provides a twisted pair of conductors, each with a profiled insulation thereon, where in the twisted pair, the peak to peak contact of adjacent conductor insulation is ensured along the length of the pair. To this end, each of the profiled insulations on the conductors of the pair are forward twisted prior to twinning to ensure the maximum number of peak to peak contacts per unit length of the pair. | 05-23-2013 |
20140000935 | PROFILE FILLER TUBES IN LAN CABLES | 01-02-2014 |
Patent application number | Description | Published |
20150223416 | Automated Control System - Aspects of the disclosure relate to a method that may include receiving a watering restriction for a location, detecting that a sprinkler controller is associated with a property within the location, and transmitting, to the sprinkler controller, the watering restriction. Additionally, a method may include receiving, at a sprinkler controller, a watering restriction for a location, the sprinkler controller associated with a property within the location, and adjusting, in response to the watering restriction, a sprinkling schedule for the property. Furthermore, a method may include receiving weather prediction information associated with a property, updating, in response to the weather prediction information, a sprinkling schedule for a sprinkler system associated with the property, receiving, after a time period, updated weather prediction information for the property, and updating the sprinkling schedule based on a comparison between the sprinkling schedule and the weather prediction information over the time period. | 08-13-2015 |
Patent application number | Description | Published |
20080227302 | FIBROUS LAMINATE INTERFACE FOR SECURITY COATINGS - an integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and connections. The bond coat layer is configured to encapsulate the IC components. The top coat layer has at least a portion embedded in the bond coat layer. Moreover, the top coat layer includes a fibrous interface configured to provide security and strengthen the bond coat layer. | 09-18-2008 |
20100254095 | MICROELECTRONIC SECURITY COATINGS - A security coating on an electronic circuit assembly comprises a mesh coating that may have a unique signature pattern and comprise materials that easily produce an image of the signature so that it is possible to determine if reverse engineering has been attempted. Spaces in the mesh may include electrical components to erase circuit codes to destroy the functionality and value of the protected die if the mesh coated is disturbed. The voids may include compositions to enhance the mesh signature and abrade the circuit if tampering takes place. | 10-07-2010 |
20130235544 | INTEGRATED CIRCUIT STACK - In some examples, an integrated circuit system includes a plurality of integrated circuit layers. At least one of the integrated circuit layers includes an integrated circuit die, which may not include any through-silicon vias that provide a pathway to an adjacent integrated circuit layer, and an interposer portion, which includes electrically conductive through-vias. The interposer portion may facilitate communication of the integrated circuit die with other integrated circuit layers of the integrated circuit system. In some examples, the stacked integrated circuit system may include more than one integrated circuit die, which may be in the same integrated circuit layer as at least one other integrated circuit die, or may be in a different integrated circuit layer. | 09-12-2013 |
20140293562 | FIBROUS LAMINATE INTERFACE FOR SECURITY COATINGS - An integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and connections. The bond coat layer is configured to encapsulate the IC components. The top coat layer has at least a portion embedded in the bond coat layer. Moreover, the top coat layer includes a fibrous interface configured to provide security and strengthen the bond coat layer. | 10-02-2014 |
20150109061 | SYSTEMS AND METHODS FOR A WAFER SCALE ATOMIC CLOCK - Systems and methods for a wafer scale atomic clock are provided. In at least one embodiment, a wafer scale device comprises a first substrate; a cell layer joined to the first substrate, the cell layer comprising a plurality of hermetically isolated cells, wherein separate measurements are produced for each cell in the plurality of hermetically isolated cells; and a second substrate joined to the cell layer, wherein the first substrate and the second substrate comprise electronics to control the separate measurements, wherein the separate measurements are combined into a single measurement. | 04-23-2015 |
20150156184 | PHYSICS-BASED AUTHENTICATION - In some examples, a controller is configured to generate a key based on a physics-based output of a component. The controller may, for example, use the key to authenticate communication between at least two nodes, to encrypt data, or to decrypt data. In some examples, the component includes one or more subcomponents, each subcomponent including a cell filled with a gas, a light source configured to transmit a light through the gas cell, and a photodetector configured to sense light transmitted through the gas cell. The photodetector of each subcomponent is configured to generate an electrical signal that changes as a function of one or more properties of the light sourced by the light source, transmitted through the gas cell. The output of the component can is based on the signals generate by the one or more photodetectors. | 06-04-2015 |
20150180841 | PHYSICS-BASED KEY GENERATION - In some examples, a controller is configured to generate a key based on a physics-based output of a component. The controller may, for example, use the key to authenticate communication between at least two nodes, to encrypt data, or to decrypt data, may be generated based on a physics-based output generated a component. The output generated by the component may vary over time, such that the controller is configured to generate a different key, depending on the time at which the output from the component used to generate the key was generated by the component. In some examples, the key is not stored in a memory, and is a discrete signal that only exists in real-time while the component is active and generating the detectable output. | 06-25-2015 |