Patent application number | Description | Published |
20080227258 | Methods of forming a semiconductor device - Methods of forming a semiconductor device include forming a mask layer on a semiconductor substrate. The mask layer has vertically and horizontally extending portions. The vertically extending portions have a thickness selected to provide a desired line width to an underlying structure to be formed using the mask layer and a height greater than a height of the horizontally extending portions. The underlying structure is formed using the mask layer. | 09-18-2008 |
20090154240 | NAND FLASH MEMORY DEVICES HAVING WIRING WITH INTEGRALLY-FORMED CONTACT PADS AND DUMMY LINES AND METHODS OF MANUFACTURING THE SAME - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction | 06-18-2009 |
20090159962 | Non-Volatile Memory Devices - Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well. | 06-25-2009 |
20090236651 | SEMICONDUCTOR DEVICES HAVING A CONVEX ACTIVE REGION - Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions. | 09-24-2009 |
20090298276 | METHODS OF FORMING SEMICONDUCTOR DEVICE PATTERNS - A first mask layer pattern including a plurality of parallel line portions is formed on an etch target layer on a semiconductor substrate. A sacrificial layer is formed on the first mask layer pattern and portions of the etch target layer between the parallel line portions of the first mask layer pattern. A second mask layer pattern is formed on the sacrificial layer, the second mask layer pattern including respective parallel lines disposed between respective adjacent ones of the parallel line portions of the first mask layer pattern, wherein adjacent line portions of the first mask layer pattern and the second mask layer pattern are separated by the sacrificial layer. A third mask layer pattern is formed including first and second portions covering respective first and second ends of the line portions of the first mask layer pattern and the second mask layer pattern and having an opening at the line portions of the first and second mask layer patterns between the first and second ends. The sacrificial layer and the etch target layer are etched using the third mask layer pattern, the first mask layer pattern and the second mask layer pattern as a mask to thereby form a plurality of parallel trenches in the etch target layer between the line portions of the first and second mask layer patterns. Conductive lines may be formed in the trenches. | 12-03-2009 |
20100096719 | METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES - A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are isotropically etched to remove the etch mask pattern from the first mask structure while maintaining at least a portion of the etch mask pattern on the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region using the portion of the etch mask pattern on the second mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region. The feature layer may be patterned using the first mask pattern as a mask to define a first feature on the first region, and using the second mask pattern as a mask to define a second feature on the second region having a greater width than the first feature. | 04-22-2010 |
20110032763 | SEMICONDUCTOR DEVICES INCLUDING FIRST AND SECOND BIT LINES - In some embodiments, a semiconductor device includes first bit lines connected to respective first contacts. Spacers are disposed on sidewalls of the first bit lines. A second bit line is self-alignedly disposed between adjacent spacers, and a second contact is self-aligned with and connected to the second bit line. | 02-10-2011 |
20110103147 | NAND FLASH MEMORY DEVICES HAVING WIRING WITH INTEGRALLY-FORMED CONTACT PADS AND DUMMY LINES AND METHODS OF MANUFACTURING THE SAME - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction | 05-05-2011 |
20110198685 | Non-Volatile Memory Devices - Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well. | 08-18-2011 |
20120147674 | Nonvolatile Memory Devices that Utilize Dummy Word Line Segments to Inhibit Dishing During Fabrication - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction | 06-14-2012 |
20120252185 | METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES - A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region. | 10-04-2012 |
20130102151 | METHODS OF MANUFACTURING NAND FLASH MEMORY DEVICES - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction | 04-25-2013 |