Gee, CA
Adam Gee, San Francisco, CA US
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20160124977 | DATA MANAGEMENT SYSTEM - Methods and systems for managing, storing, and serving data within a virtualized environment are described. In some embodiments, a data management system may manage the extraction and storage of virtual machine snapshots, provide near instantaneous restoration of a virtual machine or one or more files located on the virtual machine, and enable secondary workloads to directly use the data management system as a primary storage target to read or modify past versions of data. The data management system may allow a virtual machine snapshot of a virtual machine stored within the system to be directly mounted to enable substantially instantaneous virtual machine recovery of the virtual machine. | 05-05-2016 |
20160127307 | CLUSTER-BASED NETWORK FILE SERVER - Methods and systems for managing, storing, and serving data within a virtualized environment are described. In some embodiments, a data management system may manage the extraction and storage of virtual machine snapshots, provide near instantaneous restoration of a virtual machine or one or more files located on the virtual machine, and enable secondary workloads to directly use the data management system as a primary storage target to read or modify past versions of data. The data management system may allow a virtual machine snapshot of a virtual machine stored within the system to be directly mounted to enable substantially instantaneous virtual machine recovery of the virtual machine. | 05-05-2016 |
Albert Gee, Los Altos, CA US
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20160051233 | SYSTEM AND METHOD FOR PROVIDING VARIABLE ULTRASOUND ARRAY PROCESSING IN A POST-STORAGE MODE - An ultrasonic imaging method includes activating a transmit aperture within a multi-element transducer array, transmitting one or more ultrasonic beams along scan direction(s) that span the region of interest, for each transmit event, receiving ultrasound echoes from each element of a receive aperture, grouping the receive channel echo data into two or more sets corresponding to different receive sub-apertures, combining each sub-aperture data set to generate partially focused echo-location data for one or more reconstruction lines, and storing all the sub-aperture echo data sets during a storage period in a format that can be retrieved for later analysis. A method includes, during a post-storage period, retrieving stored sub-aperture data, combining the sub-aperture data to form one or more selected reconstruction lines, processing echo data to extract motion information from one or more sample positions along the selected reconstruction lines, and displaying an image representative of the processed motion information. | 02-25-2016 |
Casey Gee, Encinitas, CA US
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20140215860 | MAGNETICALLY COUPLEABLE FOOTWEAR - Embodiments disclosed herein are directed towards magnetically coupleable footwear. The footwear can include a first footwear piece having a first sole, the first sole having a bottom surface and at least one magnet disposed in the first sole, and a second footwear piece having a second sole, the second sole having a bottom surface and at least one complementary magnet disposed in the second sole, wherein the at least one magnet and the at least one complementary magnet are oriented so as to attract each other when the bottom surface of the first sole is facing the bottom surface of the second sole. | 08-07-2014 |
Corey Gee, Fremont, CA US
Patent application number | Description | Published |
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20130290684 | DATA PACKET ARITHMETIC LOGIC DEVICES AND MEHTODS - New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed. | 10-31-2013 |
20150134936 | SINGLE INSTRUCTION MULTIPLE DATA ADD PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS - New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed. | 05-14-2015 |
Dale Alan Gee, Los Gatos, CA US
Patent application number | Description | Published |
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20130133432 | PRESSURE SENSOR ASSEMBLY - A pressure sensor assembly is disclosed wherein the substrate to which the pressure sensing die is mounted is decoupled from the package. | 05-30-2013 |
20140000375 | PRESSURE SENSOR ASSEMBLY | 01-02-2014 |
Daniel D. Gee, Manhattan Beach, CA US
Patent application number | Description | Published |
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20100277372 | SYSTEM AND METHOD FOR OPERATING A RADAR SYSTEM IN A CONTINUOUS WAVE MODE FOR DATA COMMUNICATION - A system and a method for operating a radar system in a continuous wave mode for communicating information are provided. In one embodiment, the invention relates to a method for operating a radar system, having an antenna including a plurality of active array elements, in a continuous wave mode to communicate information, the method including receiving an instruction to enter the continuous wave mode, loading a plurality of tables, where each table includes information indicative of a primary group of the active array elements to be activated and a secondary group of elements to be deactivated, receiving a communication signal to be transmitted, and providing, repeatedly, the communication signal, for a preselected period of time, to the primary group of elements of each of the plurality of tables. | 11-04-2010 |
David A. Gee, Los Angeles, CA US
Patent application number | Description | Published |
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20100088239 | Collaborative Negotiation Methods, Systems, and Apparatuses for Extended Commerce - A round of negotiation for an item is initiated between a plurality of bidders at a plurality of client nodes and a host processing node. A price bid for the item is received from each of the plurality of bidders. At least one negotiation parameter is received from at least one of the plurality of bidders. The negotiation parameter is associated with the item. A total cost value is determined based on an active negotiation term, the price bid, and the negotiation parameter for each of the plurality of bidders. | 04-08-2010 |
Esmond Gee, Loma Linda, CA US
Patent application number | Description | Published |
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20080203803 | Lumber Distraction Chair - Lumbar distraction is an effective treatment for back pain. However the discomfort and morbidities associated with vertical inversion has limited its use. The Lumbar Distraction Chair delivers a gentler lumbar distraction without the discomfort of being suspended vertically. The device is a modified office swivel chair with inward folding arm rests that secure the patient's legs on the chair seat. The patient positions him/herself onto the device with their back lying on the floor with hips and knees flexed. The arm rests of the chair fold inwards and hold the patient's legs securely onto the seat. A pneumatic telescopic stand elevates the seat, which also lifts the patient's legs hips and lower back off the ground by several centimeters. This provides lumbar distraction to the lower back. In this position, pain and inflammation is alleviated. This permits the muscle cell relaxation, recuperation and repair. | 08-28-2008 |
Glen Gee, Yorba Linda, CA US
Patent application number | Description | Published |
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20130104890 | ANALYZING MEDICAL DEVICE DATA | 05-02-2013 |
20130104891 | SUGGESTING VENTILATOR PROTOCOLS | 05-02-2013 |
20130104892 | VENTILATION HARM INDEX | 05-02-2013 |
20130110529 | VENTILATOR AVOIDANCE REPORT | 05-02-2013 |
20130110530 | VENTILATOR REPORT GENERATION | 05-02-2013 |
Glenn P. Gee, San Jose, CA US
Patent application number | Description | Published |
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20080259492 | Lapping plate texture for increased control over actual lapping force - A slider lapping texture for implementation in a lapping environment. The slider lapping texture includes a lapping texture structure for utilization in a lapping process performed on a slider. The structure also includes a first surface having a base elevation. The structure further includes a second surface at an elevation higher than the base elevation. The second surface is for lapping the slider. The structure additionally includes an opening for expelling residue associated with a lapping process. The slider lapping texture is configured to generate an attractive force when the slider is motioned thereupon in a substantially unidirectional manner. | 10-23-2008 |
20080273265 | Determining smear of a hard disk drive slider - A disk drive head slider for a magnetic disk drive is provided. The head slider includes a tunnel magnetic resistance device for reading data on a magnetic disk and a dedicated sensor for measuring resistance wherein the resistance corresponds to a level of smear associated with the head slider. | 11-06-2008 |
20090211081 | CONTROLLED LAPPING FOR AN ABS DAMASCENE PROCESS - Methods of lapping rows of recording heads are described after an air bearing surface (ABS) damascene process is performed. The ABS damascene process uses a selective etching process to form voids in the row of recording heads where conductive material forms a feature in the recording head, such as a wrap around shield. The conductive material is then deposited on the ABS of the row to fill the voids, and the row is lapped. According to methods provided herein, the resistance of one or more lapping guides in the row of recording heads is monitored to determine when the conductive material is removed by the lapping process. When the monitored resistance indicates that the conductive material is removed, the lapping process is stopped. The resistance across one or more lapping guides may also be used to control the lapping process to uniformly lap the conductive material from the ABS. | 08-27-2009 |
20140154952 | WAFER GROUNDING DESIGN FOR SINGLE PAD LAPPING - Embodiments described herein generally relate to connecting Electronic Lapping Guides (ELG) to a lapping controller to reduce resistance from current crowding while reducing connections to the ELG. A device and a system can include a wafer with peripheral grounding vias having a radius of at least 10 μm, a plurality of sliders with a magnetoresistive (MR) elements; a plurality of ELG electrically coupled to the lapping controller through a combination of the wafer and grounding pads and a bonding pad electrically coupled to the ELG. The ELG or the bonding pad can be positioned in the kerf or the device region of a row. If the ELG and the bonding pad are positioned in separate regions, a noble metal should be used to connect. Further, the number of grounding pads can be reduced by using grounding vias at specific intervals and specific sizes. | 06-05-2014 |
20140154953 | CORRECTING CURRENT CROWDING IN ROW BAR AND VIAS FOR SINGLE PAD BONDING - Embodiments described herein generally relate to connecting electronic lapping guides (ELGs) to a lapping controller to prevent the effects of current crowding while reducing connections to the ELGs in single pad lapping. Devices and systems can include a row of sliders including a magnetoresistive (MR) element, a plurality of high resistance ELGs connected to both the wafer and to at least one bonding pad and at least two peripheral grounding vias connected to the wafer. Methods and systems include a wafer comprising a plurality of sliders wherein each slider is connected to a lapping controller and the delivery of current to the ELGs is sequential to groups of sliders such that only one group of ELGs is being measured at any time. | 06-05-2014 |
Glenn Paul Gee, San Jose, CA US
Patent application number | Description | Published |
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20090130957 | SYSTEM, METHOD AND APPARATUS FOR LAPPING WORKPIECES WITH SOLUBLE ABRASIVES - A soluble abrasive is used to lap workpieces to overcome the problem of embedding and retaining abrasive particles in the workpieces. The soluble abrasives are dissolved from the workpiece even if they become embedded in the workpiece. For example, the abrasives may be dissolved with water and comprise ionic salts. The soluble abrasive has a hardness that is equal to or slightly greater than the hardness of the metal being lapped. | 05-21-2009 |
Glen P. Gee, San Jose, CA US
Patent application number | Description | Published |
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20140154951 | COMMON GROUND FOR ELECTRONIC LAPPING GUIDES - Embodiments described herein generally relate to connecting Electronic Lapping Guides (ELG) to a lapping controller such that the number of wire bonds from the controller to a row of read heads is minimized. When lapping the air bearing surface of the read heads, the electrical resistances of the ELGs are monitored to adjust the lapping process and set the stripe height for read sensors in the read heads. Once the resistance corresponds to the desired stripe height, the lapping process is stopped. To measure the resistance, each ELG may be electrically coupled to the same substrate—i.e., share the same common ground. The lapping controller applies a voltage potential across the ELGs using a wire bonded to a pad in the respective read head and one or more connections to the grounded substrate. This configuration avoids having to bond two wires onto each read head. | 06-05-2014 |
Harold H. Gee, San Jose, CA US
Patent application number | Description | Published |
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20120300327 | SYSTEM AND METHOD FOR IMPROVING HEAD POSITIONING - Systems and methods for improving accuracy of head positioning using existing servo patterns are provided. In one embodiment, a method for improving read head positioning is provided that comprises: writing a series of tracks over a range of read offsets to be calibrated; measuring a set of raw track profiles from the series of tracks; sampling the set of raw track profiles at a series of signal amplitude levels; constructing a reference track profile from the set of sampled track profiles; calculating a set of read offset deltas from each sampled track profile; merging the sets of read offset deltas into a set of average read offset deltas; and converting the set of average read offset deltas into a read offset correction table. A similar method for improving disk write head positioning is also provided which utilizes such a read offset correction table to eventually create write offset correction table. | 11-29-2012 |
Harry Gee, Sunnyvale, CA US
Patent application number | Description | Published |
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20110163352 | MONOLITHIC MULTI-CHANNEL ESD PROTECTION DEVICE - A semiconductor device is described that includes one or more electrostatic discharge (ESD) protection circuits. Each circuit comprises reverse-biased steering diodes connected in series between power rail and signal ground, a bypass Zener diode and a substrate Zener diode. The Zener diodes provide ESD protection and the steering diode cooperate with the substrate Zener diode to provide a bypass function that is substantially symmetric about the signal ground. Noise in the circuit can be shunted using internal and/or external capacitances that can be implemented as Zener diodes. | 07-07-2011 |
20130234092 | THREE DIMENSION PROGRAMMABLE RESISTIVE RANDOM ACCESSED MEMORY ARRAY WITH SHARED BITLINE AND METHOD - A method of forming a non-volatile memory device. A substrate is provided and a first dielectric material forms overlying the substrate. A first polysilicon material is deposited overlying the first dielectric material. A second dielectric material is deposited overlying the first polysilicon material. A second polysilicon material is deposited overlying the second dielectric material. A third dielectric material is formed overlying the second polysilicon material. The third dielectric material, the second polysilicon material, the second dielectric material, and the first polysilicon material is subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material, a third wordline and associated with a third switching device, and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and overlies the amorphous silicon material and connected to a common bitline. | 09-12-2013 |
20150188051 | THREE DIMENSION PROGRAMMABLE RESISTIVE RANDOM ACCESSED MEMORY ARRAY WITH SHARED BITLINE AND METHOD - A method of forming a non-volatile memory device. The method forms a vertical stack of first polysilicon material and a second polysilicon material layer isolated by a dielectric material. The polysilicon material layers and the dielectric material are subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material layer, and a third wordline associated with a third switching device and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and connects to a common bitline. | 07-02-2015 |
Harry Yue Gee, Sunnyvale, CA US
Patent application number | Description | Published |
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20080227240 | Method of Making Reliable Wafer Level Chip Scale Package Semiconductor Devices - The present invention relates to a method of making a robust wafer level chip scale package and, in particular, a method that prevents cracking of the passivation layer during solder flow and subsequent multiple thermal reflow steps. In one embodiment, a passivation layer that is formed using a highly compressive insulating material is used. In another aspect, another layer is applied over the passivation layer to assist with preventing cracking of the passivation layer. | 09-18-2008 |
20080258263 | High Current Steering ESD Protection Zener Diode And Method - A method of fabricating a N+/P+ zener diode where the reverse breakdown occurs in a controlled, and uniform manner leading to improved speed of operation and increase in current handling capability. | 10-23-2008 |
20080259518 | Low Operating Voltage Electro-Static Discharge Device And Method - The present invention describes ESD apparatus, methods of forming the same, and methods of providing ESD protection. In certain aspects, the invention achieves the desired turn-on voltage and maintains low leakage in the ESD apparatus, and the methods of providing ESD protection. In one aspect, a zener diode that has a positive trigger voltage is used to quickly turn-on a transistor. In another aspect, different zener diodes that have positive and negative trigger voltages, respectively, are used to quickly turn on a transistor. In still another aspect, a linearly graded P-region is used to implement the ESD device of the present invention. | 10-23-2008 |
20120080769 | ESD DEVICE AND METHOD - A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode. | 04-05-2012 |
Harry Yue Gee, Santa Clara, CA US
Patent application number | Description | Published |
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20140145135 | SUB-OXIDE INTERFACE LAYER FOR TWO-TERMINAL MEMORY - Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichimetric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiO | 05-29-2014 |
20140159108 | METHOD OF FORMING AN ESD DEVICE AND STRUCTURE THEREFOR - In one embodiment, an ESD device is configured to include a trigger device that assists in forming a trigger of the ESD device. The trigger device is configured to enable a transistor or a transistor of an SCR responsively to an input voltage having a value that is no less than the trigger value of the ESD device. | 06-12-2014 |
20140242771 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode. | 08-28-2014 |
20150228893 | SCALABLE SILICON BASED RESISTIVE MEMORY DEVICE - A memory cell that includes a first metal layer formed over a substrate is provided. The substrate includes one or more complementary metal-oxide semiconductor devices. The memory cell also includes a via device that connects at least a portion of the first metal layer and at least another portion of a second metal layer. The first metal layer has a first thickness having an edge thereof that serves as an electrode for a memory cell formed by the via device. The memory cell scales as a function of the first thickness and at least in part independent of a minimum feature size of the memory device. | 08-13-2015 |
20150243886 | MONOLITHICALLY INTEGRATED RESISTIVE MEMORY USING INTEGRATED-CIRCUIT FOUNDRY COMPATIBLE PROCESSES - Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer. | 08-27-2015 |
Harry Yue Gee, Milpitas, CA US
Patent application number | Description | Published |
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20150318333 | INTEGRATIVE RESISTIVE MEMORY IN BACKEND METAL LAYERS - Providing for a memory device having a resistive switching memory integrated within backend layers of the memory device is described herein. By way of example, the resistive switching memory can be embedded memory such as cache, random access memory, or the like, in various embodiments. The resistive memory can be fabricated between various backend metallization schemes, including backend copper metal layers and in part utilizing one or more damascene processes. In some embodiments, the resistive memory can be fabricated in part with damascene processes and in part with subtractive etch processing, utilizing four or fewer photo-resist masks. Accordingly, the disclosure provides a relatively low cost, high performance embedded memory compatible with a variety of fabrication processes of integrated circuit foundries. | 11-05-2015 |
Jeffrey Gee, Daly City, CA US
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20110041015 | DETECTING SOFTWARE RACE CONDITIONS - Detecting a race condition is disclosed. An indication of a store operation to a memory address is received. An identifier of the memory address is stored. The identifier is used to detect an occurrence of a memory operation that is not associated with a previous ordering operation. | 02-17-2011 |
Kelvin W. Gee, Irvine, CA US
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20120077816 | SUBSTITUTED HETEROCYCLES AND THEIR USE AS ALLOSTERIC MODULATORS OF NICOTINIC AND GABAA RECEPTORS - The present invention is related to heterocycles represented by a compound of Formula I that are novel allosteric modulators of α7 nAChRs and/or GABA | 03-29-2012 |
Kyle Gee, Los Angeles, CA US
Patent application number | Description | Published |
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20130206904 | INTEGRATED LAVATORY GALLEY MONUMENT - A monument assembly configured to be positioned interior of an aircraft that includes a galley module, a first lavatory module and a second lavatory module. The module is positioned between the first and second lavatory modules, and the first lavatory module and the galley module share a first inboard dividing wall that includes at least a first non-vertical wall section. | 08-15-2013 |
20130206905 | INTEGRATED GALLEY AND BIN MONUMENT - A galley monument assembly that is configured to be positioned in the interior of an aircraft. The galley monument assembly includes a lower storage section that is adapted to receive at least one trolley cart and that includes a vertically oriented rear wall and two opposing side walls. The lower storage section defines a first storage depth. The galley monument assembly also includes an upper storage section that defines a second storage depth. The second storage depth is deeper than the first storage depth. | 08-15-2013 |
Mark Gee, South Pasadena, CA US
Patent application number | Description | Published |
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20130266417 | BEARING COOLING SYSTEM FOR FLEXIBLE SHAFT TURBOMACHINE - A turbomachine having gas cooled bearings may include an axially-oriented, cooling-gas passageway interconnecting first and second bearing chambers. The passageway may include grooves formed at an interface between an aerodynamic component of the turbomachine (e.g., a wheel or impeller) and a portion of a shaft assembly of the turbomachine. | 10-10-2013 |
20150090119 | SELF-CONTAINED AIRCRAFT ELECTRONIC AIR TREATMENT SYSTEM - An Environmental Control System may use an electronic air treatment system to control humidity in an aircraft. The electronic air treatment system may use an electronic charging system and a separation system. A turbine rotor may drive a power generating stage to provide high voltage power to the electronic charging system. The charging stage may charge airflow passing through to repel liquid particles away from the airflow. Liquid droplets may be collected and centrifugally flung toward a periphery of the separation system. The liquid particles may be collected outside of the airflow, which may be allowed to pass through the separation system and out to a destination in the aircraft without the collected liquid. | 04-02-2015 |
Marvin H. Gee, Stanford, CA US
Patent application number | Description | Published |
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20150197771 | DOMAIN-SWAP T CELL RECEPTORS - Disclosed herein are genetically engineered T cell receptors, and methods, vectors, and genetically engineered T cells related to genetically engineered T cell receptors. | 07-16-2015 |
Michael Gee, Loma Linda, CA US
Patent application number | Description | Published |
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20080203803 | Lumber Distraction Chair - Lumbar distraction is an effective treatment for back pain. However the discomfort and morbidities associated with vertical inversion has limited its use. The Lumbar Distraction Chair delivers a gentler lumbar distraction without the discomfort of being suspended vertically. The device is a modified office swivel chair with inward folding arm rests that secure the patient's legs on the chair seat. The patient positions him/herself onto the device with their back lying on the floor with hips and knees flexed. The arm rests of the chair fold inwards and hold the patient's legs securely onto the seat. A pneumatic telescopic stand elevates the seat, which also lifts the patient's legs hips and lower back off the ground by several centimeters. This provides lumbar distraction to the lower back. In this position, pain and inflammation is alleviated. This permits the muscle cell relaxation, recuperation and repair. | 08-28-2008 |
Michael Gee, San Jose, CA US
Patent application number | Description | Published |
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20120063329 | Manageability Tools for Lossless Networks - Manageability tools are provided for allowing an administrator to have better control over switches in a lossless network of switches. These tools provide the ability to detect slow drain and congestion bottlenecks, detect stuck virtual channels and loss of credits, while hold times on edge ASICs to be different from hold times encore ASICs, and mitigate severe latency bottlenecks. | 03-15-2012 |
20130286858 | MANAGEABILITY TOOLS FOR LOSSLESS NETWORKS - Manageability tools are provided for allowing an administrator to have better control over switches in a lossless network of switches. These tools provide the ability to detect slow drain and congestion bottlenecks, detect stuck virtual channels and loss of credits, while hold times on edge ASICs to be different from hold times encore ASICs, and mitigate severe latency bottlenecks. | 10-31-2013 |
Nancy A. Gee, Woodland, CA US
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20120277203 | ANDROSTENEDIOL AS AN INDICATOR FOR ASSESSING ESTROGENICITY - The present invention provides methods of determining whether a female patient will benefit from hormone replacement therapy. | 11-01-2012 |
Paul Gee, San Jose, CA US
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20090031953 | CHEMICAL VAPOR DEPOSITION OF HIGH QUALITY FLOW-LIKE SILICON DIOXIDE USING A SILICON CONTAINING PRECURSOR AND ATOMIC OXYGEN - Methods of depositing a silicon oxide layer on a substrate are described. The methods may include the steps of providing a substrate to a deposition chamber, generating an atomic oxygen precursor outside the deposition chamber, and introducing the atomic oxygen precursor into the chamber. The methods may also include introducing a silicon precursor to the deposition chamber, where the silicon precursor and the atomic oxygen precursor are first mixed in the chamber. The silicon precursor and the atomic oxygen precursor react to form the silicon oxide layer on the substrate, and the deposited silicon oxide layer may be annealed. Systems to deposit a silicon oxide layer on a substrate are also described. | 02-05-2009 |
Paul Edward Gee, San Jose, CA US
Patent application number | Description | Published |
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20090031955 | VACUUM CHUCKING HEATER OF AXISYMMETRICAL AND UNIFORM THERMAL PROFILE - Embodiments of a vacuum chuck having an axisymmetrical and/or more uniform thermal profile are provided herein. In some embodiments, a vacuum chuck includes a body having a support surface for supporting a substrate thereupon; a plurality of axisymmetrically arranged grooves formed in the support surface, at least some of the grooves intersecting; and a plurality of chucking holes formed through the body and within the grooves, the chucking holes for fluidly coupling the grooves to a vacuum source during operation, wherein the chucking holes are disposed in non-intersecting portions of the grooves. | 02-05-2009 |
20090120364 | GAS MIXING SWIRL INSERT ASSEMBLY - A gas mixing system for a semiconductor wafer processing chamber is described. The mixing system may include a gas mixing chamber concentrically aligned with a gas transport tube that extends to a blocker plate. The gas mixing chamber and the transport tube are separated by a porous barrier that increases a duration of gas mixing in the gas mixing chamber before processes gases migrate into the transport tube. The system may also include a gas mixing insert having a top section with a first diameter and a second section with a second diameter smaller than the first diameter and concentrically aligned with the top section. The processes gases enter the top section of the insert and follow channels through the second section that cause the gases to mix and swirl in the gas mixing chamber. The second section extends into the gas mixing chamber while still leaving space for the mixing and swirling around the sidewalls and bottom of the mixing chamber. | 05-14-2009 |
20100159711 | PRECURSOR ADDITION TO SILICON OXIDE CVD FOR IMPROVED LOW TEMPERATURE GAPFILL - Methods of depositing silicon oxide layers on substrates involve flowing a silicon-containing precursor, an oxidizing gas, water and an additive precursor into a processing chamber such that a uniform silicon oxide growth rate is achieved across the substrate surface. The surface of silicon oxide layers grown according to embodiments may have a reduced roughness when grown with the additive precursor. In other aspects of the disclosure, silicon oxide layers are deposited on a patterned substrate with trenches on the surface by flowing a silicon-containing precursor, an oxidizing gas, water and an additive precursor into a processing chamber such that the trenches are filled with a reduced quantity and/or size of voids within the silicon oxide filler material. | 06-24-2010 |
20110223774 | REDUCED PATTERN LOADING USING BIS(DIETHYLAMINO)SILANE (C8H22N2Si) AS SILICON PRECURSOR - Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications. | 09-15-2011 |
20110250731 | PREFERENTIAL DIELECTRIC GAPFILL - Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively dense first portion of a silicon oxide layer followed by a more porous (and more rapidly etched) second portion of the silicon oxide layer. Narrow trenches are filled with dense material whereas open areas are covered with a layer of dense material and more porous material. Dielectric material in wider trenches may be removed at this point with a wet etch while the dense material in narrow trenches is retained. | 10-13-2011 |
20120094468 | TWO SILICON-CONTAINING PRECURSORS FOR GAPFILL ENHANCING DIELECTRIC LINER - Aspects of the disclosure pertain to methods of depositing silicon oxide layers on substrates. In embodiments, silicon oxide layers are deposited by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor and a second silicon-containing precursor, having both a Si—C bond and a Si—N bond, into a semiconductor processing chamber to form a conformal liner layer. Upon completion of the liner layer, a gap fill layer is formed by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor into the semiconductor processing chamber. The presence of the conformal liner layer improves the ability of the gap fill layer to grow more smoothly, fill trenches and produce a reduced quantity and/or size of voids within the silicon oxide filler material. | 04-19-2012 |
20120225565 | REDUCED PATTERN LOADING USING SILICON OXIDE MULTI-LAYERS - Aspects of the disclosure pertain to methods of depositing conformal silicon oxide multi-layers on patterned substrates. The conformal silicon oxide multi-layers are each formed by depositing multiple sub-layers. Sub-layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS) and an oxygen-containing precursor into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. A plasma treatment may follow formation of sub-layers to further improve conformality and to decrease the wet etch rate of the conformal silicon oxide multi-layer film. The deposition of conformal silicon oxide multi-layers grown according to embodiments have a reduced dependence on pattern density while still being suitable for non-sacrificial applications. | 09-06-2012 |
Perry Gee, San Jose, CA US
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20090300556 | Hierarchical Partitioning - Some embodiments provide a method of simulating an electrical circuit that receives a circuit description that has a set of sub-circuits. The method defines several partitions for several sub-circuits. The method then simulates the circuit using the partitioned sub-circuits. In some embodiments, the method ranks the sub-circuits prior to partitioning based on a parent-child relationship that shows how a sub-circuit is instantiated by other sub-circuits. These embodiments partition child sub-circuits first. Some embodiments provide a method of partitioning an electrical circuit that has a set of sub-circuits. For a particular sub-circuit that is instantiated from other sub-circuits, the method duplicates the particular sub-circuit into a first copy and a second copy when one port of the particular sub-circuit is connected to a voltage source in at least one instance and the same port is not connected to a voltage source in at least another instance. | 12-03-2009 |
20090300566 | Hierarchical Partitioning - Some embodiments provide a method of simulating an electrical circuit that receives a circuit description that has a set of sub-circuits. The method defines several partitions for several sub-circuits. The method then simulates the circuit using the partitioned sub-circuits. In some embodiments, the method ranks the sub-circuits prior to partitioning based on a parent-child relationship that shows how a sub-circuit is instantiated by other sub-circuits. These embodiments partition child sub-circuits first. Some embodiments provide a method of partitioning an electrical circuit that has a set of sub-circuits. For a particular sub-circuit that is instantiated from other sub-circuits, the method duplicates the particular sub-circuit into a first copy and a second copy when one port of the particular sub-circuit is connected to a voltage source in at least one instance and the same port is not connected to a voltage source in at least another instance. | 12-03-2009 |
Randy Gee, Merced, CA US
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20120080026 | APPARATUS AND METHOD FOR SOLAR THERMAL ENERGY COLLECTION - An apparatus for collecting solar energy includes a receptacle adapted for receiving solar thermal energy; an insert located within the receptacle, the insert being a heat pipe adapted to transfer heat; and an absorption device positioned proximate to and substantially conforming to at least a portion of an internal surface of the receptacle and thermally coupled to the insert. The insert enters the receptacle substantially at a cross-sectional center of the receptacle, and further inside the receptacle, the insert shifts to become closer to the absorption fin. | 04-05-2012 |
Robert Gee, Sunnyvale, CA US
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20100308780 | PHASE-CONTROLLED NON-ZERO-CROSS PHOTOTRIAC WITH ISOLATED FEEDBACK - An electronic component for providing optical isolation an electronic component package, a phototriac disposed within the electronic component package for providing the optical isolation, and a reverse zero-cross feedback channel integrated into the electronic component package to thereby provide zero-cross detection. The electronic component may be in a circuit which includes a phase control circuit. A method of driving an AC load and providing zero-cross detection using a single electronic component includes providing an electronic component having an electronic component package, a phototriac disposed within the electronic component package, and a reverse zero-cross feedback channel integrated into the electronic component package to thereby provide for zero-cross detection. The method further includes placing the electronic component within a circuit. | 12-09-2010 |
Samuel Gee, San Bruno, CA US
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20140340796 | System and method of automatic detection and prevention of motor runaway - A robotic catheter control system includes a plurality of electric motors. Diagnostic logic automatically detects motor runaway fault conditions based on the current motor position, the target motor position and a predetermined tolerance parameter. Fault conditions include overshoot, movement in the a non-prescribed direction, exceeding a prescribed maximum motor speed and exceeding a prescribed maximum motor acceleration. The diagnostic logic terminates operating power to the electric motor when a fault condition is detected for any one of the motor. An error message is generated to notify the operator of the fault. | 11-20-2014 |
Samuel K. Gee, San Bruno, CA US
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20120017013 | SYSTEM AND METHODS FOR AVOIDING DATA COLLISIONS OVER A DATA BUS - The disclosed system and methods involve controlling the timing and order in which numerous motors and sensors exchange data over a data bus. The method can be used with, for example, motion control, automotive, industrial automation, and medical equipment applications using data buses. As an example of one possible medical equipment application, the method of exchanging data on a bus can be used with a remote catheter guidance system. The disclosed system and methods help optimize data exchange over a bus and avoid collisions by grouping the transmission of sensor readings, by grouping the transmission of motor commands, and by predetermining the order of these groups. Further, the method provides a way of ensuring that incomplete data sets are not exchanged over the bus. The method also provides a way of synchronizing motor actuation based on data transmitted to the data bus. | 01-19-2012 |
20120158012 | SYSTEM AND METHOD OF AUTOMATIC DETECTION AND PREVENTION OF MOTOR RUNAWAY - A robotic catheter control system includes a plurality of electric motors. Diagnostic logic automatically detects motor runaway fault conditions based on the current motor position, the target motor position and a predetermined tolerance parameter. Fault conditions include overshoot, movement in the a non-prescribed direction, exceeding a prescribed maximum motor speed and exceeding a prescribed maximum motor acceleration. The diagnostic logic terminates operating power to the electric motor when a fault condition is detected for any one of the motor. An error message is generated to notify the operator of the fault. | 06-21-2012 |
Shirley J. Gee, Davis, CA US
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20080279912 | Use of Cis-Epoxyeicosatrienoic Acids And Inhibitors of Soluble Epoxide Hydrolase to Alleviate Eye Disorders - The invention provides methods for alleviating eye disorders due to increased intraocular pressure (“IOP”) or inflammation by administering to the eye or eyes of an individual in need thereof a cis-epoxyeicosatrienoic acid, an inhibitor of soluble epoxide hydrolase (sEH), or both. The invention further provides for reducing IOP or inflammation by methods in which the sEH inhibitor or EETs, or both, are administered systemically. In some embodiments, the methods comprise administering to the individual a nucleic acid encoding an inhibitor of sEH. | 11-13-2008 |
Shirley Jacqueline Gee, Davis, CA US
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20140030741 | In Vitro Method for Determining Presence of Type II Pyrethroids - A method of determining the presence of type II pyrethroid compounds in a sample. | 01-30-2014 |
Stephen Gee, Danville, CA US
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20100109167 | CONDUCTIVE PATHS FOR TRANSMITTING AN ELECTRICAL SIGNAL THROUGH AN ELECTRICAL CONNECTOR - The claimed invention relates to structures suitable for improving the performance and reliability of electrical connectors. One embodiment of the claimed invention includes an integrated circuit die having an electrical contact coupled with electrically conductive paths that share a common electrical source. The conductive paths are configured to transmit the same electrical signal to the electrical contact, which supports an electrical connector, such as a solder bump. The electrical connector couples the die with an outside component, such as a circuit board. Each of the conductive paths connect to the electrical contact at different interface locations. When the electrical signal passes through the interface locations, the paths are configured to have non-zero current densities at those locations. The electrical resistance of the conductive paths may be substantially similar. Thus, instead of being concentrated at a single point, current is more evenly distributed along the junction between the die and solder bump, which may reduce voiding and localized heating. | 05-06-2010 |
Stephen K. Gee, Santa Clara, CA US
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20130138365 | UNINTERRUPTIBLE POWER SUPPLY TESTING - A system includes an uninterruptible power supply (UPS), one or more power supplies, and a processing device. The processing device to execute instructions which cause the processing device to determine a total output current of the one or more power supplies, enable the UPS, determine an output current of at least the UPS, determine a current sharing percentage for at least the UPS, and compare the current sharing percentage for the UPS with an expected current sharing percentage range. | 05-30-2013 |
Vic Gee, Fremont, CA US
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20090143059 | System and method remote servicing of a wireless data processing device - A system and method for remotely servicing a wireless data processing device over a telephony audio channel. For example, a method is described for remotely debugging a wireless data processing device from a service, the wireless device capable of communicating over both a data channel and a telephony channel, the method comprising: receiving a remote diagnostic session request at the service from a wireless data processing device; establishing a telephony-based communication channel with the wireless data processing device if a telephony-based communication channel is not already established; entering codes via the telephone keypad at the service to diagnose the wireless data processing device and transmitting the codes to the wireless data processing device, the codes causing the wireless data processing device to perform one or more operations identified by the codes; and receiving the results of the operations at the service, the results usable for the diagnosis of a problem with the wireless data processing device. | 06-04-2009 |
Zorana Gee, San Francisco, CA US
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20130243306 | Methods and Apparatus for 3D Camera Positioning Using a 2D Vanishing Point Grid - Methods and apparatus for three-dimensional (3D) camera positioning using a two-dimensional (2D) vanishing point grid. A vanishing point grid in a scene and initial camera parameters may be obtained. A new 3D camera may be calculated according to the vanishing point grid that places the grid as a ground plane in a scene. A 3D object may then be placed on the ground plane in the scene as defined by the 3D camera. The 3D object may be placed at the center of the vanishing point grid. Once placed, the 3D object can be moved to other locations on the ground plane or otherwise manipulated. The 3D object may be added as a layer in the image. | 09-19-2013 |