Patent application number | Description | Published |
20090254516 | ACCESSING DATA IN A COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE INDEXING AND REPLICATED REORDERED COLUMNS - Embodiments of the present invention provide hardware-friendly indexing of databases. In particular, forward and reverse indexing are utilized to allow for easy traversal of primary key to foreign key relationships. A novel structure known as a hit list also allows for easy scanning of various indexes in hardware. Group indexing is provided for flexible support of complex group key definition, such as for date range indexing and text indexing. A Replicated Reordered Column (RRC) may also be added to the group index to convert random I/O pattern into sequential I/O of only needed column elements. | 10-08-2009 |
20090254532 | ACCESSING DATA IN A COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE DATA STRUCTURES - Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups. | 10-08-2009 |
20090319486 | METHODS AND SYSTEMS FOR REAL-TIME CONTINUOUS UPDATES - Embodiments of the present invention provide fine grain concurrency control for transactions in the presence of database updates. During operations, each transaction is assigned a snapshot version number or SVN. A SVN refers to a historical snapshot of the database that can be created periodically or on demand. Transactions are thus tied to a particular SVN, such as, when the transaction was created. Queries belonging to the transactions can access data that is consistent as of a point in time, for example, corresponding to the latest SVN when the transaction was created. At various times, data from the database stored in a memory can be updated using the snapshot data corresponding to a SVN. When a transaction is committed, a snapshot of the database with a new SVN is created based on the data modified by the transaction and the snapshot is synchronized to the memory. When a transaction query requires data from a version of the database corresponding to a SVN, the data in the memory may be synchronized with the snapshot data corresponding to that SVN. | 12-24-2009 |
20090319550 | FAST BULK LOADING AND INCREMENTAL LOADING OF DATA INTO A DATABASE - Embodiments of the present invention provide for batch and incremental loading of data into a database. In the present invention, the loader infrastructure utilizes machine code database instructions and hardware acceleration to parallelize the load operations with the I/O operations. A large, hardware accelerator memory is used as staging cache for the load process. The load process also comprises an index profiling phase that enables balanced partitioning of the created indexes to allow for pipelined load. The online incremental loading process may also be performed while serving queries. | 12-24-2009 |
20110099155 | FAST BATCH LOADING AND INCREMENTAL LOADING OF DATA INTO A DATABASE - Embodiments of the present invention provide for batch and incremental loading of data into a database. In the present invention, the loader infrastructure utilizes machine code database instructions and hardware acceleration to parallelize the load operations with the I/O operations. A large, hardware accelerator memory is used as staging cache for the load process. The load process also comprises an index profiling phase that enables balanced partitioning of the created indexes to allow for pipelined load. The online incremental loading process may also be performed while serving queries. | 04-28-2011 |
20110246432 | ACCESSING DATA IN COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE DATA STRUCTURES - Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups. | 10-06-2011 |
20130268489 | METHODS AND SYSTEMS FOR REAL-TIME CONTINUOUS UPDATES - Embodiments of the present invention provide fine grain concurrency control for transactions in the presence of database updates. During operations, each transaction is assigned a snapshot version number or SVN. A SVN refers to a historical snapshot of the database that can be created periodically or on demand. Transactions are thus tied to a particular SVN, such as, when the transaction was created. Queries belonging to the transactions can access data that is consistent as of a point in time, for example, corresponding to the latest SVN when the transaction was created. At various times, data from the database stored in a memory can be updated using the snapshot data corresponding to a SVN. When a transaction is committed, a snapshot of the database with a new SVN is created based on the data modified by the transaction and the snapshot is synchronized to the memory. When a transaction query requires data from a version of the database corresponding to a SVN, the data in the memory may be synchronized with the snapshot data corresponding to that SVN. | 10-10-2013 |
20140324821 | ACCESSING DATA IN A COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE INDEXING AND REPLICATED REORDERED COLUMNS - Embodiments of the present invention provide hardware-friendly indexing of databases. In particular, forward and reverse indexing are utilized to allow for easy traversal of primary key to foreign key relationships. A novel structure known as a hit list also allows for easy scanning of various indexes in hardware. Group indexing is provided for flexible support of complex group key definition, such as for date range indexing and text indexing. A Replicated Reordered Column (RRC) may also be added to the group index to convert random I/O pattern into sequential I/O of only needed column elements. | 10-30-2014 |
20150088880 | SYSTEMS AND METHODS FOR SUPPORTING MULTIPLE DATABASE SERVER VERSIONS ON A DATABASE MACHINE - Techniques are described herein for supporting multiple versions of a database server within a database machine comprising a separate database layer and storage layer. In an embodiment, the database layer includes compute nodes each hosting one or more instances of a database server. The storage layer includes storage nodes each hosting one or more instances of a storage server, also referred to herein as a “cell server.” In general, the database servers may receive data requests, such as SQL queries, from client applications and service the requests in coordination with the cell servers of the storage layer. | 03-26-2015 |
20150356158 | Storage-Side Scanning on Non-Natively Formatted Data - A storage system communicatively coupled to a DBMS performs storage-side scanning of data sources that are not stored in the native database storage format of the DBMS. Data sources for external tables are accessible in a storage system referred to herein as a distributed data access system, e.g. a Hadoop Distributed File System. To execute a query that references an external table, a DBMS first generates an execution plan. The distributed data access system supplies the DBMS with information that specifies each portion of the data source, and specifies which data node to use to access the portion. The DBMS sends a request for each portion to the respective data node, the request requesting that the data node generate rows from data in the portion. The request may specify scanning criteria, specifying one or more columns to project and/or filter on. The request may also specify code modules for the data node to execute to generate rows or records and columns. | 12-10-2015 |
20160092507 | OPTIMIZING A QUERY WITH EXTREMA FUNCTION USING IN-MEMORY DATA SUMMARIES ON THE STORAGE SERVER - Techniques for optimizing a query with an extrema function are provided. In main memory, a data summary is maintained for a plurality of extents stored by at least one storage server. The data summary includes an extent minimum value and an extent maximum value for one or more columns. A storage server request is received, from a database server, based on a query with an extrema function applied to a particular column of a particular table. The data summaries for a set of relevant extents are processed by maintaining at least one global extrema value corresponding to the extrema function and, for each relevant extent of the set of relevant extents, determining whether to scan records of the relevant extent based on at least one of the global extrema value and an extent summary value of the data summary of the relevant extent. | 03-31-2016 |
Patent application number | Description | Published |
20160140258 | METHODS AND SYSTEMS FOR DESIGNING PHOTOVOLTAIC SYSTEMS - A method for designing a photovoltaic (PV) system is implemented by a design automation computer system. The method includes receiving a set of site data, receiving a system type selection, receiving a plurality of system component selections, receiving a plurality of PV layout preferences, determining a PV module layout by iteratively applying a first layout algorithm to the set of site data and the plurality of PV layout preferences, the PV module layout defining a placement of a plurality of PV modules of a PV system, determining a structural layout, an electrical design, and an electrical layout based on the PV module layout, determining a bill of materials based on the PV module layout, the structural layout, and the electrical layout, and designing the PV system using the structural layout, the electrical design, the electrical layout, the PV module layout, and the bill of materials. | 05-19-2016 |
20160140282 | METHODS AND SYSTEMS FOR DETERMINING OBSTRUCTION SETBACKS IN A PHOTOVOLTAIC SYSTEM - A computer-implemented method for determining boundary offsets in a photovoltaic (PV) system based on shadow simulations is implemented by a design automation computer system in communication with a memory. The method includes identifying a set of obstructions wherein the set of obstructions includes a set of obstruction elevations and a set of obstruction offsets, simulating a set of shadow effects using a first coarse shadow algorithm based on the set of obstructions, refining the set of shadow effects using a second fine shadow algorithm based on the set of obstructions and the set of shadow effects, and defining a plurality of boundary of boundary offsets based on the refined set of shadow effects. | 05-19-2016 |
20160140283 | METHODS AND SYSTEMS FOR DETERMINING A PHOTOVOLTAIC SYSTEM LAYOUT - A computer-implemented method for determining a system layout of a photovoltaic (PV) system is implemented by a design automation computer system in communication with a memory. The method includes receiving a first selection of a system table, receiving a layout mode designation, identifying a system orientation, identifying a system spacing, receiving a layout detail designation, and applying a layout algorithm based on the first selection of a system table, the layout mode designation, the layout mode designation, the system orientation, the system spacing and the layout detail designation. | 05-19-2016 |
Patent application number | Description | Published |
20080315811 | System and Method for Collecting Characteristic Information of a Motor, Neural Network and Method for Estimating Regions of Motor Operation from Information Characterizing the Motor, and System and Method for Controlling Motor - A method for collecting operational parameters of a motor may include controlling the energization of a phase winding of the motor to establish an operating point, monitoring operational parameters of the motor that characterize a relationship between the energization control applied to the motor's phase winding and the motor's response to this control, and collecting information of the operational parameters for the operating point that characterizes the relationship between the applied energization control and the motor's response. The collected information characterizing the relationship between the applied energization control and the motor's response may be employed by a neural network to estimate the regions of operation of the motor. And a system for controlling the operation of motor may employ this information, the neural network, or both to regulate the energization of a motor's phase winding di-ring a phase cycle. | 12-25-2008 |
20090045768 | SINGLE SWITCH CONTROLLED SWITCHED RELUCTANCE MACHINE - An improved single-switch control circuit for use in a multi-phase switched reluctance machine is provided. The control circuit includes at least first and second phase windings, a switch, a capacitor, and a diode. The capacitor may have a polarity opposite that of a power source in the control circuit. The first winding may be connected in series with the switch and connected in parallel with a circuit block comprising the second winding. The second winding may be connected in parallel with the capacitor and in series with the diode. In operation, the switch may be used to redirect current from the first winding to the second winding. The capacitor can become charged by the redirected current until it eventually stores enough energy to essentially discontinue current flow in the first winding. Then, the capacitor can discharge its stored energy as a current through the second winding. In this manner, substantially all of the energy from the first winding can be transferred to the second winding. | 02-19-2009 |
20090200980 | SYSTEM AND METHOD FOR CONTROLLING FOUR-QUADRANT OPERATION OF A SWITCHED RELUCTANCE MOTOR DRIVE THROUGH A SINGLE CONTROLLABLE SWITCH - A single controllable switch ( | 08-13-2009 |
20100141061 | Switched Reluctance Machines with Minimum Stator Core - A two-phase switched reluctance machine is provided using discontinuous core structures as the stator for low-cost, high-performance drives. This discontinuous stator core structure contains short flux paths and maximum overlap between the rotor poles and stator poles in the stator discontinuous core structures, regardless of the rotor position. Example configurations of such core structure include E-core, L-core and I-core configurations. Using less steel and magnet wire than in conventional SRM designs results in cost savings of stator material and winding material. Efficiency of this novel SRM is improved because of shorter flux paths resulting in reduction of core losses and decreased phase resistance resulting in reduction of copper losses. Two-phase simultaneous excitation of the novel SRM can reduce torque ripple during commutation as compared with existing two-phase SRMs. | 06-10-2010 |
20110025253 | Single Switch Controlled Switched Reluctance Machine - An improved single-switch control circuit for use in a multi-phase switched reluctance machine is provided. The control circuit includes at least first and second phase windings, a switch, a capacitor, and a diode. The capacitor may have a polarity opposite that of a power source in the control circuit. The first winding may be connected in series with the switch and connected in parallel with a circuit block comprising the second winding. The second winding may be connected in parallel with the capacitor and in series with the diode. In operation, the switch may be used to redirect current from the first winding to the second winding. The capacitor can become charged by the redirected current until it eventually stores enough energy to essentially discontinue current flow in the first winding. Then, the capacitor can discharge its stored energy as a current through the second winding. In this manner, substantially all of the energy from the first winding can be transferred to the second winding. | 02-03-2011 |
20110187300 | Motor Power Factor Correction Apparatus and Method - A power factor correction system includes a rectifier that rectifies the voltage of an alternating current (ac) power source to produce a voltage waveform that transitions, in a half sinusoid, from a minimum amplitude to a maximum amplitude and back to the minimum amplitude twice in the period of the ac power source. A phase winding of a motor conveys current induced by the voltage waveform, and a regulator regulates the flow of the current conveyed by the phase winding for storage as energy in a storage component. | 08-04-2011 |
20110193507 | Method, Controller, and Power Converter for Controlling a Single-Switch Based Switched Reluctance Machine - A method for controlling a multi-phase motor includes withholding energization of a first phase of the motor for a non-zero period when the first phase's dwell time begins. Energization of the first phase is activated upon the expiration of the non-zero period. Energization of the first phase is deactivated for the remainder of the dwell time at a deactivation time occurring before or at the expiration of the dwell time. | 08-11-2011 |
20110234027 | HIGH DENSITY WINDINGS FOR A CONCENTRIC WOUND ELECTRICAL MACHINE STATOR - A switched reluctance motor includes at least four stator poles and an electrically conductive material around each of the stator poles. The geometric outline, on one side of the stator pole, of at least one of the conductive materials is not rectangular, as viewed from a cross-section of the switched reluctance motor showing each of the stator poles. | 09-29-2011 |
20110234134 | PM BRUSHLESS MOTOR DRIVE CIRCUIT TOPOLOGY AND CONTROL - An inverter for a permanent magnet brushless do machine, having a permanent magnet rotor and a set of stator windings, applies the full dc voltage provided to the inverter to each phase of the machine. | 09-29-2011 |
20110234136 | POWER FACTOR CORRECTION DRIVE CIRCUIT TOPOLOGIES AND CONTROL FOR SWITCHED RELUCTANCE MACHINES - Drive circuits that provide power factor correction and input current waveform shaping for controlling the speed and torque in a switched reluctance machine (SRM). The machine's phase windings are split into two segments, one of which is used for active power factor correction, input ac current waveform shaping and partial torque generation and the other of which is used for torque generation. | 09-29-2011 |
20110260672 | HIGH POWER DENSITY SWITCHED RELUCTANCE MACHINES WITH HYBRID EXCITATION - A switched reluctance machine having salient stator and rotor poles. Alternating ones of the stator poles having windings and the others having permanent magnets attached on their pole faces. The alternate stator pole windings are provided with polarities that are suitable for unidirectional and bidirectional current operation of the switched reluctance machine. The alternate poles with permanent magnets in the switched reluctance machines can have also concentric windings placed on them and excited with currents to further augment the flux linkages in the stator poles. The windings on the poles with permanent magnets can be excited from the same source as the windings on the poles without permanent magnets to enhance power output or provide power factor correction. | 10-27-2011 |
20120056570 | SYSTEM AND METHOD FOR COLLECTING CHARACTERISTIC INFORMATION OF A MOTOR, NEURAL NETWORK AND METHOD FOR ESTIMATING REGIONS OF MOTOR OPERATION FROM INFORMATION CHARACTERIZING THE MOTOR, AND SYSTEM AND METHOD FOR CONTROLLING MOTOR OPERATION USING THE CHARACTERISTIC INFORMATION, THE NEURAL NETWORK, OR BOTH - A method for collecting operational parameters of a motor may include controlling the energization of a phase winding of the motor to establish an operating point, monitoring operational parameters of the motor that characterize a relationship between the energization control applied to the motor's phase winding and the motor's response to this control, and collecting information of the operational parameters for the operating point that characterizes the relationship between the applied energization control and the motor's response. The collected information characterizing the relationship between the applied energization control and the motor's response may be employed by a neural network to estimate the regions of operation of the motor. And a system for controlling the operation of motor may employ this information, the neural network, or both to regulate the energization of a motor's phase winding during a phase cycle. | 03-08-2012 |
20120104879 | NOISE REDUCTION STRUCTURES FOR ELECTRICAL MACHINES - An electrical machine rotor or stator having a plurality of salient poles and a barrier that inhibits the flow of air along an axial path between the environment outside the rotor or stator and the space between adjacent pairs of the poles. The barrier serves to reduce acoustic noise. | 05-03-2012 |
20120104895 | HIGH POWER DENSITY SRM - An electromagnetic machine stator has a common pole and a plurality of excitation poles. Each excitation pole has a coil wound around it for inducing a magnetic flux through the excitation pole. The common pole that does not have a coil wound around it for inducing a magnetic flux. A flux barrier, disposed within the common pole, inhibits the flow of flux from one part of the common pole across the flux barrier to another part of the common pole. The flux barrier is less conducive to the flow of flux than is the common pole. | 05-03-2012 |
20120104980 | SWITCHED RELUCTANCE AND PM BRUSHLESS DC MOTOR DRIVE CONTROL FOR ELECTRIC VEHICLE APPLICATION - A method of operating an electrical machine having first and second phase windings. The method includes: (1) applying positive first current to the first phase winding while the first phase winding's back electromotive force (emf) is positive; (2) applying negative second current to the first phase winding while the first phase winding's back emf is negative; and (3) applying positive third current to the second phase winding while the second phase winding's back emf is positive. The first current is conducted through a circuit composed of a battery, the first phase winding, and a first switch. The second current is conducted through a circuit composed of a first capacitive storage element, the battery, the first phase winding, and a second switch, and the third current is conducted through a circuit composed of the battery, the second phase winding, and a third switch. | 05-03-2012 |
20120104982 | ROTOR LAMINATION SHAPING FOR MINIMUM CORE LOSS IN SRMs - An electrical machine rotor includes a flux-conducting portion and a flux-inhibiting portion. The flux-conducting portion is conducive to conveying an electromagnetic flux and has a plurality of salient rotor poles and a portion of back material. The flux-inhibiting portion is less conducive to conveying an electromagnetic flux than the flux-conducting portion and is disposed entirely outside the boundaries of the rotor poles. | 05-03-2012 |
20120104984 | POWER FACTOR CORRECTION CIRCUITS FOR SWITCHED RELUCTANCE MACHINES - An electrical device has a capacitive storage element and first and second switches. The capacitive storage element and first and second switches are interconnected such that when interconnected with a direct current (dc) voltage supply and first and second windings of an electrical machine: (1) a first operational state exists in which conductive states of the first and second switches cause the dc voltage supply to conduct current through the first winding and the first switch and conduct current through the first and second switches and the second winding, respectively, thereby storing energy within the first and second windings, and (2) a second operational state exists in which non-conductive states of the first and second switches cause each of the first and second windings to discharge stored energy by conducting current through the capacitive storage element, thereby storing energy in the capacitive storage element. | 05-03-2012 |
20120104988 | HIGH POWER DENSITY SRMs - A power converter having a first switch and a first unidirectional current device that conducts current unidirectionally. The first switch and first unidirectional current device are interconnected such that when interconnected with a dc voltage supply, battery, and first phase winding of an electrical machine: (1) a first operational state exists in which a conductive state of the first switch causes the dc voltage supply to conduct current through the first switch and first phase winding, so as to store energy within the first phase winding and (2) a second operational state exists in which a non-conductive state of the first switch causes the first phase winding to discharge its stored energy by conducting current through the first unidirectional current device and battery, so as to store energy in the battery. | 05-03-2012 |
20130009589 | SYSTEM AND METHOD FOR CONTROLLING FOUR-QUADRANT OPERATION OF A SWITCHED RELUCTANCE MOTOR DRIVE THROUGH A SINGLE CONTROLLABLE SWITCH - Regulating the speed of a two-phase switched reluctance machine (TPSRM) rotor includes selecting either a motoring mode or braking mode of operation for the TPSRM, regulating the rotor speed, when the motoring mode is selected, using a control signal cooperatively produced by a speed control feedback loop and a current control feedback loop; and regulating the rotor speed, when the braking mode is selected, using a control signal produced by the current control feedback loop without the cooperation of the speed control feedback loop. The speed control feedback loop uses an established speed control signal and a signal indicative of the rotor's speed to dynamically adjust a first parameter governing the control signal. The current control feedback loop uses an established current control signal and a signal indicative of the current flowing through a stator winding of the TPSRM to dynamically adjust a second parameter governing the control signal. | 01-10-2013 |
20140035490 | POWER FACTOR CORRECTION DRIVE CIRCUIT TOPOLOGIES AND CONTROL FOR SWITCHED RELUCTANCE MACHINES - Drive circuits that provide power factor correction and input current waveform shaping for controlling the speed and torque in a switched reluctance machine (SRM). The machine's phase windings are split into two segments, one of which is used for active power factor correction, input ac current waveform shaping and partial torque generation and the other of which is used for torque generation. | 02-06-2014 |
20140084816 | POWER CONVERTER FOR AN ELECTRICAL MACHINE AND METHOD OF OPERATING THE MACHINE - A power converter has a first electrical circuit including a direct current (dc) voltage source, a first phase winding of an electrical machine, and a first switch operating in a conductive state. A second electrical circuit includes the first phase winding, a first unidirectional current device, and a capacitive storage element. A third electrical circuit includes the capacitive storage element, a second switch operating in a conductive state, and the first phase winding. A fourth electrical circuit includes the first phase winding, the dc voltage source, and a second unidirectional current device. | 03-27-2014 |
20150124267 | ROTOR LAMINATION SHAPING FOR MINIMUM CORE LOSS IN SRMS - An electrical machine rotor includes a flux-conducting portion and a flux-inhibiting portion. The flux-conducting portion is conducive to conveying an electromagnetic flux and has a plurality of salient rotor poles and a portion of back material. The flux-inhibiting portion is less conducive to conveying an electromagnetic flux than the flux-conducting portion and is disposed entirely outside the boundaries of the rotor poles. | 05-07-2015 |
20150372543 | SYSTEM AND METHODS OF ELECTRIC MACHINE ROTOR POSITION DETECTION - An electric machine includes a stator assembly defining a longitudinal axis. The stator assembly includes a substantially cylindrical stator core that is concentric with and extends longitudinally along the longitudinal axis. The stator core includes a stator pole having an inner surface spaced radially outward from the longitudinal axis. The stator pole includes a first aperture extending radially outward from the inner surface of the stator pole. The electric machine also includes a rotor assembly rotatable about the longitudinal axis. The rotor assembly includes a rotatable shaft and a rotor core. The rotor core is concentric with and extends longitudinally along the longitudinal axis. The rotor core also includes a rotor pole including an outer surface spaced radially outward from the longitudinal axis. The outer surface is spaced radially inward from the stator pole inner surface. | 12-24-2015 |
Patent application number | Description | Published |
20110119426 | LIST BASED PREFETCH - A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current cache miss address is valid. If the current cache miss address is valid, the list prefetch engine compares the current cache miss address and a list address. A list address represents an address in a list. A list describes an arbitrary sequence of prior cache miss addresses. The prefetch engine prefetches data according to the list, if there is a match between the current cache miss address and the list address. | 05-19-2011 |
20110119526 | LOCAL ROLLBACK FOR FAULT-TOLERANCE IN PARALLEL COMPUTING SYSTEMS - A control logic device performs a local rollback in a parallel super computing system. The super computing system includes at least one cache memory device. The control logic device determines a local rollback interval. The control logic device runs at least one instruction in the local rollback interval. The control logic device evaluates whether an unrecoverable condition occurs while running the at least one instruction during the local rollback interval. The control logic device checks whether an error occurs during the local rollback. The control logic device restarts the local rollback interval if the error occurs and the unrecoverable condition does not occur during the local rollback interval. | 05-19-2011 |
20110173357 | ARBITRATION IN CROSSBAR INTERCONNECT FOR LOW LATENCY - A system and method and computer program product for reducing the latency of signals communicated through a crossbar switch, the method including using at slave arbitration logic devices associated with Slave devices for which access is requested from one or more Master devices, two or more priority vector signals cycled among their use every clock cycle for selecting one of the requesting Master devices and updates the respective priority vector signal used every clock cycle. Similarly, each Master for which access is requested from one or more Slave devices, can have two or more priority vectors and can cycle among their use every clock cycle to further reduce latency and increase throughput performance via the crossbar. | 07-14-2011 |
20110173358 | EAGER PROTOCOL ON A CACHE PIPELINE DATAFLOW - A master device sends a request to communicate with a slave device to a switch. The master device waits for a period of cycles the switch takes to decide whether the master device can communicate with the slave device, and the master device sends data associated with the request to communicate at least after the period of cycles has passed since the master device sent the request to communicate to the switch without waiting to receive an acknowledgment from the switch that the master device can communicate with the slave device. | 07-14-2011 |
20110173397 | PROGRAMMABLE STREAM PREFETCH WITH RESOURCE OPTIMIZATION - A stream prefetch engine performs data retrieval in a parallel computing system. The engine receives a load request from at least one processor. The engine evaluates whether a first memory address requested in the load request is present and valid in a table. The engine checks whether there exists valid data corresponding to the first memory address in an array if the first memory address is present and valid in the table. The engine increments a prefetching depth of a first stream that the first memory address belongs to and fetching a cache line associated with the first memory address from the at least one cache memory device if there is not yet valid data corresponding to the first memory address in the array. The engine determines whether prefetching of additional data is needed for the first stream within its prefetching depth. The engine prefetches the additional data if the prefetching is needed. | 07-14-2011 |
20110173398 | TWO DIFFERENT PREFETCHING COMPLEMENTARY ENGINES OPERATING SIMULTANEOUSLY - A prefetch system improves a performance of a parallel computing system. The parallel computing system includes a plurality of computing nodes. A computing node includes at least one processor and at least one memory device. The prefetch system includes at least one stream prefetch engine and at least one list prefetch engine. The prefetch system operates those engines simultaneously. After the at least one processor issues a command, the prefetch system passes the command to a stream prefetch engine and a list prefetch engine. The prefetch system operates the stream prefetch engine and the list prefetch engine to prefetch data to be needed in subsequent clock cycles in the processor in response to the passed command. | 07-14-2011 |
20110173420 | PROCESSOR RESUME UNIT - A system for enhancing performance of a computer includes a computer system having a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processor. An external unit is external to the processor for monitoring specified computer resources. The external unit is configured to detect a specified condition using the processor. The processor including one or more threads. The thread resumes an active state from a pause state using the external unit when the specified condition is detected by the external unit. | 07-14-2011 |
20110173422 | PAUSE PROCESSOR HARDWARE THREAD UNTIL PIN - A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit. | 07-14-2011 |
20110219208 | MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER - A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency. | 09-08-2011 |
20120324142 | LIST BASED PREFETCH - A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current cache miss address is valid. If the current cache miss address is valid, the list prefetch engine compares the current cache miss address and a list address. A list address represents an address in a list. A list describes an arbitrary sequence of prior cache miss addresses. The prefetch engine prefetches data according to the list, if there is a match between the current cache miss address and the list address. | 12-20-2012 |
Patent application number | Description | Published |
20080229049 | PROCESSOR CARD FOR BLADE SERVER AND PROCESS. - System including a processor card containing at least two processors, and a memory card containing at least two memory units. At least one memory unit is associated with each processor. A controller dynamically allocates memory in the at least two memory units to the at least two processors. | 09-18-2008 |
20090006718 | SYSTEM AND METHOD FOR PROGRAMMABLE BANK SELECTION FOR BANKED MEMORY SUBSYSTEMS - A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures. | 01-01-2009 |
20090006762 | METHOD AND APPARATUS OF PREFETCHING STREAMS OF VARYING PREFETCH DEPTH - Method and apparatus of prefetching streams of varying prefetch depth dynamically changes the depth of prefetching so that the number of multiple streams as well as the hit rate of a single stream are optimized. The method and apparatus in one aspect monitor a plurality of load requests from a processing unit for data in a prefetch buffer, determine an access pattern associated with the plurality of load requests and adjust a prefetch depth according to the access pattern. | 01-01-2009 |
20090006808 | ULTRASCALABLE PETAFLOP PARALLEL SUPERCOMPUTER - A novel massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. Novel use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node. | 01-01-2009 |
20140281084 | LOCAL BYPASS FOR IN MEMORY COMPUTING - Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network. | 09-18-2014 |
20140281100 | LOCAL BYPASS FOR IN MEMORY COMPUTING - Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network. | 09-18-2014 |
Patent application number | Description | Published |
20080233069 | Multi-Purpose Polymers, Methods and Compositions - Disclosed are multi-purpose polymers that are the polymerization product of a monomer mixture comprising at least one amino-substituted vinyl monomer; at least one nonionic vinyl monomer; at least one associative vinyl monomer; at least one semihydrophobic vinyl surfactant monomer; and, optionally, comprising one or more hydroxy-substituted nonionic vinyl monomer, crosslinking monomer, chain transfer agent or polymeric stabilizer. These vinyl addition polymers have a combination of substituents, including amino substituents that provide cationic properties at low pH, hydrophobic substituents, hydrophobically modified polyoxyalkylene substituents, and hydrophilic polyoxyalkylene substituents. The polymers provide surprisingly beneficial rheological properties in acidic aqueous compositions, and are compatible with cationic materials. The multi-purpose polymers are useful in a variety of products for personal care, health care, household care, institutional and industrial care, and industrial applications. | 09-25-2008 |
20090087400 | BREATHABLE POLYURETHANES, BLENDS, AND ARTICLES - A hair fixative composition containing a breathable polyurethane having an upright moisture vapor transmission rate (MVTR) of more than about 500 gms/m | 04-02-2009 |
20120136174 | Method For Synthesizing Aminoalcohols - The present invention relates to a method for synthesizing amonoalcohols (e.g., aminoalcohols that contain an amine group that is either unsubstituted, mono-substituted, or di-substituted) and to the products formed therefrom. In one embodiment, the present invention relates to a method for synthesizing aminoalcohols from a corresponding aminoaldehyde and to the products formed therefrom. In another embodiment, the present invention relates to a method for synthesizing aminoalcohols from a corresponding aminoaldehyde via a hydrogenation process using a suitable catalyst (e.g., Raney® Nickel) and to the products formed therefrom. In still another embodiment, the present invention relates to aminoalcohols formed via direct hydrogenation from a corresponding aminoaldehyde without the intervening step of converting the aminoaldehyde starting material to a salt. | 05-31-2012 |
20120237465 | Hydrolytically Stable Multi-Purpose Polymer - The present invention relates to compositions containing hydrolytically stable multi-purpose polymers that are polymerized from a monomer mixture comprising: at least one amino-substituted meth(acrylate) (ASMA) monomer or salt thereof; and at least one nonionic vinyl (NIV) monomer, wherein the monomer mixture optionally comprises one or more of at least one vinyl associative (VA) monomer; at least one vinyl surfactant (VS) monomer; and/or at least one polymerizable silicone macromer (PSM) and wherein the monomer mixture further optionally comprises one or more of at least one crosslinking (XL) monomer; at least one chain transfer agent (CTA); and/or at least one polymeric stabilizer. The multi-purpose polymers of the present invention can also be prepared from monomer mixtures containing chain transfer agents or other functional components commonly utilized in polymerization processes. | 09-20-2012 |
20120316308 | Hydrolytically Stable Multi-Purpose Polymers - The present invention relates to hydrolytically stable multi-purpose polymers that are polymerized from a monomer mixture comprising: at least one amino-substituted meth(acrylate) (ASMA) monomer or salt thereof; and at least one nonionic vinyl (NIV) monomer, wherein the monomer mixture optionally comprises one or more of at least one vinyl associative (VA) monomer; at least one vinyl surfactant (VS) monomer; and/or at least one polymerizable silicone macromer (PSM) and wherein the monomer mixture further optionally comprises one or more of at least one crosslinking (XL) monomer; at least one chain transfer agent (CTA); and/or at least one polymeric stabilizer. The multi-purpose polymers of the present invention can also be prepared from monomer mixtures containing chain transfer agents or other functional components commonly utilized in polymerization process. | 12-13-2012 |
20130046063 | Irritation Mitigating Polymers and Uses Therefor - A method for increasing the efficacy of hydrophobically modified (meth)acrylic based polymers to increase the critical micelle concentration of a surfactant composition by attenuating the degree of neutralization (DN) of the polymer is disclosed. | 02-21-2013 |
20130101543 | Blends Of Acrylic Copolymer Thickeners - Disclosed are blends of acrylic polymers comprising at least one crosslinked acrylic copolymer and at least one linear acrylic copolymer. The acrylic polymer blends surprisingly provide desirable rheological, clarity, and aesthetic properties in aqueous surfactant containing compositions, particularly at low pH. | 04-25-2013 |
20130115185 | Structured Acrylate Copolymer Thickeners - Disclosed are multi-staged acrylic based core-shell polymers comprising a linear core polymer and at least one subsequently polymerized shell polymers is crosslinked. The core-shell polymers surprisingly provide desirable rheological, clarity, and aesthetic properties in aqueous surfactant containing compositions, particularly at low pH. | 05-09-2013 |
20130137844 | Polymerizable Silicone Copolyol Macromers And Polymers Made Therefrom - A polymerizable dimethicone copolyol macromer composition is synthesized by reacting itaconic anhydride with a dimethicone copolyol. During the reaction itaconic anhydride spontaneously isomerizes to citraconic anhydride which in turn is esterified by the dimethicone copolyol. The obtained macromers are copolymerizable with olefinically unsaturated monomers. Polymers containing the macromer repeating units are useful in a variety of applications including personal care, textile and industrial formulations to deliver softness, lubricity, fixative, water repellency, gloss, surface modification, and surfactant properties. | 05-30-2013 |
20130164242 | Polymers And Compositions - The present invention relates to hair care and personal care compositions which contain an acrylic copolymer which is polymerized in the presence of at least two different classes of crosslinking monomers. The polymer functions both as a fixative/film former and a thickening agent for hair styling and personal care compositions in which it is contained. The copolymer exhibits advantageous fixative, film forming and rheological gel properties. | 06-27-2013 |
20130183361 | STRUCTURED ACRYLATE COPOLYMER FOR USE IN MULTI-PHASE SYSTEMS - Disclosed are multi-staged acrylic based core-shell polymers comprising a linear core polymer and at least one subsequently polymerized shell polymer. At least one of the subsequently polymerized shell polymers is crosslinked. The core-shell polymers surprisingly provide desirable rheological, clarity, and aesthetic properties in aqueous surfactant containing compositions, particularly at low pH. The multi-staged acrylic base core-shell polymers can be included in at least one phase of a multi-phase personal care, home care, health care, and institutional and industrial care composition to impart phase stability thereto. | 07-18-2013 |
20130189198 | Acrylate Copolymer Thickeners - Disclosed are surfactant compositions containing at least one crosslinked acrylic copolymer. The crosslinked acrylic copolymer is polymerized in the presence of at least two different classes of crosslinking monomers. The crosslinked acrylic copolymers provide desirable rheological, clarity, and aesthetic properties in aqueous surfactant containing compositions. | 07-25-2013 |
20140275460 | Acrylate-Olefin Copolymers, Methods For Producing Same And Compositions Utilizing Same - The present invention relates to a thickeners that are the polymerization product of a monomer mixture comprising: (a) at least one C3 to C30 olefin; (b) at least one monomer that contains at least one carboxylic acid group; (c) at least one ethylenically unsaturated ester monomer; and (d) one or more crosslinking compounds. Optionally, the above multi-purpose polymer compositions can further include any combination of one or more of: (e) at least one functional monomer; (f) at least one associative hydrophobic monomer; and/or (g) at least one chain transfer agent (CTA) and/or at least one polymeric stabilizer. The thickeners of the present invention are useful in a variety of products including, but not limited to, personal care products, health care products, household care products, institutional and industrial care products, and industrial applications. | 09-18-2014 |
20150342858 | CARBOXYETHYL ACRYLATE CONTAINING COPOLYMER STABILIZER/THICKENERS AND METHODS TO MITIGATE THE LOSS OF SILICONE DEPOSITION ON KERATINOUS SUBSTRATES - A conditioning cleansing composition comprising at least one detersive surfactant, a silicone conditioning agent and a crosslinked acrylic copolymer stabilizer/thickener that mitigates the loss silicone deposition on keratinous substrates is disclosed. The crosslinked acrylic copolymer is prepared by polymerizing a monomer composition comprising: a) from about 5 to about 50 wt. % of carboxyethyl acrylate and/or oligomers thereof; b) from about 30 to about 95 wt. % of a monomer selected from ethyl acrylate, vinyl acetate, or mixtures thereof; c) from about 0 to about 50 wt. % of (meth)acrylic acid; and d) from about 0.001 to about 5 wt. % of a polyunsaturated crosslinking monomer containing at least two polymerizable ethylenically unsaturated moieties. | 12-03-2015 |
Patent application number | Description | Published |
20130080419 | AUTOMATIC INFORMATION PRESENTATION OF DATA AND ACTIONS IN SEARCH RESULTS - Architecture that inserts one or more label items in search result entries. In addition to the typical search result caption (title, snippet, and link), the architecture includes the label component of one or more of the label items in the result entry. The number and type of label annotations are based on the query. When a particular label item is selected (e.g., hover, mouse click), a presentation component (e.g., expansion object, pop-up window) launches proximate to a label item in response to interaction with the label item and presents additional information from the target webpage. The additional information can include an action and data related to the search result entry and the target webpage. The data can be obtained from a data source other than the target webpage. | 03-28-2013 |
20130086041 | USE OF OFF-PAGE CONTENT TO ENHANCE CAPTIONS WITH ADDITIONAL RELEVANT INFORMATION - Architecture that uses content from off-page data sources such as feeds (e.g., yellow pages, coupons, social networks, commerce, etc.) to present additional, relevant information in association with search results. The additional and relevant information is directly relevant to the implicit task the user is trying to accomplish. The architecture includes online and offline mechanisms that identify an entity represented on a web page and look-up information related to that entity in disparate data sources. Relevance heuristics are employed to determine which of the available entity data to show in the caption given the user query, the web page, and the underlying user task (other known information about the user such as geographic location). | 04-04-2013 |
20130151936 | PAGE PREVIEW USING CONTEXTUAL TEMPLATE METADATA AND LABELING - Architecture that provides a preview template of information supplemented to a result entry of a results page, such as a search engine results page. A data component supplements the result entry with information from a results destination document. The information is segmented and grouped into logical collections of related results according to contextual templates. Each template is associated with an interactive label that exposes a corresponding collection in response to label interaction. Each label of a template is a visual cue that includes a descriptive title which relates to individual web results of the collection. A user can scan through the labels and interact only with the section (collection) of interest to obtain a preview of destination document results before committing a click that navigates the user to the destination document of the website. The labels are also ranked within the template of information for a given result entry. | 06-13-2013 |
20130262430 | DOMINANT IMAGE DETERMINATION FOR SEARCH RESULTS - Architecture that computes a dominant image from one or more images on a webpage. A dominant image classifier scans webpages in an offline-created index to identify the prominent images in the webpages. In a more specific implementation the image selected is the image associated with a name query. Face detection technology can be utilized to identify which of the images on a given webpage contain faces. A query classifier identifies queries that contain people names. In the context of search engines and search result pages, the web results for name queries can further include prominent people face images as thumbnail images. Additional facts (structured data) can further be included that together with the results elements of caption title, snippet and attribute (uniform resource locator (URL)) provide an improved summary of the person on the page. | 10-03-2013 |