Sugimae
Kikuko Sugimae, Kuwana JP
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20150243887 | SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor memory device comprises a memory cell array. The memory cell array comprises a plurality of first wiring lines, a plurality of second wiring lines extending crossing the first wiring lines, and a plurality of memory cells disposed at intersections of the first and second wiring lines. The memory cells are stacked in a direction perpendicular to a substrate, and each memory cell comprises a variable resistance element. The semiconductor memory device also includes a select transistor layer comprising a plurality of select transistors, each select transistor being operative to select any one of the first wiring lines or one of the second wiring lines. Two select transistors are connected to two different respective first wiring lines, stacked in a direction perpendicular to the substrate, and configured to share one gate electrode. | 08-27-2015 |
Kikuko Sugimae, Kanagawa JP
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20130026566 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device according to an embodiment includes: a p-type semiconductor substrate; a p-type first p well which is formed in the semiconductor substrate and in which a bit line connecting transistor configured to connect a bit line of a memory cell and a sense amplifier unit is formed; and an n-type first N well which surrounds the first P well and which is configured to electrically isolate the first P well from the semiconductor substrate. | 01-31-2013 |
Kikuko Sugimae, Mie JP
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20140268999 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell that is connected to a selected first wire and a selected second wire during a reset operation. The control circuit is configured to execute a cancel operation that applies a cancel voltage of a second polarity that is opposite to the first polarity to an unselected memory cell and at the same time can execute a verify operation that reads out the state of the selected memory cell by applying a readout voltage of the second polarity to the selected memory cell. The cancel voltage and the readout voltage are the same voltage value. | 09-18-2014 |
Kikuko Sugimae, Kuwana Mie JP
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20150162083 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell that is connected to a selected first wire and a selected second wire during a reset operation. The control circuit is configured to execute a cancel operation that applies a cancel voltage of a second polarity that is opposite to the first polarity to an unselected memory cell and at the same time can execute a verify operation that reads out the state of the selected memory cell by applying a readout voltage of the second polarity to the selected memory cell. The cancel voltage and the readout voltage are the same voltage value. | 06-11-2015 |
Kikuko Sugimae, Kanagawa-Ken JP
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20090303797 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the substrate, a first gate electrode formed on the gate insulating film, source and drain regions formed in the substrate so as to sandwich the first gate electrode, an intergate insulating film formed on the first gate electrode and including an opening, a second gate electrode formed on the intergate insulating film and electrically connected to the first gate electrode through the opening, and a boost electrode formed on the intergate insulating film and electrically isolated from the first gate electrode and the second gate electrode. | 12-10-2009 |
20100052173 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A first impurity diffusion layer in a memory cell portion and a second impurity diffusion layer in a peripheral circuit portion are provided in a surface of a semiconductor substrate and having upper faces substantially flush with each other. First and second insulating films are formed to cover the upper faces of the impurity diffusion layers, and having substantially uniform film thicknesses. A first metal plug is formed in the insulating films, and connected to the first impurity diffusion layer. A second metal plug is formed in the first insulating film, to have a lower height than the first metal plug, and is connected to the second impurity diffusion layer. A first metal interconnection is connected to an upper end portion of the first metal plug, and having an upper face embedded in and flush with the second insulating film. A second metal interconnection is connected to an upper end portion of the second metal plug, and having an upper face embedded in and flush with the second insulating film. | 03-04-2010 |
20110241095 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In one embodiment, a semiconductor memory device, including a memory cell having a floating gate electrode above a semiconductor substrate via a first gate insulator and a control gate electrode above the floating gate electrode via a first inter-gate insulator, a contact electrode having a bottom electrode contacted to an upper surface of the semiconductor substrate, top electrodes via a second inter-gate insulators on both edge portions of the bottom electrode and a plug electrode between the top electrodes, the plug electrode contacted to an upper surface of the bottom electrode. | 10-06-2011 |
20120236619 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory array and a peripheral circuit. The memory array has a plurality of memory cells, word lines, and bit lines, in which a first, second, and third blocks are set in the order along the bit line. The peripheral circuit has a transistor group. The transistor group includes a first transfer transistor belonging to the first block, a second transfer transistor belonging to the second block, and a third transfer transistor belonging to the third block. The first, second, and third transfer transistors share the other of a source and a drain of each. With regard to a direction in which either of the source and the drain is connected to the other in each of the first, second, and third transfer transistors, the directions of the adjacent transfer transistors are different from each other by 90° or 180°. | 09-20-2012 |
20130077461 | STORAGE DEVICE - A storage device includes a recording medium, a probe, a substrate, and a processing unit. The recording medium stores a signal. The probe reads or writes the signal to/from the recording medium. The substrate is provided with the probe via a conductive anchor interposed therebetween and a first connection terminal connected to the probe. The processing unit is provided on the substrate and has a second connection terminal. The second connection terminal is connected to the first connection terminal. | 03-28-2013 |
20140070161 | MEMORY DEVICE - According to one embodiment, a memory device includes a first interconnect, a second interconnect and a pillar connected between the first interconnect and the second interconnect. The pillar includes a first high-resistance layer, a second high-resistance layer, and a metal layer. The first high-resistance layer is connected to the first interconnect. A resistivity of the first high-resistance layer is higher than a resistivity of the first interconnect and a resistivity of the second interconnect. The second high-resistance layer is connected to the second interconnect. A resistivity of the second high-resistance layer is higher than the resistivity of the first high-resistance layer. A thickness of the second high-resistance layer is not more than a thickness of the first high-resistance layer. The metal layer is disposed between the first high-resistance layer and the second high-resistance layer. The metal layer includes a metal. | 03-13-2014 |
20140284536 | RESISTANCE RANDOM ACCESS MEMORY DEVICE - A resistance random access memory device according to one embodiment includes an interlayer insulation film which a trench is made therein, an ion supply layer provided along a bottom surface and a side surface of the trench, a portion of the ion supply layer provided along the bottom surface is thicker than a portion of the ion supply layer provided along the side surface, and a resistance change layer provided at least below the ion supply layer. | 09-25-2014 |
Kikuko Sugimae, Minato-Ku JP
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20120037976 | NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME - A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor. | 02-16-2012 |
Rich Sugimae, Oceanside, CA US
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20090170627 | FERRULE AND GOLF CLUB INCORPORATING SAME - A ferrule, and a golf club incorporating same, are provided. The ferrule defines an axial bore for receiving a club shaft therethrough. A bottom portion of the ferrule is sized to receive and surround an upper end of a hosel of a club head. The ferrule can further include a chamfered or rounded, annular edge formed on a bottom end thereof. The hosel and the ferrule are cooperatively configured to inhibit movement of the ferrule and, preferably, axial rotation and longitudinal movement of the ferrule are both inhibited by engagement of corresponding surfaces of the ferrule and the hosel. Preferably, protrusions at an upper, interior surface of the ferrule body serve to center the shaft within the ferrule and to enhance a flow of adhesive between the shaft, hosel and ferrule. Preferably, ribs at a lower, interior surface of the ferrule are received in corresponding grooves formed on an upper exterior surface of the hosel. These ribs serve to locate and initially fix the ferrule onto the hosel of the club head. Alternatively, the hosel may include at least one strut having a knife-like edge configured to cut into the interior surface of the ferrule, thereby inhibiting axial rotation. | 07-02-2009 |
Ryuichi Sugimae, Oceanside, CA US
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20090253530 | Golf club grip - A golf club has a hand grip comprising an exterior surface and an interior surface with an elongated bore located between the two surfaces and extending generally parallel to the golf club shaft. A removable shim with a generally arc shaped cross section is disposed inside of the bore and forms a “reminder rib” for a player using the club. | 10-08-2009 |
20140295988 | GOLF CLUB HEAD WITH IMPROVED STRIKING FACE - A golf club head with an improved striking face is disclosed herein. More specifically, the present invention utilizes an innovative die quenching method that can alter the Young's modulus of the material of the striking face. The striking face portion of the present invention generally created from an α+β titanium alloy such as SP 700 that contains a β rich alloy composition to create more phase change in the alloying elements. In a preferred embodiment, the die quenching process could create a localized change in the material's Young's modulus throughout different regions of the striking face, resulting in a change in the Young's modulus of the material within the same striking face. | 10-02-2014 |
Ryuichi Sugimae, San Diego, CA US
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20140171215 | GOLF CLUB SHAFT - A golf club and golf club shaft includes a tubular member having at least one neck portion with a reduced outer diameter and at least one relatively rigid two-piece sleeve secured to the tubular member in overlying relationship to each neck portion. The two-piece sleeve defines a small central gap filled by a compressible ring to allow the two otherwise longitudinally aligned sleeve pieces to pivot relative to one another under dynamic loading of the tubular member during a golf swing, and then upon reaching a limit point restrict additional deflection or bending of the tubular member. | 06-19-2014 |
Toshio Sugimae, Chiba JP
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20100010107 | RESIN COMPOSITION FOR VIBRATION DAMPING MATERIAL AND VIBRATION DAMPING MATERIAL - A resin composition for vibration damping material for a vibration damping material exhibiting high vibration damping performance in a wider temperature range and a vibration damping material using the same are provided. The resin composition contains 100 parts by weight of a resin component A as a matrix and 5 to 300 parts by weight of a resin component B dispersed in the matrix. The resin component B has two or more cyclic structures selected from the group consisting of an aromatic hydrocarbon group, an aliphatic cyclic hydrocarbon group, and a heteroaromatic group, and is in a glassy state at use temperature. | 01-14-2010 |