Patent application number | Description | Published |
20110085385 | Nonvolatile Memory Devices Having Dummy Cell and Bias Methods Thereof - Provided are nonvolatile memory devices and methods of operating thereof. The nonvolatile memory devices include: dummy cells connected to a dummy bit line; and a dummy bit line bias circuit providing a dummy bit line voltage to the dummy bit line during a program operation, wherein, due to the dummy bit line voltage, at least one of the dummy cells is programmed with a threshold voltage lower than the top programmed state and higher than an erased state during the program operation. | 04-14-2011 |
20110205802 | NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME - Provided are a nonvolatile memory device and a method of reading the same. The nonvolatile memory device includes: a memory cell; a transistor disposed between a common source line and the memory cell; and a control logic for controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line during a read operation. The method includes: applying a read voltage to the memory cell; and controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line. | 08-25-2011 |
20110286274 | NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - A nonvolatile memory device preventing a program disturb, a program method thereof and a memory system including the nonvolatile memory device and the program method. The nonvolatile memory device includes a memory cell array; first and second word lines connected to a NAND string in the memory cell array; a third word line connected to the NAND string, the third word line being disposed between the first and second word lines; a temperature sensor configured to measure the temperature of the nonvolatile memory device; and a voltage generator configured to generate first and second pass voltages and a program voltage, and the voltage level of at least one of the first and second pass voltages is controlled according to the measured temperature. When a program operation is performed, the program voltage is applied to the third word line, the first pass voltage is applied to the first word line, the second pass voltage is applied to the second word line. | 11-24-2011 |
20110305079 | NONVOLATILE MEMORY DEVICE INCLUDING DUMMY MEMORY CELL AND PROGRAM METHOD THEREOF - A nonvolatile memory device including a dummy memory cell and a method of programming the same, wherein the nonvolatile memory device includes a dummy memory cell, and a plurality of memory cells serially connected to the dummy memory cell. The nonvolatile memory device sets a voltage provided to the dummy memory cell according to a distance between a selected memory cell among the plurality of memory cells and the dummy memory cell when a program operation is performed. | 12-15-2011 |
20120003828 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME - A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern. | 01-05-2012 |
20120033503 | CHARGE TRAP FLASH MEMORY DEVICE AND AN ERASING METHOD THEREOF - An erase method of a charge trap flash memory device, the method including receiving a temperature detection result, and performing an erase operation based on the temperature detection result, wherein the erase operation includes an erase execution interval, an erase verify interval and a delay time between the erase execution interval and the erase verify interval, wherein the erase operation changes a level of a word line voltage applied to word lines during the erase execution interval, a length of the delay time, or a level of the word line voltage applied to the word lines during the delay time. | 02-09-2012 |
20120061744 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Three dimensional semiconductor memory devices are provided. The three dimensional semiconductor memory device includes a first stacked structure and a second stacked structure sequentially stacked on a substrate. The first stacked structure includes first insulating patterns and first gate patterns which are alternately and repeatedly stacked on a substrate, and the second stacked structure includes second insulating patterns and second gate patterns which are alternately and repeatedly stacked on the first stacked structure. A plurality of first vertical active patterns penetrate the first stacked structure, and a plurality of second vertical active patterns penetrate the second stacked structure. The number of the first vertical active patterns is greater than the number of the second vertical active patterns. | 03-15-2012 |
20120230103 | Nonvolatile Memory Device And Operating Method Thereof - According to example embodiments, a nonvolatile memory device includes a substrate, at least one string extending vertically from the substrate, and a bit line current controlling circuit connected to the at least one string via at least one bit line. The at least one string may include a channel containing polycrystalline silicon. The bit line current controlling circuit may be configured to increase the amount of current being supplied to the bit line according to a decrease in a temperature such that a current flowing through the channel of the at least one string is increased when a temperature decreases. | 09-13-2012 |
20150084114 | NON-VOLATILE MEMORY DEVICES INCLUDING BLOCKING INSULATION PATTERNS WITH SUB-LAYERS HAVING DIFFERENT ENERGY BAND GAPS - A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed. | 03-26-2015 |
Patent application number | Description | Published |
20090206387 | Non-volatile memory device, method of fabricating the same, and non-volatile semiconductor integrated circuit device, including the same - A non-volatile memory device has improved operating characteristics. The non-volatile memory device includes an active region; a wordline formed on the active region to cross the active region; and a charge trapping layer interposed between the active region and the wordline, wherein a cross region of the active region and the wordline includes an overlap region in which the charge trapping layer is disposed and a non-overlap region in which the charge trapping layer is not disposed. | 08-20-2009 |
20100133604 | Semiconductor Devices Having Gate Structures with Conductive Patterns of Different Widths and Methods of Fabricating Such Devices - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern. | 06-03-2010 |
20100301425 | SEMICONDUCTOR DEVICE HAVING A GATE CONTACT STRUCTURE CAPABLE OF REDUCING INTERFACIAL RESISTANCE - A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening. | 12-02-2010 |
20100317157 | CELL ARRAY OF SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FORMING THE SAME - A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region. | 12-16-2010 |
20110095351 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region. | 04-28-2011 |
20110119564 | FLASH MEMORY DEVICE AND MEMORY SYSTEM COMPRISING SAME - A flash memory device provided here comprises a user data area storing user data; and a security data area storing security data. The security data area stores a security data pattern in which first groups of memory cells storing security data are arranged respectively between second groups of memory cells storing dummy data. | 05-19-2011 |
20110298037 | VERTICAL STRUCTURE NONVOLATILE MEMORY DEVICES - A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends. | 12-08-2011 |
20130301350 | Vertical Structure Nonvolatile Memory Device - A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends. | 11-14-2013 |
20140087534 | METHODS OF MANUFACTURING VERTICAL STRUCTURE NONVOLATILE MEMORY DEVICES - A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends. | 03-27-2014 |
20140183615 | NON-VOLATILE MEMORY DEVICES INCLUDING BLOCKING INSULATION PATTERNS WITH SUB-LAYERS HAVING DIFFERENT ENERGY BAND GAPS - A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed. | 07-03-2014 |
20150060979 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes a channel and gate electrodes. The channel extends in a vertical direction with respect to a top surface of a substrate. The gate electrodes are disposed on an outer sidewall of the channel. The gate electrodes includes a ground selection line (GSL), a word line, a string selection line (SSL) and a first dummy word line sequentially stacked from the top surface of the substrate in the vertical direction to be spaced apart from each other. The channel includes an impurity region at a portion adjacent to the SSL. | 03-05-2015 |
Patent application number | Description | Published |
20090215233 | PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING ARRAY SUBSTRATE USING THE SAME - A photoresist composition includes a binder resin, a photo acid generator, an acryl resin having four different types of monomers, and a solvent. | 08-27-2009 |
20100009482 | PHOTORESIST COMPOSITION, METHOD OF FORMING A METAL PATTERN, AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE USING THE SAME - A photoresist composition includes 5% to 50% by weight of an alkali-soluble resin, 0.5% to 30% by weight of a quinone diazide compound, 0.1% to 15 % by weight of a curing agent, and a remainder of an organic solvent. A method of forming a metal pattern includes coating a photoresist composition on a base substrate having a metal layer, and forming a first photoresist film. The photoresist composition includes 5% to 50% by weight of an alkali-soluble resin, 0.5% to 30% by weight of a quinone diazide compound, 0.1% to 15% by weight of a curing agent, and a remainder of an organic solvent. The first photoresist film is patterned, and forms a first photo pattern. The base substrate having the first photo pattern is heated, and forms a first baked pattern. The metal layer is patterned using the first baked pattern, and forms a metal pattern. | 01-14-2010 |
20100167206 | PHOTORESIST COMPOSITION AND METHOD FOR MANUFACTURING A DISPLAY SUBSTRATE USING THE PHOTORESIST COMPOSITION - A photoresist composition includes a novolac resin, a benzophenone photosensitizer and an ethylidyne tris phenol photosensitizer, and an organic solvent. Thus, a micropattern having a higher resolution than the resolution of an exposure apparatus is formed to decrease an amount of exposure and/or exposure time, thereby improving manufacturing reliability and productivity. | 07-01-2010 |
20110171581 | PHOTORESIST COMPOSTION AND METHOD OF MANUFACTURING ARRAY SUBSTRATE USING THE SAME - A photoresist composition includes a binder resin, a photo acid generator, an acryl resin having four different types of monomers, and a solvent. | 07-14-2011 |
20110287360 | PHOTORESIST COMPOSITION AND METHOD OF FORMING PATTERN BY USING THE SAME - A photoresist composition is provided. The photoresist composition includes an alkali-soluble resin; a photosensitizer containing a first compound that contains a diazonaphthoquinone represented by Formula 1 and a second compound that contains a diazonaphthoquinone represented by Formula 2; and a solvent. | 11-24-2011 |
20130048604 | PHOTORESIST COMPOSITION AND METHOD OF FORMING A FINE PATTERN USING THE SAME - A photoresist composition includes from about 20% to about 50% by weight of a polymer, from about 0.5% to about 1.5% by weight of a photo-acid generator, from about 0.01% to about 0.5% by weight of a photo absorber and the remainder includes an organic solvent. Also provided is a method of forming a fine pattern including forming a thin film on a substrate; forming a photoresist pattern by using a photoresist composition that includes from about 20% to about 50% by weight of a polymer, from about 0.5% to about 1.5% by weight of a photo-acid generator, from about 0.01% to about 0.5% by weight of a photo absorber and a remainder comprising an organic solvent; and patterning the thin film by using the photoresist pattern as an etch-stop layer to form a fine pattern. | 02-28-2013 |
Patent application number | Description | Published |
20080273405 | Multi-bit programming device and method of multi-bit programming - A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to select backup memory cells in the memory cell array with respect to each bit of the original multi-bit data, and program each bit of the original multi-bit data to a respective one of the selected backup memory cells. | 11-06-2008 |
20080276149 | Error control code apparatuses and methods of using the same - An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data. | 11-06-2008 |
20080276150 | ERROR CONTROL CODE APPARATUSES AND METHODS OF USING THE SAME - An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose. | 11-06-2008 |
20080285340 | Apparatus for reading data and method using the same - Disclosed are an apparatus and a method for reading data. The method for reading data according to example embodiments includes comparing a threshold voltage of a memory cell with a first boundary voltage, comparing the threshold voltage with a second boundary voltage having a higher voltage level than that of the first boundary voltage, and determining data of the memory cell based on the threshold voltage, the first boundary voltage, and the second boundary voltage. | 11-20-2008 |
20080320064 | Method and apparatus for controlling reading level of memory cell - A method and apparatus for controlling a reading level of a memory cell are provided. The method of controlling a reading level of a memory cell may include: receiving metric values calculated based on given voltage levels and reference levels; generating summed values for each of the reference levels by summing metric values corresponding to levels of a received signal from among the received metric values; selecting the reference level having the greatest value of the generated summed values from the reference levels; and controlling the reading level of the memory cell based on the selected reference level. | 12-25-2008 |
20090196097 | Device for reading memory data and method using the same - Provided are a device for reading memory data and a method using the same. The device for reading memory data comprises a memory cell which stores multi-bit information, an information detection unit which detects as much bit information as a predetermined number of bits from among multi-bit information, a source-line voltage control unit which controls a source-line voltage of the memory cell based on the detected bit information from the information detection unit, and a remaining bit information read unit which reads remaining bit information stored in the memory cell by using the controlled source-line voltage. | 08-06-2009 |
20110213930 | Multi-level cell memory device and method thereof - A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions. | 09-01-2011 |
20130294158 | MULTI-LEVEL CELL MEMORY DEVICES AND METHODS OF STORING DATA IN AND READING DATA FROM THE MEMORY DEVICES - A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream. | 11-07-2013 |
20150023108 | NONVOLATILE MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A nonvolatile memory device comprises a memory cell array comprising multiple memory cells disposed at intersections of corresponding word lines and bitlines, and multiple page buffers connected to the bitlines, respectively, and performing consecutive verify read operations on selected memory cells programmed in first to N-th logic states (N>2), wherein, in the consecutive verify read operations, the bitlines are placed in a precharged state by precharging them to a first level during a verification period of memory cells programmed in the first logic state, are maintained in the precharged state during verification periods of memory cells programmed in the second to (N−1)-th logic states, and are discharged after a verification period of memory cells programmed in the N-th logic state. | 01-22-2015 |
20150063030 | METHOD OF TESTING NON-VOLATILE MEMORY DEVICE AND METHOD OF MANAGING NON-VOLATILE MEMORY DEVICE - A method of testing a non-volatile memory device and a method of managing the non-volatile memory device are provided. The method of testing the non-volatile memory device includes calculating first and second values based on program loop frequencies corresponding to word lines of a memory area. A characteristic value of the memory area may be calculated based on the first and second values, and may be compared to a reference value to determine whether the memory area is defective. | 03-05-2015 |
Patent application number | Description | Published |
20100041723 | Thiazole Compound (as PPAR delta) Ligand and Pharmaceutical, Cosmetic and Health Food Comprised Thereof - The present invention relates to a thiazole compound as a peroxisome proliferator activated receptor δ (PPARδ) activator or pharmaceutically acceptable salts thereof, and a pharmaceutical composition, a functional cosmetic composition, a health food, health beverages, a food additive and animal feeds containing the same. | 02-18-2010 |
20110004023 | Potassium Organotrifluoroborate Derivative and a Production Method Therefor - Provided are a production method for a potassium organotrifluoroborate compound having a hydroxyl group, and a novel potassium organotrifluoroborate compound having a hydroxyl group. The production method is advantageous in that a potassium organotrifluoroborate compound can be produced in a single reaction without recourse to a process of isolating and purifying an intermediate. The novel potassium organotrifluoroborate compound having a hydroxyl group is useful as a reactant which is widely used in the total synthesis of physiologically active natural products and diverse organic synthesis reactions including halogen substitution reactions, 1,2- and 1,4-addition reactions using a rhodium (Rh) catalyst, and Suzuki coupling reactions using a palladium (Pd) catalyst. | 01-06-2011 |
20120197024 | Thiazole Compound (as PPAR delta) Ligand and Pharmaceutical, Cosmetic and Health Food Comprised Thereof - The present invention relates to a thiazole compound as a peroxisome proliferator activated receptor δ (PPARδ) activator or pharmaceutically acceptable salts thereof, and a pharmaceutical composition, a functional cosmetic composition, a health food, health beverages, a food additive and animal feeds containing the same. | 08-02-2012 |
20120271055 | ARYL COMPOUNDS AS PPAR LIGANDS AND THEIR USE - The present invention relates to a compound as a peroxisome proliferator activated receptor (PPAR) activator and a hydrate, a solvate, a stereoisomer and a pharmaceutically acceptable salt thereof, and a pharmaceutical composition, a cosmetic composition, a muscle strengthening agent, a memory improving agent, a therapeutic agent for dementia and Parkinson's disease, a functional food and a feed composition containing the same. | 10-25-2012 |
20120316346 | SELENALZOLE DERIVATIVE HAVING LIGAND WHICH ACTIVATES PEROXISOME PROLIFERATOR ACTIVATED RECEPTOR (PPAR), PREPARING METHOD THEREOF AND USAGE OF THE CHEMICAL COMPOUNDS - Provided are a novel selenazole derivative which activates peroxisome proliferator-activated receptor (PPAR), a hydrate thereof, a solvate thereof, a stereoisomer thereof and a pharmaceutically acceptable salt thereof, a method for preparing the same, and a pharmaceutical composition, a cosmetic composition, a functional food composition, a functional drink composition and an animal feed composition containing the same. | 12-13-2012 |
Patent application number | Description | Published |
20090083514 | APPARATUS AND METHOD FOR BLOCK INTERLEAVING IN MOBILE COMMUNICATION SYSTEM - A method and apparatus for block interleaving that eliminates the step of intermediary buffering. The method includes: (a) calculating a memory address at which first output data, of which number is equal to the number of rows of a first encoder is stored, (b) storing the first output data at the calculated memory address of a circular buffer, (c) storing second output data at an address which is incremented by a specific constant value from the calculated memory address of the circular buffer, and (d) storing (n+1) | 03-26-2009 |
20090154442 | METHOD AND APPARATUS FOR REDUCING DIGITAL TO ANALOG CONVERSION (DAC) BITS IN FREQUENCY DIVISION MULTIPLE ACCESS (FDMA) SYSTEM - A method and an apparatus for reducing Digital-to-Analog Conversion (DAC) bits at a transmitter of a Frequency Division Multiple Access (FDMA) system reduces a number of the bits for conversion so as to save power and reduce the cost of operation. The method can include generating a digital signal gain control value and an analog signal gain control value using subcarrier allocation information, a required Signal to Noise Ratio (SNR), and a Peak to Average Power Ratio (PAPR); controlling a gain of a signal input to a digital-to-analog converter using the digital signal gain control value; converting a digital signal of the controlled gain to an analog signal using the digital-to-analog converter; and restoring an original signal by controlling a gain of a signal output from the digital-to-analog converter using the analog signal gain control value. | 06-18-2009 |
20100322065 | APPARATUS AND METHOD FOR TRANSMITTING/RECEIVING SIGNAL IN SINGLE CARRIER FREQUENCY DIVISION MULTIPLEXING ACCESS COMMUNICATION SYSTEM - A method and apparatus for transmitting a signal in a Single Carrier-Frequency Division Multiplexing Access (SC-FDMA) communication system are provided. The method includes determining if a Bandwidth Expansion Factor (BEF) Q is an integer, the BEF being determined as N/M according to a number N of subcarriers of a system band and a number M of subcarriers of an allocated band, expanding an input signal to be transmitted Q times in a time domain when the Q is an integer, generating an SC-FDMA signal, and transmitting the SC-FDMA signal. | 12-23-2010 |
20110182339 | METHOD AND APPARATUS FOR REDUCING PEAK TO AVERAGE POWER RATIO USING PEAK WINDOWING - A method and apparatus for reducing a Peak to Average Power Ratio (PAPR) using peak windowing is provided. In the apparatus, an absolute value calculator calculates an absolute value of an input signal, a subtractor subtracts a predetermined clipping threshold level from the absolute value, a smoothing unit performs smoothing on the subtracted signal according to a predetermined smoothing scheme and outputs a first smoothed signal, an adder adds the first smoothed signal to the clipping threshold level, an inverse calculator outputs a second smoothed signal by multiplying the clipping threshold level by an inverse of the added signal, and a multiplier outputs a final PAPR-reduced signal by multiplying the input signal by the second smoothed signal. The method and apparatus address an overcompensation problem while processing signals having a large bandwidth and a high data rate without delay, thereby minimizing the clipping influences on Bit Error Rate (BER) and Adjacent Channel Leakage Ratio (ACLR) performances. | 07-28-2011 |
20110258244 | SMOOTHING APPARATUS FOR PEAK WINDOWING - A smoothing apparatus for peak windowing includes an operator for generating a first input signal for smoothing using an input signal for peak windowing and a predetermined clipping threshold level. The apparatus also includes a subtractor for subtracting a feedback signal from the first input signal, and a maximum operator for generating a second input signal. The apparatus also includes a feedback path for generating a feedback signal for a next smoothed input signal by multiplying samples of the second input signal by window coefficients in a first window coefficient combination and a predetermined gain and summing up the multiplication results. The apparatus further includes a convolutional operator for generating a smoothed signal by multiplying samples of the second input signal by window coefficients in a second window coefficient combination for low pass filtering and summing up the multiplication results. | 10-20-2011 |
20120089658 | MODULO OPERATION METHOD AND APPARATUS FOR SAME - The present invention provides a modulo operation method. The modulo operation method, in a case where the square of a divisor N is greater than or equal to a dividend C, includes: determining the number of computation stages n satisfying 2 | 04-12-2012 |
20130072139 | APPARATUS AND METHOD FOR PROCESSING REDUCED BANDWIDTH ENVELOPE TRACKING AND DIGITAL PRE-DISTORTION - An apparatus and a method for processing reduced bandwidth Envelope Tracking (ET) and Digital Pre-Distortion (DPD) are provided. The apparatus includes a Crest Factor Reduction (CFR) unit, a resealing Digital Pre-Distortion (DPD) unit, an envelope converter, a Supply Modulator (SM), and a Power Amplifier (PA). The CFR unit suppresses an increase of a side lobe occurring when a Peak to Average Power Ratio (PAPR) decreases with respect to a signal generated in a baseband according to a standard and passes through a transmit (Tx) filter. The resealing DPD unit receives an original envelope amplitude and a reduced bandwidth envelope amplitude of an In-phase/Quadrature-phase (I/Q) signal output from the CFR unit to perform a pre-distortion process. The envelope converter converts an envelope signal to a reduced bandwidth envelope signal based on the I/Q signal output from the CFR unit. | 03-21-2013 |
20130159369 | APPARATUS AND METHOD FOR PERFORMING DISCRETE FOURIER TRANSFORM - A Discrete Fourier Transform (DFT) apparatus is provided. The DFT apparatus includes a first delay, a second delay, an operator, and a multiplier. The first delay delays one sampling data by N-sample in a time axis when the one sampling data is input. The second delay delays an output value of a frequency component for a previous sampling data by 1-sample. The operator performs an operation based on the input one sampling data, the one sampling data delayed by the N-sample in the time axis, and the 1-sample delayed output value of the frequency component for the previous sampling data. The multiplier multiplies an output value from the operator by a twiddle factor | 06-20-2013 |
Patent application number | Description | Published |
20120256729 | METHOD, APPARATUS, AND SYSTEM FOR PROVIDING A SERVICE - A method and a system for providing a service are provided. In the method for providing the service, a user terminal receives customized information among individuals or group members. The method includes: obtaining tag information by reading a tag attached to an object, the tag information containing a tag code and service data; obtaining service access information from an Object Directory Service (ODS) server when the tag is tagged in a situation, the service access information corresponding to at least one of the obtained tag information and identification information; and receiving a customized information service corresponding to the user terminal by accessing a service providing server in accordance with the service access information. | 10-11-2012 |
20120259780 | METHOD, TERMINAL AND SYSTEM FOR PROVIDING DATA TRANSMISSION AND FINANCIAL TRANSACTION BASED ON THE POSITION OF MOBILE TERMINALS HAVING SHORT-RANGE COMMUNICATION FUNCTION - Method and terminal for performing a financial transaction based on a relative position between terminals. A system for performing a financial transaction based on a relative position of mobile terminals includes: a user terminal configured to generate payment data in association with a transaction amount and to deduct the transaction amount from a payer account; a transaction terminal configured to receive the payment data from the user terminal by use of short-range communication and to add the transaction amount corresponding to the payment data to a payee account; and a financial server configured to approve the financial transaction based on the payment data, wherein the payment data is determined by a positional relationship between the user terminal and the transaction terminal. | 10-11-2012 |
20120260311 | METHOD, MOBILE TERMINAL AND SYSTEM FOR PROVIDING DIFFERENT AUTHENTICATION VALUES ACCORDING TO CONTACT METHOD OF MOBILE TERMINAL - System and method of authenticating a terminal. An authentication system which provides an authentication value specified by a tilt angle of a terminal, includes a terminal which measures the tilt angle, and a short-range communication reader which receives the tilt angle and terminal identification data from the terminal by using short-range communication and which generates the authentication value based on the tilt angle. The short-range communication reader authenticates the terminal based on the authentication value. | 10-11-2012 |
20130045682 | SYSTEM, MOBILE COMMUNICATION TERMINAL AND METHOD FOR TRANSFERRING INFORMATION - A system, a mobile communication terminal, and a method for transferring information. The system for transferring information includes a first terminal configured to extract and transmit transfer information and a second terminal configured to receive the transfer information. Here, the transfer information corresponds to an intersection state between the first terminal and the second terminal when the first terminal performs first short-range communication with the second terminal, and the first terminal and the second terminal compute their respective position information when the first short-range communication is performed, exchange the position information with each other, and calculate the intersection state information based on the respective position information of the first and second terminals. | 02-21-2013 |
20130045686 | SYSTEM, MOBILE COMMUNICATION TERMINAL AND METHOD FOR PROVIDING INFORMATION - A system, a mobile communication terminal, and a method for providing information. The system for providing information includes: a tag configured to store tag information; a mobile communication terminal configured to obtain the tag information using short-range communication and to calculate position information of the mobile communication terminal when the tag information is obtained; and an information providing server configured to receive the tag information and the position information from the mobile communication terminal, extract service address information which provides information for connecting to a service identified by the tag information and based on the position information, and provide the extracted service address information to the mobile communication terminal. The mobile communication terminal is connected to the service based on the service address information. | 02-21-2013 |
20130282569 | METHOD, TERMINAL AND SYSTEM FOR PROVIDING DATA TRANSMISSION AND FINANCIAL TRANSACTION BASED ON THE POSITION OF MOBILE TERMINALS HAVING SHORT-RANGE COMMUNICATION FUNCTION - Method and terminal for performing a financial transaction based on a relative position between terminals. A system for performing a financial transaction based on a relative position of mobile terminals includes: a user terminal configured to generate payment data in association with a transaction amount and to deduct the transaction amount from a payer account; a transaction terminal configured to receive the payment data from the user terminal by use of short-range communication and to add the transaction amount corresponding to the payment data to a payee account; and a financial server configured to approve the financial transaction based on the payment data, wherein the payment data is determined by a positional relationship between the user terminal and the transaction terminal. | 10-24-2013 |
20130295964 | MOTION BASED SERVICE PROVISION - In one example embodiment, an end device includes a sensor configured to sense a motion of the end device; a location detector configured to detect a location of the end device; a translator configured to translate parameters of the sensed motion into a service request stored in a memory of the end device; a transmitter configured to transmit, to a service provider, the service request and the location of the end device; and a receiver configured to receive, from the service provider, an expression of a service that is associated with an object located within a predetermined range of the end device. | 11-07-2013 |
20130328662 | MOTION BASED SERVICE PROVISION - In one example embodiment, an apparatus includes a reader configured to read motion information, received from an end device, regarding a motion that was enacted by a user relative to the end device; a request generator configured to generate a service request that includes an identifier of the apparatus and the read motion information; a transmitter configured to transmit, to a service provider, the service request; and a receiver configured to receive, from the service provider, an expression of a service that is associated with the identifier of the apparatus and the read motion information. | 12-12-2013 |
20130335201 | FUNCTION EXECUTION BASED ON TAG INFORMATION - In one example embodiment, an end device includes a memory configured to store function information regarding at least one predefined function and tag information regarding at least one electronic tag that is associated with the at least one predefined function; a reader configured to read tag identification information received from a detected electronic tag located within a predetermined range of the end device; and a processor configured to select a predefined function from among the at least one predefined function based on the stored tag information and the read tag identification information and perform the selected predefined function. | 12-19-2013 |
Patent application number | Description | Published |
20130003362 | OPTICAL SEMICONDUCTOR BASED ILLUMINATING APPARATUS - An optical semiconductor based illuminating apparatus including a housing having an opening portion, a lighting unit disposed adjacent to the housing that includes at least one optical semiconductor, a power supply mounted within the housing that supplies power to the lighting unit, and a gate unit connected to the opening part that opens and shuts the inner housing. | 01-03-2013 |
20130314914 | OPTICAL SEMICONDUCTOR LIGHTING APPARATUS - An optical semiconductor lighting apparatus includes: a light emitting module including one or more semiconductor optical devices; a switching mode power supply (SMPS) connected to the light emitting module; a housing disposed to be adjacent to the light emitting module, in which the housing has both ends opened and accommodates the SMPS; a first heat dissipation unit disposed at an inner side of the housing; and a second heat dissipation unit disposed radially at an outer side of the housing and formed from an outer side of one end portion of the housing to the edge of the light emitting module. The first heat dissipation unit includes a plurality of heat dissipation plates through which the heat pipe penetrates, and a plurality of vent portions formed on the heat dissipation plates. | 11-28-2013 |
20140043833 | OPTICAL SEMICONDUCTOR LIGHTING APPARATUS - A first heat sinking path formed in a forming direction of a heat sink unit disposed radially in a housing where a light emitting module is mounted. A second heat sinking path is formed along an edge of the light emitting module. By providing a light engine concept in which a light emitting module, an optical member, and a heat sink unit are included and a bottom surface is gradually widened from one side to the other side, an optical semiconductor lighting apparatus can reduce a total weight of a product, can further improve heat dissipation efficiency by inducing natural convection, is simple in the product assembly and installation, and is easy in maintenance, and can provide products with high reliability by increasing the arrangement efficiency of semiconductor optical devices per unit area. | 02-13-2014 |
20150062914 | OPTICAL SEMICONDUCTOR LIGHTING APPARATUS - A first heat sinking path formed in a forming direction of a heat sink unit disposed radially in a housing where a light emitting module is mounted. A second heat sinking path is formed along an edge of the light emitting module. By providing a light engine concept in which a light emitting module, an optical member, and a heat sink unit are included and a bottom surface is gradually widened from one side to the other side, an optical semiconductor lighting apparatus can reduce a total weight of a product, can further improve heat dissipation efficiency by inducing natural convection, is simple in the product assembly and installation, and is easy in maintenance, and can provide products with high reliability by increasing the arrangement efficiency of semiconductor optical devices per unit area. | 03-05-2015 |
20150070911 | OPTICAL SEMICONDUCTOR LIGHTING APPARATUS - A first heat sinking path formed in a forming direction of a heat sink unit disposed radially in a housing where a light emitting module is mounted. A second heat sinking path is formed along an edge of the light emitting module. By providing a light engine concept in which a light emitting module, an optical member, and a heat sink unit are included and a bottom surface is gradually widened from one side to the other side, an optical semiconductor lighting apparatus can reduce a total weight of a product, can further improve heat dissipation efficiency by inducing natural convection, is simple in the product assembly and installation, and is easy in maintenance, and can provide products with high reliability by increasing the arrangement efficiency of semiconductor optical devices per unit area. | 03-12-2015 |
Patent application number | Description | Published |
20110170414 | APPARATUS AND METHOD FOR PERFORMING CONGESTION CONTROL IN A COMMUNICATION SYSTEM - A method for performing congestion control in a communication system. The method includes transmitting a request message to a node using a first packet with a highest priority and receiving a response message corresponding to the request message using the first packet and at least one of a plurality of second packets, estimating a one-way delay of the first packet according to a round trip time for the first packet, converting one of the one-way delay of the first packet and the one-way delay of at least one of the plurality of second packets into a quality of service (QoS) level using a predetermined upper delay bound for a corresponding packet, and converting the converted QoS level into an effective congestion level representing a congestion degree in a network and performing congestion control using the effective congestion level. | 07-14-2011 |
20110179329 | APPARATUS AND METHOD FOR SETTING HYBRID AUTOMATIC REPEAT REQUEST AND AUTOMATIC REPEAT REQUEST PARAMETER IN MOBILE COMMUNICATION SYSTEM - An apparatus is capable of setting HARQ and ARQ parameters in a mobile communication system. The apparatus sets HARQ and ARQ parameters in a mobile communication system. The apparatus sets a default HARQ parameter based on the determined default HARQ parameter setting condition determined by using a plurality of QCIs. The apparatus sets a default ARQ parameter based on the determined default ARQ parameter setting condition determined by using the plurality of QCIs, and updates the set default HARQ parameter and the set default ARQ parameter according to a channel status of a UE. | 07-21-2011 |
20110182181 | METHOD AND APPARATUS FOR ADAPTIVELY MANAGING BUFFER IN COMMUNICATION SYSTEM INCLUDING A PLURALITY OF NETWORK NODES - A method and apparatus manage a buffer of a lower network node in a communication system. A current queue length of the buffer is monitored in every measurement time. A logical region in which the current queue length is included is determined, among a plurality of logical regions included in the buffer. Each of the logical regions corresponds to a queue length determined by using an upper threshold and a lower threshold of a total queue length of the buffer. A congestion state of a network is detected, and a first queue length is readjusted when the current queue length is included in the first queue length which corresponds to a first logical region that exceeds the upper threshold. And a network congestion state signal that represents the detected congestion state of the network is transmitted to the upper network node. | 07-28-2011 |
20110183672 | METHOD AND APPARATUS FOR DETERMINING HANDOVER IN MOBILE COMMUNICATION SYSTEM - A method and an apparatus of a serving base station for determining handover of a terminal in a mobile communications system are provided, including determining whether a measurement report message is received from a User Equipment (UE); when receiving the measurement report message, determining whether a channel status value of the UE satisfies a preset condition during a certain time; and determining whether to hand over the UE according to the determination result. | 07-28-2011 |
20110188377 | METHOD AND APPARATUS FOR FLOW CONTROL BETWEEN RLC AND PDCP IN A COMMUNICATION - An apparatus and a method for flow control between a Packet Data Convergence Protocol (PDCP) layer and a Radio Link Control (RLC) layer in a communication system are provided. The method includes storing Service Data Units (SDUs) to be transferred to the RLC layer, receiving information on a capacity that is currently unused in a buffer of the RLC layer from the RLC layer, and generating Packet Data Units (PDUs) from SDUs, a capacity of which corresponds to the information, among packets stored in a buffer of the PDCP layer, and then transferring the generated PDUs to the RLC layer. | 08-04-2011 |
20120155431 | APPARATUS AND METHOD FOR FORWARDING HANDOVER DATA IN WIRELESS COMMUNICATION SYSTEM - A technique forwards handover data in a wireless communication system. A base station apparatus includes a first buffer for storing downlink data of a terminal, a handover agent for, when the terminal performs a handover, performing scheduling on data which is stored in the first buffer for at least one terminal including the terminal that performs the handover so that an interruption time of the at least one terminal is reduced in order to forward the data to a target base station, and a communication unit for transmitting the data according to a scheduling result of the handover agent. | 06-21-2012 |
20130201832 | METHOD AND APPARATUS FOR CONTROLLING TRAFFIC TRANSFER RATE BASED ON CELL CAPACITY IN MOBILE COMMUNICATION SYSTEM - A system that provides a content delivery service to a user in a mobile communication system is provided. The system receives, from an enhanced Node B (eNB), cell-specific capacity information that is determined based on cell-specific load state information of the eNB, determines a transfer rate for traffic to be transmitted to a User Equipment (UE) in each cell, based on the received cell-specific capacity information, and transmits the traffic to be transmitted to the UE in each cell to the eNB at the determined transfer rate. | 08-08-2013 |
Patent application number | Description | Published |
20080297677 | DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND DISPLAY DEVICE USING THE DISPLAY SUBSTRATE - A display substrate that has increased aperture ratio is presented. The display substrate includes a base substrate, a first metal pattern formed on the base substrate and a gate wiring and a gate electrode. A first insulating layer is formed on the base substrate covering the first metal pattern. A second metal pattern is formed on the first insulating layer including a data wiring crossing the gate wiring, a source electrode connected to the data wiring and a drain electrode separated from the source electrode. A second insulating layer is formed on the base substrate covering the second metal pattern. A transparent electrode is formed on the second insulating layer. An organic layer is formed on the transparent electrode, and a pixel electrode is formed on the organic layer being insulated with the transparent electrode, and contacted to the drain electrode. The organic layer may comprise red, green and blue color filters. | 12-04-2008 |
20080316383 | METHOD FOR DETECTING STORAGE VOLTAGE, DISPLAY APPARATUS USING THE STORAGE VOLTAGE AND METHOD FOR DRIVING THE DISPLAY APPARATUS - A method for detecting a storage voltage, a display apparatus using the storage voltage and a method for driving the display apparatus. The method for detecting the storage voltage includes applying a test voltage to a storage line in a display panel having an active layer disposed between the storage line and a data line while varying the test voltage, the active layer being in an active state or an inactive state according to the test voltage, and detecting the storage voltage corresponding to the test voltage in an inactive state of the active layer. Thus, the display panel is driven by using the detected storage voltage, so that an aperture ratio may be increased and current consumption may be decreased. | 12-25-2008 |
20090009685 | POLARIZER AND LIQUID CRYSTAL DISPLAY HAVING THE SAME - A liquid crystal display includes a backlight unit, a liquid crystal display panel, and first and second polarizers. The first polarizer is attached to a lower portion of the liquid crystal display panel to face the backlight unit, and the second polarizer is attached to an upper portion of the liquid crystal display panel to correspond to the first polarizer. The liquid crystal display panel includes a first optical layer that partially reflects light provided from the backlight unit, and the first polarizer includes a second optical layer to prevent the light reflected by the first optical layer from being re-reflected to the liquid crystal display panel. | 01-08-2009 |
20090290086 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF REPAIRING BAD PIXELS THEREIN - A liquid crystal display device and a method of repairing bad pixels thereof, in which the bad pixels can be efficiently and easily repaired, includes a first insulating substrate, a gate wiring and a storage wiring arranged substantially parallel to each other in a first direction on the first insulating substrate, a data wiring intersecting the gate and storage wirings in an insulated manner and arranged substantially in a second direction, and a pixel electrode formed on a pixel area defined by the gate and data wirings. The storage wiring includes a horizontal portion arranged substantially in the first direction and at least a part of which does not overlap the pixel electrode, and a vertical portion branching off substantially in the second direction from the horizontal portion and overlapping the data wiring. | 11-26-2009 |
20110096449 | Substrate for a Display Device and Method of Manufacturing the Same - A mother substrate for a display device includes a display cell, a test pad, an electrostatic preventing pattern and a connecting line. The display cell includes a pad and a signal line. The signal line is extended from the pad and is electrically connected to a pixel. The test pad is disposed out of the display cell and is electrically connected to the signal line of the display cell and receives a test signal. The electrostatic preventing pattern electrically connected to the test pad is disposed adjacent to the test pad and includes a plurality of edges. The electrostatic preventing pattern is formed from a metal pattern. The connecting line is extended from the electrostatic preventing pattern and is electrically connected to the pad of the display cell. | 04-28-2011 |
20110317107 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF REPAIRING BAD PIXELS THEREIN - A liquid crystal display device and a method of repairing bad pixels thereof, in which the bad pixels can be efficiently and easily repaired, includes a first insulating substrate, a gate wiring and a storage wiring arranged substantially parallel to each other in a first direction on the first insulating substrate, a data wiring intersecting the gate and storage wirings in an insulated manner and arranged substantially in a second direction, and a pixel electrode formed on a pixel area defined by the gate and data wirings. The storage wiring includes a horizontal portion arranged substantially in the first direction and at least a part of which does not overlap the pixel electrode, and a vertical portion branching off substantially in the second direction from the horizontal portion and overlapping the data wiring. | 12-29-2011 |
20130294004 | SUBSTRATE FOR A DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A mother substrate for a display device includes a display cell, a test pad, an electrostatic preventing pattern and a connecting line. The display cell includes a pad and a signal line. The signal line is extended from the pad and is electrically connected to a pixel. The test pad is disposed out of the display cell and is electrically connected to the signal line of the display cell and receives a test signal. The electrostatic preventing pattern electrically connected to the test pad is disposed adjacent to the test pad and includes a plurality of edges. The electrostatic preventing pattern is formed from a metal pattern. The connecting line is extended from the electrostatic preventing pattern and is electrically connected to the pad of the display cell. | 11-07-2013 |
Patent application number | Description | Published |
20110079897 | INTEGRATED CIRCUIT CHIP AND FLIP CHIP PACKAGE HAVING THE INTEGRATED CIRCUIT CHIP - In an integrated circuit (IC) chip and a flip chip package having the same, no wiring line is provided and the first electrode pad does not make contact with the wiring line in a pad area of the IC chip. Thus, the first bump structure makes contact with the first electrode regardless of the wiring line in the pad area. The second electrode pad makes contact with the wiring line in a pseudo pad area of the IC chip. Thus, the second bump structure in the pseudo pad area makes contact with an upper surface of the second electrode at a contact point(s) spaced apart from the wiring line under the second electrode. | 04-07-2011 |
20110169173 | WIRING SUBSTRATE FOR A SEMICONDUCTOR CHIP AND SEMICONDUCOTOR PACKAGE HAVING THE WIRING SUBSTRATE - A wiring substrate for a semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface. The substrate has at least one slot from the first surface to the second surface that exposes chip pads of a semiconductor chip mounted to the first surface. The substrate has first and second regions divided by the slot. A plurality of bonding pads is arranged along both side portions of the slot and the bonding pads are connected to bonding wires that are drawn from the chip pads through the slot. First and second conductive patterns are respectively formed in the first and second regions and respectively connected to the at least one bonding pad. A merging pattern extends from the first region to the second region to electrically connect the first conductive pattern and the second conductive pattern. A merging wire electrically connects the merging pattern and the at least one chip pad. | 07-14-2011 |
20110187406 | Semiconductor Chip And Semiconductor Module Including The Semiconductor Chip - A semiconductor chip including a termination resistance and a semiconductor module including the semiconductor chip. The semiconductor chip comprising a plurality of memory cells, the semiconductor chip including: at least one first center pads disposed on a center region of the semiconductor chip and connected to the plurality of memory cells; at least one first edge pads disposed on an edge region of the semiconductor chip and connected to a first transmission line of a semiconductor module; at least one second edge pads disposed on the edge region of the semiconductor chip and connected to a chipset voltage application unit of the semiconductor module; at least one first redistribution patterns connected between the at least one first center pads and the at least one first edge pads; and at least one second redistribution patterns connected between the at least one first edge pads and the at least one second edge pads, wherein an impedance of the at least one second redistribution patterns is impedance matched to an impedance of the first transmission line. | 08-04-2011 |
20110283034 | SEMICONDUCTOR CHIP, AND SEMICONDUCTOR PACKAGE AND SYSTEM EACH INCLUDING THE SEMICONDUCTOR CHIP - A semiconductor chip includes a redistribution interconnect that is implemented by shorting bumps, and a semiconductor package and a system each including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a passivation film disposed on the semiconductor substrate, and a plurality of pseudo bumps disposed on the passivation film. Each pseudo bump is directly connected to adjacent pseudo bumps to form at least one redistribution interconnect. | 11-17-2011 |
20130088838 | DIE PACKAGE, METHOD OF MANUFACTURING THE SAME, AND SYSTEMS INCLUDING THE SAME - A die package includes a substrate, a die mounted on the substrate, and a ZQ resistor disposed in the die package and connected to the substrate and the die. The ZQ resistor may be used to calibrate impedance of the die. | 04-11-2013 |
20130168842 | INTEGRATED CIRCUIT PACKAGES HAVING REDISTRIBUTION STRUCTURES - A semiconductor package includes a semiconductor chip stack disposed between first and second leads near first and second sides of the package and including a plurality of semiconductor chips, and a redistribution structure disposed on the semiconductor chip stack. At least one semiconductor chip of the semiconductor chip stack includes a plurality of first chip pads disposed near or closer to a third side of the package. The redistribution structure includes a first redistribution pad disposed near or closer to the first side and electrically connected to the first lead, a second redistribution pad disposed near or closer to the second side and electrically connected to the second lead, and a third redistribution pad disposed near or closer to the third side and electrically connected to a first one of the first chip pads and the first redistribution pad. | 07-04-2013 |
20130292846 | SEMICONDUCTOR PACKAGE - Provided is a semiconductor package including a first semiconductor chip and a second semiconductor chip respectively disposed at a bottom and at a top so that active surfaces thereof face each other. Further includes is a first molding member for sealing the first semiconductor chip and exposing the active surface of the first semiconductor chip through a top surface, a first rewiring formed on the top surface of the first molding member and the active surface of the first semiconductor chip, a second rewiring formed on a bottom surface of the first molding member, a through-via for penetrating through the first molding member and electrically connecting the first and second rewirings, and a first connection member disposed between the first and second semiconductor chips. Also provided are various systems including same and various methods for making same. | 11-07-2013 |
20140339704 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate; and first and second semiconductor chips sequentially disposed on the substrate so that active surfaces of the first and second semiconductor chips face each other, wherein the first and second semiconductor chips are center pad-type semiconductor chips each having I/O pads arranged in two columns to be adjacent to a central line thereof, and I/O pads of the second semiconductor chip are electrically connected directly to the substrate without intersecting the central line of the second semiconductor chip. | 11-20-2014 |
Patent application number | Description | Published |
20100001379 | Multi-chip package (MCP) having three dimensional mesh-based power distribution network, and power distribution method of the MCP - A MCP includes a plurality of semiconductor memory devices, the plurality of semiconductor memory devices being stacked to define a three-dimensional (3D) structure, and a mesh structure, the mesh structure interconnecting the plurality of semiconductor memory devices to define a 3D mesh-based power distribution network. | 01-07-2010 |
20100020583 | Stacked memory module and system - A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system. | 01-28-2010 |
20100177572 | SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING PAGE SIZE - A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device. | 07-15-2010 |
20110249483 | STACKED MEMORY DEVICE HAVING INTER-CHIP CONNECTION UNIT, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF COMPENSATING FOR DELAY TIME OF TRANSMISSION LINE - A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip. | 10-13-2011 |
20110292708 | 3D SEMICONDUCTOR DEVICE - A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked. | 12-01-2011 |
20110298130 | SEMICONDUCTOR DEVICES WITH THROUGH-SILICON VIAS - Through silicon vias (TSVs) include a first metal plug having a cylindrical shape, passing through a semiconductor substrate, and with an outer peripheral surface surrounded by a first insulating film; an isolated semiconductor substrate in the semiconductor substrate and surrounding a first metal plug surrounded by a first insulating film; and a second metal plug surrounding the isolated semiconductor substrate and being surrounded by a second insulating film. A first bias voltage is applied to the isolated semiconductor substrate so that a depletion layer is formed in the isolated semiconductor substrate from an interface between the isolated semiconductor substrate and the first insulating film. The first bias voltage is different from a second bias voltage applied to the semiconductor substrate, which is a main semiconductor substrate, with a device forming area where transistors constituting circuits are formed. | 12-08-2011 |
20110310649 | Stacked Memory Module and System - A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system. | 12-22-2011 |
20120059984 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor package is disclosed. The semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential signal providing first information, and includes an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias. | 03-08-2012 |
20120086125 | Semiconductor Having Chip Stack, Semiconductor System, and Method of Fabricating the Semiconductor Apparatus - In one embodiment, a semiconductor device includes a plurality of semiconductor chip stacks mounted on a substrate. Bonding terminals disposed on the substrate correspond to the chip stacks, such that at least one chip in each chip stack may be directly connected to a bonding terminal on the substrate and at least one chip in the chip stack is not directly connected to the bonding terminal. The semiconductor chip stacks may each act as one semiconductor device to the outside. | 04-12-2012 |
20120138927 | SEMICONDUCTOR DEVICE HAVING STACKED STRUCTURE INCLUDING THROUGH-SILICON-VIAS AND METHOD OF TESTING THE SAME - A semiconductor device having a stacked structure including through-silicon-vias (TSVs) and a method of testing the semiconductor device. The semiconductor device includes a first semiconductor layer, one or more second semiconductor layers stacked on the first semiconductor layer, and a plurality of input through-silicon-vias (TSVs) to transmit signals from a plurality of input pads, respectively. In a test mode, a test signal from the plurality of input pads is transmitted through at least two test paths, and the test signal transmitted through each of the test paths is output as a test result with respect to each of the plurality of input TSVs through an output pad. | 06-07-2012 |
20120300528 | Stacked Memory Module and System - A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system. | 11-29-2012 |
20120317352 | Method and Apparatus for Refreshing and Data Scrubbing Memory Device - At least one refresh without scrubbing is performed on a corresponding portion of the memory device with a first frequency. In addition, at least one refresh with scrubbing is performed on a corresponding portion of the memory device with a second frequency less than the first frequency. Accordingly, refresh operations with data scrubbing are performed to prevent data error accumulation. Furthermore, refresh operations without data scrubbing are also performed to reduce undue power consumption from the data scrubbing. | 12-13-2012 |
20130039135 | MEMORY DEVICE FOR MANAGING TIMING PARAMETERS - A method of performing write operations in a memory device including a plurality of banks is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types. | 02-14-2013 |
20130055048 | BAD PAGE MANAGEMENT IN MEMORY DEVICE OR SYSTEM - A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information. | 02-28-2013 |
20130058145 | MEMORY SYSTEM - A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells. | 03-07-2013 |
20140085999 | SEMICONDUCTOR MEMORY DEVICE HAVING ADJUSTABLE REFRESH PERIOD, MEMORY SYSTEM COMPRISING SAME, AND METHOD OF OPERATING SAME - A semiconductor memory device comprises a cell array comprising a plurality of cell regions, a row decoder configured to drive rows corresponding to cell regions in which a refresh operation is to be performed, based on a counting address, and a refresh address generator configured to generate the counting address and a modified address in response to a control signal, wherein the modified address is generated by inverting at least one bit of the counting address, and wherein the semiconductor memory device performs concurrent refresh operations on a first cell region corresponding to the counting address and a second cell region corresponding to the modified address where the second cell region is determined to have weak cells. | 03-27-2014 |
20140140153 | REPAIR CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A repair control circuit of controlling a repair operation of a semiconductor memory device includes a row matching block and a column matching block. The row matching block stores fail group information indicating one or more fail row groups among a plurality of row groups. The row groups are determined by grouping a plurality of row addresses corresponding to a plurality of wordlines. The row matching block generates a group match signal based on input row address and the fail group information, such that the group match signal indicates the fail row group including the input row address. The column matching block stores fail column addresses of the fail memory cells, and generates a repair control signal based on input column address, the group match signal and the fail column addresses, such that the repair control signal indicates whether the repair operation is executed or not. | 05-22-2014 |
20140146624 | MEMORY MODULES AND MEMORY SYSTEMS - In one example embodiment, a memory module includes a plurality of memory devices and a buffer chip configured to manage the plurality of memory device. The buffer chip includes a memory management unit having an error correction unit configured to perform error correction operation on each of the plurality of memory devices. Each of the plurality of memory devices includes at least one spare column that is accessible by the memory management unit, and the memory management unit is configured to correct errors of the plurality of memory devices by selectively using the at least one spare column based on an error correction capability of the error correction unit. | 05-29-2014 |
20140189215 | MEMORY MODULES AND MEMORY SYSTEMS - A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices. The buffer chip includes a refresh control circuit that groups a plurality of memory cell rows of the memory devices into a plurality of groups according to a data retention time of tire memory cell rows. The buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality of groups, respectively. | 07-03-2014 |
20140233292 | 3D SEMICONDUCTOR DEVICE - A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked. | 08-21-2014 |
20140247677 | METHOD OF ACCESSING SEMICONDUCTOR MEMORY AND SEMICONDUCTOR CIRCUIT - A method of accessing a semiconductor memory is disclosed which includes outputting a row address and an active command to the semiconductor memory; outputting a column address and a read or write command to the semiconductor memory; and outputting a spare access command to the semiconductor memory to access data from a spare memory cell at a timing based on an additive latency of the semiconductor memory. Related devices and systems are also disclosed. | 09-04-2014 |
20140359242 | MEMORY DEVICE WITH RELAXED TIMING PARAMETER ACCORDING TO TEMPERATURE, OPERATING METHOD THEREOF, AND MEMORY CONTROLLER AND MEMORY SYSTEM USING THE MEMORY DEVICE - A memory device used with a relaxed timing requirement specification according to temperatures, an operation method thereof, and a memory controller and a memory system using the memory device are provided. The memory device has a first timing characteristic at a first temperature and a second timing characteristic that is longer than the first timing characteristic at a second temperature. If a temperature of the memory device is higher than a reference temperature, the memory controller controls the first timing characteristic as a timing requirement specification of the memory device. If the temperature of the memory device is lower than the reference temperature, the memory controller controls the second timing characteristic as the timing requirement specification of the memory device. | 12-04-2014 |
20150067448 | METHOD OF OPERATING MEMORY DEVICE AND METHODS OF WRITING AND READING DATA IN MEMORY DEVICE - In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word. | 03-05-2015 |
Patent application number | Description | Published |
20090155692 | SURFACE TREATED ANODE ACTIVE MATERIAL AND METHOD OF MAKING THE SAME, ANODE INCLUDING THE SAME, AND LITHIUM BATTERY INCLUDING THE SAME - An anode includes a collector; and an anode active material layer disposed on the collector comprises an anode active material, which is lithium oxide coated Li | 06-18-2009 |
20090191464 | ORGANIC ELECTROLYTIC SOLUTION COMPRISING CYCLOOLEFIN MONOMER AND LITHIUM BATTERY EMPLOYING THE SAME - An organic electrolytic solution includes a lithium salt; an organic solvent containing a high dielectric constant solvent; and a polymerizable cycloolefin monomer, and an lithium battery employing the same. The organic electrolytic solution prevents decomposition of an electrolyte, and thus the lithium battery employing the organic electrolytic solution has improved cycle characteristics and lifetime. | 07-30-2009 |
20100143804 | ANODE ACTIVE MATERIAL FOR LITHIUM SECONDARY BATTERY, METHOD OF MANUFACTURING THE SAME, AND LITHIUM SECONDARY BATTERY INCLUDING THE ANODE ACTIVE MATERIAL - An anode active material includes a material alloyable with lithium coated with an oxide including lithium or coated with a complex of an oxide including lithium and an electrically conductive material. An anode of a lithium secondary battery includes the anode active material. | 06-10-2010 |
20120100439 | ELECTROLYTE SOLUTION FOR SECONDARY LITHIUM BATTERY AND SECONDARY LITHIUM BATTERY INCLUDING THE ELECTROLYTE SOLUTION - An electrolyte solution for a secondary lithium battery, the electrolyte solution including: a lithium salt, a non-aqueous organic solvent, and a phenanthroline-based compound having a polar substituent. The electrolyte solution enables production of a secondary lithium battery having good high-temperature lifetime characteristics and good high-temperature preservation characteristics. | 04-26-2012 |
20120121990 | ELECTROLYTE FOR LITHIUM SECONDARY BATTERY AND LITHIUM SECONDARY BATTERY INCLUDING THE SAME - An electrolyte for a lithium secondary battery, the electrolyte comprising: a lithium salt, a non-aqueous organic solvent, and an additive represented by Formula 1 below: | 05-17-2012 |
20120251892 | ELECTROLYTE FOR LITHIUM SECONDARY BATTERY AND LITHIUM SECONDARY BATTERY INCLUDING THE SAME - An electrolyte for a lithium secondary battery including a lithium salt, a nonaqueous organic solvent, and an additive, in which the additive is composed of one or more compounds including a purinone or a purinone derivative. The lithium secondary battery with improved life and high-temperature storage may be provided by using the electrolyte for a lithium secondary battery according to an embodiment of the present invention. | 10-04-2012 |
20120251895 | ELECTROLYTE FOR LITHIUM SECONDARY BATTERY AND LITHIUM SECONDARY BATTERY INCLUDING THE SAME - An electrolyte for a lithium secondary battery, the electrolyte including a lithium salt, a non-aqueous organic solvent, and an additive represented by Formula 1 below: | 10-04-2012 |
20130078533 | ELECTROLYTE FOR LITHIUM SECONDARY BATTERY AND LITHIUM SECONDARY BATTERY INCLUDING THE SAME - An electrolyte for a lithium secondary battery, the electrolyte including a lithium salt, a non-aqueous organic solvent, and a polar additive based on a substituted hetero-bicyclic compound. Oxidation of the electrolyte is prevented by formation of a polar thin film on a surface portion of the positive electrode, which facilitates transfer of lithium ions. The lithium secondary batteries using the electrolyte have excellent high temperature life characteristics and high temperature conservation characteristics. | 03-28-2013 |
20140377655 | COMPOSITE CATHODE ACTIVE MATERIAL, METHOD OF PREPARING THE COMPOSITE CATHODE ACTIVE MATERIAL, AND CATHODE AND LITHIUM BATTERY EACH INCLUDING THE COMPOSITE CATHODE ACTIVE MATERIAL - A composite cathode active material, a method of preparing the composite cathode active material, a cathode including the composite cathode active material, and a lithium battery including the cathode. The composite cathode active material includes a lithium intercalatable material; and a garnet oxide, wherein an amount of the garnet oxide is about 1.9 wt % or less, based on a total weight of the composite cathode active material. | 12-25-2014 |
20150064578 | ELECTROLYTE FOR LITHIUM SECONDARY BATTERY AND LITHIUM SECONDARY BATTERY USING THE SAME - An electrolyte for a lithium secondary battery, the electrolyte including: a lithium salt; a non-aqueous organic solvent; and a piperazine derivative represented by Formula 1 having an oxidation potential lower than an oxidation potential of the non-aqueous organic solvent by about 2 V to about 4 V: | 03-05-2015 |
20150079465 | COMPOSITE CATHODE ACTIVE MATERIAL, METHOD OF PREPARING THE SAME, AND CATHODE AND LITHIUM BATTERY CONTAINING THE SAME - A composite cathode active material including a lithium metal oxide including an oxide Formula 1 and sulfur, | 03-19-2015 |