Patent application number | Description | Published |
20120317153 | CACHING RESPONSES FOR SCOPED AND NON-SCOPED DOMAIN NAME SYSTEM QUERIES - In the described embodiments, while executing a DNS resolver, a processing subsystem in an electronic device with a set of network interfaces receives a scoped request from an application to determine an IP address for a domain name. Generally, a DNS query generated from a scoped request is to be transmitted only on network interfaces specified in the scoped request, whereas a DNS query generated from a non-scoped request can be transmitted on any of the network interfaces. The processing subsystem then generates a DNS query from the scoped request and transmits the DNS query on the specified network interfaces. Upon receiving a response to the DNS query, the processing subsystem stores a record of the response in a scoped portion of a DNS resolution cache that is used only for storing responses to scoped requests. The DNS resolution cache also comprises a non-scoped portion that is used only for storing responses to non-scoped requests. | 12-13-2012 |
20140244996 | PRIVATE DISCOVERY OF ELECTRONIC DEVICES - The disclosed embodiments provide a system that facilitates communication between a first electronic device and a second electronic device. During operation, the system uses the first electronic device to create a discovery request comprising a first group identifier (ID) associated with the first electronic device, wherein using the first electronic device to create the discovery request involves encrypting the first group ID and including the encrypted first group ID in the discovery request. Next, the system transmits the discovery request to the second electronic device, wherein the discovery request is used by the second electronic device to generate a discovery response to the discovery request. | 08-28-2014 |
20150350087 | CONSISTENT HASHING FOR NETWORK TRAFFIC DISPATCHING - A method is provided that uses a consistent hashing technique to dispatch incoming packets in a stable system prior to adding of a node. The method uses a hash table and assigns hash buckets in the table to each network node. A set of fields in each incoming packet is hashed and is used to identify the corresponding hash bucket. The packets are then dispatched to the network nodes based on the nodes' hash buckets. During an observation period, the method identifies the ongoing sessions by creating a bit vector table that is used to identify the old and new sessions during a re-dispatching period. The method uses the consistent hashing method and the probabilistic method dispatch the incoming packets such that each packet that belongs to an old session is dispatched to the same old node that has been processing the other packets of the session. | 12-03-2015 |
20150358288 | USE OF STATELESS MARKING TO SPEED UP STATEFUL FIREWALL RULE PROCESSING - A novel method for stateful packet classification that uses hardware resources for performing stateless lookups and software resources for performing stateful connection flow handshaking is provided. To classify an incoming packet from a network, some embodiments perform stateless look up operations for the incoming packet in hardware and forward the result of the stateless look up to the software. The software in turn uses the result of the stateless look up to perform the stateful connection flow handshaking and to determine the result of the stateful packet classification. | 12-10-2015 |
20150358290 | USE OF STATELESS MARKING TO SPEED UP STATEFUL FIREWALL RULE PROCESSING - A novel method for stateful packet classification that uses hardware resources for performing stateless lookups and software resources for performing stateful connection flow handshaking is provided. To classify an incoming packet from a network, some embodiments perform stateless look up operations for the incoming packet in hardware and forward the result of the stateless look up to the software. The software in turn uses the result of the stateless look up to perform the stateful connection flow handshaking and to determine the result of the stateful packet classification. | 12-10-2015 |
20150358433 | EFFICIENT PACKET CLASSIFICATION FOR DYNAMIC CONTAINERS - A novel algorithm for packet classification that is based on a novel search structure for packet classification rules is provided. Addresses from all the containers are merged and maintained in a single Trie. Each entry in the Trie has additional information that can be traced back to the container from where the address originated. This information is used to keep the Trie in sync with the containers when the container definition dynamically changes. | 12-10-2015 |
20150358434 | EFFICIENT PACKET CLASSIFICATION FOR DYNAMIC CONTAINERS - A novel algorithm for packet classification that is based on a novel search structure for packet classification rules is provided. Addresses from all the containers are merged and maintained in a single Trie. Each entry in the Trie has additional information that can be traced back to the container from where the address originated. This information is used to keep the Trie in sync with the containers when the container definition dynamically changes. | 12-10-2015 |
20150370723 | System, Apparatus and Method for Prioritizing the Storage of Content Based on a Threat Index - A network sensor that features a data store and a packet processing engine. Communicatively coupled to the data store, the packet processing engine is configured to (i) generate a retention priority for at least a first flow within a first storage region of a plurality of storage regions and (ii) identify, in response to an eviction request, the priority of each of the plurality of storage regions. The priority of the first storage region is partially based on the retention priority associated with the first flow while the priority of a second storage region is based on retention priorities associated with flows stored within the second storage region. The packet processing engine also is configured to identify, through use of the retention priorities of the stored flows within the first storage region, which flows are to be retained and which flows are to be evicted. | 12-24-2015 |
20150372910 | System, Apparatus and Method for Managing Redundancy Elimination in Packet Storage During Observation of Data Movement - A network sensor that features a data store and a packet processing engine. In communication with the data store, the packet processing engine comprises (1) a cache management logic and (2) deduplication logic. The cache management logic is configured to analyze packets to determine whether (a) a packet under analysis include duplicated data and (b) content of the packet is targeted for storage in a same continuous logical storage area as the duplicated data. The deduplication logic, when activated by the cache management logic, is configured to generate a deduplication reference for insertion into the packet prior to storage. | 12-24-2015 |
20160094389 | ELASTICALLY MANAGING A SERVICE NODE GROUP - Some embodiments provide an elastic architecture for providing a service in a computing system. To perform a service on the data messages, the service architecture uses a service node (SN) group that includes one primary service node (PSN) and zero or more secondary service nodes (SSNs). The service can be performed on a data message by either the PSN or one of the SSN. However, in addition to performing the service, the PSN also performs a load balancing operation that assesses the load on each service node (i.e., on the PSN or each SSN), and based on this assessment, has the data messages distributed to the service node(s) in its SN group. Based on the assessed load, the PSN in some embodiments also has one or more SSNs added to or removed from its SN group. To add or remove an SSN to or from the service node group, the PSN in some embodiments directs a set of controllers to add (e.g., instantiate or allocate) or remove the SSN to or from the SN group. Also, to assess the load on the service nodes, the PSN in some embodiments receives message load data from the controller set, which collects such data from each service node. In other embodiments, the PSN receives such load data directly from the SSNs. | 03-31-2016 |
20160094451 | INLINE LOAD BALANCING - Some embodiments provide a novel method for load balancing data messages that are sent by a source compute node (SCN) to one or more different groups of destination compute nodes (DCNs). In some embodiments, the method deploys a load balancer in the source compute node's egress datapath. This load balancer receives each data message sent from the source compute node, and determines whether the data message is addressed to one of the DCN groups for which the load balancer spreads the data traffic to balance the load across (e.g., data traffic directed to) the DCNs in the group. When the received data message is not addressed to one of the load balanced DCN groups, the load balancer forwards the received data message to its addressed destination. On the other hand, when the received data message is addressed to one of load balancer's DCN groups, the load balancer identifies a DCN in the addressed DCN group that should receive the data message, and directs the data message to the identified DCN. To direct the data message to the identified DCN, the load balancer in some embodiments changes the destination address (e.g., the destination IP address, destination port, destination MAC address, etc.) in the data message from the address of the identified DCN group to the address (e.g., the destination IP address) of the identified DCN. | 03-31-2016 |
20160094452 | DISTRIBUTED LOAD BALANCING SYSTEMS - Some embodiments provide a novel method for load balancing data messages that are sent by a source compute node (SCN) to one or more different groups of destination compute nodes (DCNs). In some embodiments, the method deploys a load balancer in the source compute node's egress datapath. This load balancer receives each data message sent from the source compute node, and determines whether the data message is addressed to one of the DCN groups for which the load balancer spreads the data traffic to balance the load across (e.g., data traffic directed to) the DCNs in the group. When the received data message is not addressed to one of the load balanced DCN groups, the load balancer forwards the received data message to its addressed destination. On the other hand, when the received data message is addressed to one of load balancer's DCN groups, the load balancer identifies a DCN in the addressed DCN group that should receive the data message, and directs the data message to the identified DCN. To direct the data message to the identified DCN, the load balancer in some embodiments changes the destination address (e.g., the destination IP address, destination port, destination MAC address, etc.) in the data message from the address of the identified DCN group to the address (e.g., the destination IP address) of the identified DCN. | 03-31-2016 |
20160094453 | LOAD BALANCER OF LOAD BALANCERS - Some embodiments provide an elastic architecture for providing a service in a computing system. To perform a service on the data messages, the service architecture uses a service node (SN) group that includes one primary service node (PSN) and zero or more secondary service nodes (SSNs). The service can be performed on a data message by either the PSN or one of the SSN. However, in addition to performing the service, the PSN also performs a load balancing operation that assesses the load on each service node (i.e., on the PSN or each SSN), and based on this assessment, has the data messages distributed to the service node(s) in its SN group. Based on the assessed load, the PSN in some embodiments also has one or more SSNs added to or removed from its SN group. To add or remove an SSN to or from the service node group, the PSN in some embodiments directs a set of controllers to add (e.g., instantiate or allocate) or remove the SSN to or from the SN group. Also, to assess the load on the service nodes, the PSN in some embodiments receives message load data from the controller set, which collects such data from each service node. In other embodiments, the PSN receives such load data directly from the SSNs. | 03-31-2016 |
20160094454 | METHOD AND APPARATUS FOR PROVIDING A SERVICE WITH A PLURALITY OF SERVICE NODES - Some embodiments provide an elastic architecture for providing a service in a computing system. To perform a service on the data messages, the service architecture uses a service node (SN) group that includes one primary service node (PSN) and zero or more secondary service nodes (SSNs). The service can be performed on a data message by either the PSN or one of the SSN. However, in addition to performing the service, the PSN also performs a load balancing operation that assesses the load on each service node (i.e., on the PSN or each SSN), and based on this assessment, has the data messages distributed to the service node(s) in its SN group. Based on the assessed load, the PSN in some embodiments also has one or more SSNs added to or removed from its SN group. To add or remove an SSN to or from the service node group, the PSN in some embodiments directs a set of controllers to add (e.g., instantiate or allocate) or remove the SSN to or from the SN group. Also, to assess the load on the service nodes, the PSN in some embodiments receives message load data from the controller set, which collects such data from each service node. In other embodiments, the PSN receives such load data directly from the SSNs. | 03-31-2016 |
20160094455 | METHOD AND APPARATUS FOR DISTRIBUTING LOAD AMONG A PLURALITY OF SERVICE NODES - Some embodiments provide an elastic architecture for providing a service in a computing system. To perform a service on the data messages, the service architecture uses a service node (SN) group that includes one primary service node (PSN) and zero or more secondary service nodes (SSNs). The service can be performed on a data message by either the PSN or one of the SSN. However, in addition to performing the service, the PSN also performs a load balancing operation that assesses the load on each service node (i.e., on the PSN or each SSN), and based on this assessment, has the data messages distributed to the service node(s) in its SN group. Based on the assessed load, the PSN in some embodiments also has one or more SSNs added to or removed from its SN group. To add or remove an SSN to or from the service node group, the PSN in some embodiments directs a set of controllers to add (e.g., instantiate or allocate) or remove the SSN to or from the SN group. Also, to assess the load on the service nodes, the PSN in some embodiments receives message load data from the controller set, which collects such data from each service node. In other embodiments, the PSN receives such load data directly from the SSNs. | 03-31-2016 |
20160094456 | METHOD AND APPARATUS FOR DISTRIBUTING LOAD AMONG A PLURALITY OF SERVICE NODES - Some embodiments provide an elastic architecture for providing a service in a computing system. To perform a service on the data messages, the service architecture uses a service node (SN) group that includes one primary service node (PSN) and zero or more secondary service nodes (SSNs). The service can be performed on a data message by either the PSN or one of the SSN. However, in addition to performing the service, the PSN also performs a load balancing operation that assesses the load on each service node (i.e., on the PSN or each SSN), and based on this assessment, has the data messages distributed to the service node(s) in its SN group. Based on the assessed load, the PSN in some embodiments also has one or more SSNs added to or removed from its SN group. To add or remove an SSN to or from the service node group, the PSN in some embodiments directs a set of controllers to add (e.g., instantiate or allocate) or remove the SSN to or from the SN group. Also, to assess the load on the service nodes, the PSN in some embodiments receives message load data from the controller set, which collects such data from each service node. In other embodiments, the PSN receives such load data directly from the SSNs. | 03-31-2016 |
20160094457 | Tunnel-Enabled Elastic Service Model - Some embodiments provide novel inline switches that distribute data messages from source compute nodes (SCNs) to different groups of destination service compute nodes (DSCNs). In some embodiments, the inline switches are deployed in the source compute nodes datapaths (e.g., egress datapath). The inline switches in some embodiments are service switches that (1) receive data messages from the SCNs, (2) identify service nodes in a service-node cluster for processing the data messages based on service policies that the switches implement, and (3) use tunnels to send the received data messages to their identified service nodes. Alternatively, or conjunctively, the inline service switches of some embodiments (1) identify service-nodes cluster for processing the data messages based on service policies that the switches implement, and (2) use tunnels to send the received data messages to the identified service-node clusters. The service-node clusters can perform the same service or can perform different services in some embodiments. This tunnel-based approach for distributing data messages to service nodes/clusters is advantageous for seamlessly implementing in a datacenter a cloud-based XaaS model (where XaaS stands for X as a service, and X stands for anything), in which any number of services are provided by service providers in the cloud. | 03-31-2016 |
20160094631 | DYNAMICALLY ADJUSTING A DATA COMPUTE NODE GROUP - Some embodiments provide a novel method for load balancing data messages that are sent by a source compute node (SCN) to one or more different groups of destination compute nodes (DCNs). In some embodiments, the method deploys a load balancer in the source compute node's egress datapath. This load balancer receives each data message sent from the source compute node, and determines whether the data message is addressed to one of the DCN groups for which the load balancer spreads the data traffic to balance the load across (e.g., data traffic directed to) the DCNs in the group. When the received data message is not addressed to one of the load balanced DCN groups, the load balancer forwards the received data message to its addressed destination. On the other hand, when the received data message is addressed to one of load balancer's DCN groups, the load balancer identifies a DCN in the addressed DCN group that should receive the data message, and directs the data message to the identified DCN. To direct the data message to the identified DCN, the load balancer in some embodiments changes the destination address (e.g., the destination IP address, destination port, destination MAC address, etc.) in the data message from the address of the identified DCN group to the address (e.g., the destination IP address) of the identified DCN. | 03-31-2016 |
20160094632 | Inline Service Switch - Some embodiments provide novel inline switches that distribute data messages from source compute nodes (SCNs) to different groups of destination service compute nodes (DSCNs). In some embodiments, the inline switches are deployed in the source compute nodes datapaths (e.g., egress datapath). The inline switches in some embodiments are service switches that (1) receive data messages from the SCNs, (2) identify service nodes in a service-node cluster for processing the data messages based on service policies that the switches implement, and (3) use tunnels to send the received data messages to their identified service nodes. Alternatively, or conjunctively, the inline service switches of some embodiments (1) identify service-nodes cluster for processing the data messages based on service policies that the switches implement, and (2) use tunnels to send the received data messages to the identified service-node clusters. The service-node clusters can perform the same service or can perform different services in some embodiments. This tunnel-based approach for distributing data messages to service nodes/clusters is advantageous for seamlessly implementing in a datacenter a cloud-based XaaS model (where XaaS stands for X as a service, and X stands for anything), in which any number of services are provided by service providers in the cloud. | 03-31-2016 |
20160094633 | Configuring and Operating a XaaS Model in a Datacenter - Some embodiments provide novel inline switches that distribute data messages from source compute nodes (SCNs) to different groups of destination service compute nodes (DSCNs). In some embodiments, the inline switches are deployed in the source compute nodes datapaths (e.g., egress datapath). The inline switches in some embodiments are service switches that (1) receive data messages from the SCNs, (2) identify service nodes in a service-node cluster for processing the data messages based on service policies that the switches implement, and (3) use tunnels to send the received data messages to their identified service nodes. Alternatively, or conjunctively, the inline service switches of some embodiments (1) identify service-nodes cluster for processing the data messages based on service policies that the switches implement, and (2) use tunnels to send the received data messages to the identified service-node clusters. The service-node clusters can perform the same service or can perform different services in some embodiments. This tunnel-based approach for distributing data messages to service nodes/clusters is advantageous for seamlessly implementing in a datacenter a cloud-based XaaS model (where XaaS stands for X as a service, and X stands for anything), in which any number of services are provided by service providers in the cloud. | 03-31-2016 |
20160094642 | DYNAMICALLY ADJUSTING LOAD BALANCING - Some embodiments provide a novel method for load balancing data messages that are sent by a source compute node (SCN) to one or more different groups of destination compute nodes (DCNs). In some embodiments, the method deploys a load balancer in the source compute node's egress datapath. This load balancer receives each data message sent from the source compute node, and determines whether the data message is addressed to one of the DCN groups for which the load balancer spreads the data traffic to balance the load across (e.g., data traffic directed to) the DCNs in the group. When the received data message is not addressed to one of the load balanced DCN groups, the load balancer forwards the received data message to its addressed destination. On the other hand, when the received data message is addressed to one of load balancer's DCN groups, the load balancer identifies a DCN in the addressed DCN group that should receive the data message, and directs the data message to the identified DCN. To direct the data message to the identified DCN, the load balancer in some embodiments changes the destination address (e.g., the destination IP address, destination port, destination MAC address, etc.) in the data message from the address of the identified DCN group to the address (e.g., the destination IP address) of the identified DCN. | 03-31-2016 |
20160094643 | DYNAMICALLY ADJUSTING LOAD BALANCING - Some embodiments provide a novel method for load balancing data messages that are sent by a source compute node (SCN) to one or more different groups of destination compute nodes (DCNs). In some embodiments, the method deploys a load balancer in the source compute node's egress datapath. This load balancer receives each data message sent from the source compute node, and determines whether the data message is addressed to one of the DCN groups for which the load balancer spreads the data traffic to balance the load across (e.g., data traffic directed to) the DCNs in the group. When the received data message is not addressed to one of the load balanced DCN groups, the load balancer forwards the received data message to its addressed destination. On the other hand, when the received data message is addressed to one of load balancer's DCN groups, the load balancer identifies a DCN in the addressed DCN group that should receive the data message, and directs the data message to the identified DCN. To direct the data message to the identified DCN, the load balancer in some embodiments changes the destination address (e.g., the destination IP address, destination port, destination MAC address, etc.) in the data message from the address of the identified DCN group to the address (e.g., the destination IP address) of the identified DCN. | 03-31-2016 |
Patent application number | Description | Published |
20120290290 | Sentence Simplification for Spoken Language Understanding - Sentence simplification may be provided. A spoken phrase may be received and converted to a text phrase. An intent associated with the text phrase may be identified. The text phrase may then be reformatted according to the identified intent and a task may be performed according to the reformatted text phrase. | 11-15-2012 |
20130158980 | SUGGESTING INTENT FRAME(S) FOR USER REQUEST(S) - Techniques are described herein that are capable of suggesting intent frame(s) for user request(s). For instance, the intent frame(s) may be suggested to elicit a request from a user. An intent frame is a natural language phrase (e.g., a sentence) that includes at least one carrier phrase and at least one slot. A slot in an intent frame is a placeholder that is identified as being replaceable by one or more words that identify an entity and/or an action to indicate an intent of the user. A carrier phrase in an intent frame includes one or more words that suggest a type of entity and/or action that is to be identified by the one or more words that may replace the corresponding slot. In accordance with these techniques, the intent frame(s) are suggested in response to determining that natural language functionality of a processing system is activated. | 06-20-2013 |
20150088510 | SYSTEM AND METHOD FOR ROBUST ACCESS AND ENTRY TO LARGE STRUCTURED DATA USING VOICE FORM-FILLING - A method, apparatus and machine-readable medium are provided. A phonotactic grammar is utilized to perform speech recognition on received speech and to generate a phoneme lattice. A document shortlist is generated based on using the phoneme lattice to query an index. A grammar is generated from the document shortlist. Data for each of at least one input field is identified based on the received speech and the generated grammar. | 03-26-2015 |
20150243278 | PRONUNCIATION LEARNING THROUGH CORRECTION LOGS - A new pronunciation learning system for dynamically learning new pronunciations assisted by user correction logs. The user correction logs provide a record of speech recognition events and subsequent user behavior that implicitly confirms or rejects the recognition result and/or shows the user's intended words by via subsequent input. The system analyzes the correction logs and distills them down to a set of words which lack acceptable pronunciations. Hypothetical pronunciations, constrained by spelling and other linguistic knowledge, are generated for each of the words. Offline recognition determines the hypothetical pronunciations with a good acoustical match to the audio data likely to contain the words. The matching pronunciations are aggregated and adjudicated to select new pronunciations for the words to improve general or personalized recognition models. | 08-27-2015 |
20150269136 | CONTEXT-AWARE RE-FORMATING OF AN INPUT - Various components provide options to re-format an input based on one or more contexts. The input is received that has been submitted to an application (e.g., messaging application, mobile application, word-processing application, web browser, search tool, etc.), and one or more outputs are identified that are possibilities to be provided as options for re-formatting. A respective score of each output is determined by applying a statistical model to a respective combination of the input and each output, the respective score comprising a plurality of context scores that quantify a plurality of contexts of the respective combination. Exemplary contexts include historical-user contexts, domain contexts, and general contexts. One or more suggested outputs are selected from among the one or more outputs based on the respective scores and are provided as options to re-format the input. | 09-24-2015 |
20150278191 | Flexible Schema for Language Model Customization - The customization of language modeling components for speech recognition is provided. A list of language modeling components may be made available by a computing device. A hint may then be sent to a recognition service provider for combining the multiple language modeling components from the list. The hint may be based on a number of different domains. A customized combination of the language modeling components based on the hint may then be received from the recognition service provider. | 10-01-2015 |
20150325235 | Language Model Optimization For In-Domain Application - Systems and methods are provided for optimizing language models for in-domain applications through an iterative, joint-modeling approach that expresses training material as alternative representations of higher-level tokens, such as named entities and carrier phrases. From a first language model, an in-domain training corpus may be represented as a set of alternative parses of tokens. Statistical information determined from these parsed representations may be used to produce a second (or updated) language model, which is further optimized for the domain. The second language model may be used to determine another alternative parsed representation of the corpus for a next iteration, and the statistical information determined from this representation may be used to produce a third (or further updated) language model. Through each iteration, a language model may be determined that is further optimized for the domain. | 11-12-2015 |
20160042732 | SYSTEM AND METHOD FOR ROBUST ACCESS AND ENTRY TO LARGE STRUCTURED DATA USING VOICE FORM-FILLING - A method, apparatus and machine-readable medium are provided. A phonotactic grammar is utilized to perform speech recognition on received speech and to generate a phoneme lattice. A document shortlist is generated based on using the phoneme lattice to query an index. A grammar is generated from the document shortlist. Data for each of at least one input field is identified based on the received speech and the generated grammar. | 02-11-2016 |
20160078868 | SUGGESTING INTENT FRAME(S) FOR USER REQUEST(S) - Techniques are described herein that are capable of suggesting intent frame(s) for user request(s). For instance, the intent frame(s) may be suggested to elicit a request from a user. An intent frame is a natural language phrase (e.g., a sentence) that includes at least one carrier phrase and at least one slot. A slot in an intent frame is a placeholder that is identified as being replaceable by one or more words that identify an entity and/or an action to indicate an intent of the user. A carrier phrase in an intent frame includes one or more words that suggest a type of entity and/or action that is to be identified by the one or more words that may replace the corresponding slot. In accordance with these techniques, the intent frame(s) are suggested in response to determining that natural language functionality of a processing system is activated. | 03-17-2016 |
Patent application number | Description | Published |
20100313083 | CHANNEL CONSTRAINED CODE AWARE INTERLEAVER - An interleaver is constructed based on the joint constraints imposed in the channel and the code domains. A sequentially optimal algorithm is used for mapping bits in the inter-symbol interference (ISI) domain to the code domain by taking into account the ISI memory depth and the connectivity of the nodes within the parity check matrix. Primary design constraints are considered such as the parallelism factor so that the proposed system is hardware compliant in meeting high throughput requirements. | 12-09-2010 |
20110078540 | INTERLACED ITERATIVE SYSTEM DESIGN FOR 1K-BYTE BLOCK WITH 512-BYTE LDPC CODEWORDS - To allow a single LDPC decoder to operate on both 512 B blocks and 4 KB blocks with comparable error correction performance, 512 KB blocks are interlaced to form a 1 KB data sequence, and four sequential 1 KB data sequences are concatenated to form a 4 KB sector. A de-interlacer between the detector and decoder forms multiple data sequence from a single data sequence output by the detector. The multiple data sequences are separately processed by a de-interleaver between the de-interlacer and the LDPC decoder, by the LDPC decoder, and by an interleaver at the output of the LDPD decoder. An interlacer recombines the multiple data sequences into a single output. Diversity may be improved by feeding interleaver seeds for respective codewords into the de-interleaver and interleaver during processing. | 03-31-2011 |
20110080668 | CLOSELY COUPLED VECTOR SEQUENCERS FOR A READ CHANNEL PIPELINE - A system and method involving a read channel pipeline having a plurality of vector sequencers that may be used to control the processing blocks. In one embodiment, a read channel pipeline may include processing blocks that may be controlled a command word provided by vector sequencers. Incoming data may be delineated by identifying an early period, a steady-state period, and a trailing period. Instead of controlling these blocks with a static state machine controller, a plurality of vector sequencers are coupled to the plurality of processing blocks. Thus, a first vector sequencer may control the processing blocks during the early period and the steady state period, but then hand off control to a second vector sequencer for the trailing period. Using vector sequencers for implementing command words allows for greater programming flexibility once the device has been manufactured and deployed for use. | 04-07-2011 |
20110080669 | CONSTRAINED ON-THE-FLY INTERLEAVER ADDRESS GENERATOR CIRCUITS, SYSTEMS, AND METHODS - An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain. | 04-07-2011 |
20110085628 | ADAPTIVE DATA DEPENDENT NOISE PREDICTION (ADDNP) - A method is provided. The method comprises calibrating noise prediction parameters by adapting one or more biases, adapting one or more filter coefficients using the adapted one or more biases, and adapting one or more prediction error variances using the adapted one or more biases and the adapted one or more filter coefficients. | 04-14-2011 |
20110167322 | Methods to improve ACS performance - In one embodiment, systems and methods of operating a SOVA system is disclosed that comprises determining the start and stop values for a trellis tree and using the start and stop values to determine the initial states of a plurality of branches within the trellis tree. | 07-07-2011 |
20110197112 | Max-log-map equivalence log likelihood ratio generation soft Viterbi architecture system and method - A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector. | 08-11-2011 |
20120047396 | IDENTIFYING A DEFECT IN A DATA-STORAGE MEDIUM - An embodiment of a data-read path includes a defect detector and a data-recovery circuit. The defect detector is operable to identify a defective region of a data-storage medium, and the data-recovery circuit is operable to recover data from the data-storage medium in response to the defect detector. For example, such an embodiment may allow identifying a defective region of a data-storage disk caused, e.g., by a scratch or contamination, and may allow recovering data that was written to the defective region. | 02-23-2012 |
20130275714 | MAPPING BETWEEN PROGRAM STATES AND DATA PATTERNS - The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G memory cells such that a combination of respective program states of the group maps to a constellation point corresponding to a received N unit data pattern, the group used to store N/G units of data per memory cell; wherein the constellation point is one of a number of constellation points of a constellation associated with mapping respective program state combinations of the group of memory cells to N unit data patterns; and wherein the constellation comprises a first mapping shell and a second mapping shell, the constellation points corresponding to the respective first and second mapping shells determined, at least partially, based on a polynomial expression of order equal to G. | 10-17-2013 |
20140036589 | MEMORY CELL STATE IN A VALLEY BETWEEN ADJACENT DATA STATES - The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method can also include transmitting a signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley. | 02-06-2014 |
20140111882 | CONSTRAINED ON-THE-FLY INTERLEAVER ADDRESS GENERATOR CIRCUITS, SYSTEMS, AND METHODS - An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain. | 04-24-2014 |
20140129896 | ERROR CORRECTION METHODS AND APPARATUSES USING FIRST AND SECOND DECODERS - Apparatuses and methods for error correcting data are provided. A first error correction code (ECC) decoder is configured to decode a first codeword to provide a first result and to decode a second codeword to provide a second result. The decoder is configured to run up to a particular number of iterations to provide each of the results. A second ECC decoder is configured to decode a third codeword to provide decoded data, wherein the third codeword comprises the first result and the second result. An evaluation module is configured to initiate a recovery scheme responsive to the decoded data including an error. | 05-08-2014 |
20140153332 | DETERMINING SOFT DATA FROM A HARD READ - Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a state of a memory cell. Soft data is determined based, at least partially, on the determined state. | 06-05-2014 |
20140164867 | STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION - The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer. | 06-12-2014 |
20140208054 | DETERMINING SOFT DATA FOR FRACTIONAL DIGIT MEMORY CELLS - Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping. | 07-24-2014 |
20140208189 | DETERMINING SOFT DATA USING A CLASSIFICATION CODE - Apparatuses and methods for determining soft data using a classification code are provided. One example apparatus can include a classification code (CC) decoder and an outer code decoder coupled to the CC decoder. The CC decoder is configured to receive a CC codeword. The CC codeword includes a piece of an outer code codeword and corresponding CC parity digits. The CC decoder is configured to determine soft data associated with the piece of the outer code codeword, at least partially, using the corresponding CC digits. | 07-24-2014 |
20140240863 | MAX-LOG-MAP EQUIVALENCE LOG LIKELIHOOD RATIO GENERATION SOFT VITERBI ARCHITECTURE SYSTEM AND METHOD - A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector. | 08-28-2014 |
20140244964 | DUAL MAPPING BETWEEN PROGRAM STATES AND DATA PATTERNS - The present disclosure includes methods and apparatuses for dual mapping between program states and data patterns. One apparatus includes a memory and a controller configured to control a dual mapping method comprising: performing a base conversion on a received data pattern and mapping a resulting base converted data pattern to one of a first number of program state combinations corresponding to a first group of memory cells; and determining a number of error data units corresponding to the base converted data pattern and mapping the number of error data units to one of a number of second program state combinations corresponding to a second group of memory cells. The number of error data units are mapped to the one of the second number of program state combinations corresponding to the second group of memory cells without being base converted. | 08-28-2014 |
20140351491 | MAPPING BETWEEN PROGRAM STATES AND DATA PATTERNS - The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G memory cells such that a combination of respective program states of the group maps to a constellation point corresponding to a received N unit data pattern, the group used to store N/G units of data per memory cell; wherein the constellation point is one of a number of constellation points of a constellation associated with mapping respective program state combinations of the group of memory cells to N unit data patterns; and wherein the constellation comprises a first mapping shell and a second mapping shell, the constellation points corresponding to the respective first and second mapping shells determined, at least partially, based on a polynomial expression of order equal to G. | 11-27-2014 |
20150162089 | MAPPING BETWEEN PROGRAM STATES AND DATA PATTERNS - The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G memory cells such that a combination of respective program states of the group maps to a constellation point corresponding to a received N unit data pattern, the group used to store N/G units of data per memory cell; wherein the constellation point is one of a number of constellation points of a constellation associated with mapping respective program state combinations of the group of memory cells to N unit data patterns; and wherein the constellation comprises a first mapping shell and a second mapping shell, the constellation points corresponding to the respective first and second mapping shells determined, at least partially, based on a polynomial expression of order equal to G. | 06-11-2015 |
20150270855 | DETERMINING SOFT DATA USING A CLASSIFICATION CODE - Apparatuses and methods for determining soft data using a classification code are provided. One example apparatus can include a classification code (CC) decoder and an outer code decoder coupled to the CC decoder. The CC decoder is configured to receive a CC codeword. The CC codeword includes a piece of an outer code codeword and corresponding CC parity digits. The CC decoder is configured to determine soft data associated with the piece of the outer code codeword, at least partially, using the corresponding CC digits. | 09-24-2015 |
20150286522 | DUAL MAPPING BETWEEN PROGRAM STATES AND DATA PATTERNS - The present disclosure includes methods and apparatuses for dual mapping between program states and data patterns. One apparatus includes a memory and a controller configured to control a dual mapping method comprising: performing a base conversion on a received data pattern and mapping a resulting base converted data pattern to one of a first number of program state combinations corresponding to a first group of memory cells; and determining a number of error data units corresponding to the base converted data pattern and mapping the number of error data units to one of a number of second program state combinations corresponding to a second group of memory cells. The number of error data units are mapped to the one of the second number of program state combinations corresponding to the second group of memory cells without being base converted. | 10-08-2015 |
20150310911 | DETERMINING WHETHER A MEMORY CELL STATE IS IN A VALLEY BETWEEN ADJACENT DATA STATES - The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method can also include transmitting a signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley. | 10-29-2015 |
20150333774 | STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION - The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer. | 11-19-2015 |
20160071618 | DETERMINING SOFT DATA FROM A HARD READ - Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a state of a memory cell. Soft data is determined based, at least partially, on the determined state. | 03-10-2016 |
20160077941 | IDENTIFYING A DEFECT IN A DATA-STORAGE MEDIUM - An embodiment of a data-read path includes a defect detector and a data-recovery circuit. The defect detector is operable to identify a defective region of a data-storage medium, and the data-recovery circuit is operable to recover data from the data-storage medium in response to the defect detector. For example, such an embodiment may allow identifying a defective region of a data-storage disk caused, e.g., by a scratch or contamination, and may allow recovering data that was written to the defective region. | 03-17-2016 |
20160094247 | PROGRESSIVE EFFORT DECODER ARCHITECTURE - A memory device may include memory components to store data. The memory device may also include a processor that may decode a codeword associated with the data. The processor may receive the codeword and determine whether the codeword is independently decodable using a BCH decoder. The processor may then decode the codeword using the BCH decoder when the codeword is determined to be independently decodable using the BCH decoder. Otherwise, the processor may decode the codeword using a second decoder and the BCH decoder when the codeword is not determined to be independently decodable using the BCH decoder. | 03-31-2016 |
20160104527 | DETERMINING SOFT DATA FOR FRACTIONAL DIGIT MEMORY CELLS - Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping. | 04-14-2016 |
Patent application number | Description | Published |
20080212665 | System for monitoring the quality of a communications channel with mirror receivers - A system is presented that monitors the quality of a communications channel with mirror receivers. A first receiver and a second receiver, coupled in parallel with the first receiver, receive a data signal transmitted over the communications channel. The second receiver generates an output signal. A signal integrity (SI) processor manipulates the output signal in order to determine the quality of the communications channel. The SI processor samples a phase-shifted version of the output signal, which has a phase shifted relative to a zero reference phase, and analyzes the phase-shifted version of the output signal for bit errors. In an embodiment, the SI processor manipulates the output signal to extract an eye diagram indicative of the quality of the communications channel. The SI processor non-intrusively determines the quality of the communications channel using the second receiver. | 09-04-2008 |
20080304579 | Apparatus and method for automatic polarity swap in a communications system - An automatic polarity swap is implemented in a communications system. Two or more transceivers having differential inputs and outputs are coupled together through an interface, such as a backplane to form a communications system. In such a configuration, it is possible to cross-connect the differential data lines or signals at the interface, which will cause invalid data words to received at the second transceiver. Accordingly, the present invention includes an error check and correction module that detects invalid data words after parallel-to-serial conversion. More specifically, an error check determines if the parallel differential signal represents a valid data word. This can be done, for example, by storing and comparing valid data words in a memory such as RAM. If the received data word is valid, then no corrective action is taken. However, if the received data word is invalid, then the parallel differential signal is inverted using a logic circuit, which will correct the error if it is due to cross-connection of the differential lines at the interface or anywhere else. | 12-11-2008 |
20090113258 | Method and system for testing devices using loop-back pseudo random datat - There is provided a method of testing a first device using a tester. The method comprises receiving test data having a pattern by the first device from the tester; detecting the pattern of the test data by the first device; generating first data, by the first device, according to the pattern detected by the detecting; comparing the test data with the pattern detected by the detecting; determining errors in the test data, by the first device, based on the comparing; inserting the errors into the first data to generate error-inserted first data; and transmitting the error-inserted first data by the first device to the tester. The method may further comprise generating a first clock at the first device; wherein the transmitting uses the first clock for transmitting the error-inserted first data. | 04-30-2009 |
20090232192 | Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase - A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed. | 09-17-2009 |
20110007785 | Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase - A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed. | 01-13-2011 |
20110191656 | Systems for High-Speed Backplane Applications Using Pre-Coding - In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems. | 08-04-2011 |
20110191657 | Systems for High-Speed Backplane Applications Using FEC Encoding - In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems. | 08-04-2011 |
20120002713 | MULTI-PROTOCOL COMMUNICATIONS RECEIVER WITH SHARED ANALOG FRONT-END - According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol. | 01-05-2012 |
20120201280 | Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase - A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed. | 08-09-2012 |
20130243072 | MULTI-PROTOCOL COMMUNICATIONS RECEIVER WITH SHARED ANALOG FRONT-END - According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol. | 09-19-2013 |
20130301691 | On-Chip Interferers for Standards Compliant Jitter Tolerance Testing - Systems and methods that facilitate on-chip testing are provided. An integrated circuit can include a transmitter configured to transmit a communications signal via a communications channel. The integrated circuit can also include a receiver configured to receive the communications signal via the communications channel. A jitter creation module also can form part of the integrated circuit and can introduce jitter into the system thereby allowing for on-chip jitter testing. The jitter creation module can form either part of the transmitter or receiver and can introduce the jitter by phase interpolation. | 11-14-2013 |
20140112382 | Systems for High-Speed Backplane Applications Using Pre-Coding - In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems. | 04-24-2014 |
20150063828 | Generalized Transmit Pre-Coding for Optical and Backplane Channels - Systems that allow for DFE functionality to be eliminated from the receiver side of a communication system and for a DFE-like functionality to be implemented instead at the transmitter side of the communication system are provided. By removing the DFE functionality from the receiver side, error propagation can be eliminated at the receiver and receiver complexity can be reduced drastically. At the transmitter side, the DFE-like functionality provides the same DFE benefits, and with the transmitter environment being noise-free, no errors can occur due noise boosting, for example. The DFE-like functionality at the transmitter side can be implemented using non-linear (recursive or feed-forward) pre-coders or a combination of non-linear pre-coders and linear filters, which can be configured to invert a net communication channel between the transmitter and the receiver. Embodiments particularly suitable for fiber optic channels and server backplane channels are also provided. | 03-05-2015 |
20150070198 | Flexible ADC Calibration Technique Using ADC Capture Memory - Systems and methods are provided for calibrating an analog to digital converter (ADC) using one or more feedback mechanisms. In an embodiment, a capture memory module captures a portion of ADC data and post-processes the captured data using a microprocessor to perform calibration. Using the microprocessor, the capture memory module calibrates the ADC until the output of the ADC is within a desired range. In an embodiment, the capture memory module also captures a portion of data output from a digital correction module and post-processes this captured data using the microprocessor. Using the microprocessor, the capture memory module calibrates the digital correction module until the output of the digital correction module is within a desired range | 03-12-2015 |
20150207502 | Method and Apparatus for Reference-Less Repeater with Digital Control - Reference-less repeating circuits provide significant advantages over repeating circuits requiring external frequency references. These repeating circuits eliminate the need for external frequency references provide significant power, layout, and physical isolation advantages. Digitally controlled reference-less repeating circuits have a relatively narrow frequency detection range, but typically consume significantly less power than analog repeating circuits while providing data rate flexibility, particularly at lower data rates. Due to the narrow frequency detection range of digitally controlled reference-less repeating circuits, efficient frequency estimation techniques allow these circuits to quickly lock to an input signal, and provide an accurate repeated output signal. | 07-23-2015 |