Patent application number | Description | Published |
20100171094 | LIGHT-EMITTING SEMICONDUCTOR APPARATUS - A light-emitting semiconductor apparatus includes a light-emitting structure, a reflective structure, and a carrier. The light-emitting structure includes a first type semiconductor layer, a second type semiconductor layer, and a light-emitting layer positioned between the first type semiconductor layer and the second type semiconductor layer. The reflective structure has a first transparent conductive layer, a first patterned reflective layer, a second transparent conductive layer, and a second patterned reflective layer. The first patterned reflective layer is disposed between the first transparent conductive layer and the second transparent conductive layer, and has an opening for physically connecting the first transparent conductive layer and the second transparent conductive layer. The second transparent conductive layer is disposed between the first patterned reflective layer and the second patterned reflective layer. The second patterned reflective layer is positioned on an area corresponding to the opening. The light-emitting structure and the carrier are respectively on two sides of the reflective structure. | 07-08-2010 |
20100308355 | LIGHT-EMITTING DEVICE HAVING A THINNED STRUCTURE AND THE MANUFACTURING METHOD THEREOF - A semiconductor light-emitting device having a thinned structure comprises a thinned structure formed between a semiconductor light-emitting structure and a carrier. The manufacturing method comprises the steps of forming a semiconductor light-emitting structure above a substrate; attaching the semiconductor light-emitting structure to a support; thinning the substrate to form a thinned structure; forming or attaching a carrier to the thinned substrate; and removing the support. | 12-09-2010 |
20110108879 | LIGHT-EMITTING DEVICE - A light-emitting device comprising a semiconductor light-emitting stack, comprising a light emitting area; an electrode formed on the semiconductor light-emitting stack, wherein the electrode comprises a current injected portion and an extension portion; a current blocking structure formed between the current injected portion and the semiconductor light-emitting stack, and formed between a first part of the extension portion and the semiconductor light-emitting stack; and an electrical contact structure formed between a second part of the extension portion and the semiconductor light-emitting stack. | 05-12-2011 |
20120231560 | LIGHT-EMITTING DEVICE HAVING A THINNED STRUCTURE AND THE MANUFACTURING METHOD THEREOF - A semiconductor light-emitting device having a thinned structure comprises a thinned structure formed between a semiconductor light-emitting structure and a carrier. The manufacturing method comprises the steps of forming a semiconductor light-emitting structure above a substrate; attaching the semiconductor light-emitting structure to a support; thinning the substrate to form a thinned structure; forming or attaching a carrier to the thinned substrate; and removing the support. | 09-13-2012 |
20130001624 | LIGHT-EMITTING DEVICE - A light-emitting device includes a semiconductor light-emitting stack; a current injected portion formed on the semiconductor light-emitting stack; an extension portion having a first branch radiating from the current injected portion and having a first width, and a first length greater than the first width, and a second branch extending from the first branch and having a second width larger than the first width, and a second length greater than the second width; and an electrical contact structure between the second branch and the semiconductor light-emitting stack. | 01-03-2013 |
20130341667 | LIGHT-EMITTING DEVICE - A light-emitting device includes a semiconductor light-emitting stack; a current injected portion formed on the semiconductor light-emitting stack; an extension portion having a first branch radiating from the current injected portion and a second branch extending from the first branch; an electrical contact structure between the second branch and the semiconductor light-emitting stack and having a first width; and a current blocking structure located right beneath the electrical contact structure and having a second width larger than the first width. | 12-26-2013 |
Patent application number | Description | Published |
20090314095 | PRESSURE SENSING DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF - A pressure sensing device package including a circuit substrate, a pressure sensing device, a molding compound, and a flexible protection layer is provided. The circuit substrate has an opening. The pressure sensing device is flip chip bonded to the circuit substrate and has a sensing region facing toward the opening. The molding compound encapsulates the pressure sensing device but exposes the sensing region. The flexible protection layer is disposed on the sensing region and exposed by the opening of the circuit substrate. | 12-24-2009 |
20100025794 | IMAGE SENSOR CHIP PACKAGE STRUCTURE AND METHOD THEREOF - An image sensor chip package structure includes a transparent substrate, a chip, a sealing ring, a number of conductive posts, and a number of conductive bumps. The transparent substrate has a number of through holes. The through holes pass through the transparent substrate. The chip has an active surface, an image sensitive area, and a number of die pads. The image sensitive area and the die pads are located on the active surface. The sealing ring is disposed between the chip and the transparent substrate and surrounds the image sensitive area and the die pads. The conductive posts are disposed in the through holes, respectively. Here, the chip is electrically connected with the conductive posts via the die pads. The conductive bumps are disposed on the die pads, respectively. The conductive bumps are connected with the conductive posts, respectively. | 02-04-2010 |
20100164092 | SEMICONDUCTOR PROCESS, AND SILICON SUBSTRATE AND CHIP PACKAGE STRUCTURE APPLYING THE SAME - A semiconductor process is provided. First, a silicon base is provided. Next, a surface of the silicon base is partially exposed and at least a stair structure is formed on the silicon base by etching the surface of the silicon base. The stair structure has a first notch with a first depth and a second notch with a second depth. The first depth is smaller than the second depth, and a diameter of the first notch is larger than a diameter of the second notch. A final insulating layer and a metal seed layer are sequentially formed on the stair structure. A patterned photoresist layer is formed on the metal seed layer. A circuit layer coving exposed portions of the metal seed layer located above the first notch is formed. The patterned photoresist layer and portions of the metal seed layer disposed below the patterned photoresist layer are then removed. | 07-01-2010 |
20100279452 | IMAGE SENSOR CHIP PACKAGE METHOD - In an image sensor chip package method, a transparent substrate having an upper surface, a lower surface, and through holes is provided. The through holes pass through the transparent substrate. Conductive posts are formed in the through holes. A sealing ring is formed on the lower surface of the transparent substrate. A chip having an active surface, an image sensitive area, and die pads is provided. The image sensitive area and the die pads are located on the active surface. Conductive bumps are formed and respectively disposed on the die pads for respectively connecting the conductive posts. At the time the active surface of the chip is turned to face toward the lower surface of the transparent substrate. The chip is assembled to the transparent substrate and electrically connected with the conductive posts via the die pads. The sealing ring surrounds the image sensitive area and the die pads. | 11-04-2010 |
20140065782 | METHOD OF MAKING A FINFET DEVICE - A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate and fin structures on the substrate. A sidewall spacer is formed along sidewall of fin structures in the precursor. A portion of fin structure is recessed to form a recessing trench with the sidewall spacer as its upper portion. A semiconductor is epitaxially grown in the recessing trench and continually grown above the recessing trench to form an epitaxial structure. | 03-06-2014 |
20140065818 | METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A sacrifice layer (SL) is formed and patterned on the substrate. The patterned SL has a plurality of openings. The method also includes forming a metal layer in the openings and then removing the patterned SL to laterally expose at least a portion of the metal layer to form a metal feature, which has a substantial same profile as the opening. A dielectric layer is deposited on sides of the metal feature. | 03-06-2014 |
20140131872 | COPPER ETCHING INTEGRATION SCHEME - The present disclosure is directed to a method of manufacturing an interconnect structure in which a sacrificial layer is formed over a semiconductor substrate followed by etching of the sacrificial layer to form a first feature. The metal layer is patterned and etched to form a second feature, followed by deposition of a low-k dielectric material. The method allows for formation of an interconnect structure without encountering the various problems presented by porous low-k dielectric damage. | 05-15-2014 |
20140197538 | COPPER ETCHING INTEGRATION SCHEME - The present disclosure is directed to an interconnect structure. The metal interconnect structure has a metal body disposed over a semiconductor substrate and a projection extending from the metal body. A barrier layer continuously extends over the projection from a first sidewall of metal body to an opposing second sidewall of the metal body. A layer of dielectric material is disposed over the semiconductor substrate at a position abutting the metal body and the projection. | 07-17-2014 |
20150060119 | CONDUCTIVE STRUCTURE AND MANUFACTURING METHOD THEREOF - A conductive structure comprises a plurality of first nanowires and a plurality of second nanowires. The first nanowires extend along a first direction substantially. The second nanowires extend along a second direction substantially, and at least a part of the second nanowires electrical connect to the first nanowires. The included angle between the first and second directions is nonzero. A manufacturing method of the conductive structure is also disclosed. | 03-05-2015 |
Patent application number | Description | Published |
20090206057 | Method To Improve Mask Critical Dimension Uniformity (CDU) - A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate. | 08-20-2009 |
20130014897 | Apparatus And Method For Controlling Relative Particle Concentrations In A Plasma - An apparatus for controlling a plasma etching process includes plasma control structure that can vary a size of a plasma flow passage, vary a speed of plasma flowing through the plasma flow passage, vary plasma concentration flowing through the plasma flow passage, or a combination thereof. | 01-17-2013 |
20130323931 | DEVICE MANUFACTURING AND CLEANING METHOD - A method of manufacturing is disclosed. An exemplary method includes providing a substrate and forming one or more layers over the substrate. The method further includes forming a surface layer over the one or more layers. The method further includes performing a patterning process on the surface layer thereby forming a pattern on the surface layer. The method further includes performing a cleaning process using a cleaning solution to clean a top surface of the substrate. The cleaning solution includes tetra methyl ammonium hydroxide (TMAH), hydrogen peroxide (H | 12-05-2013 |
20140051252 | DEVICE MANUFACTURING AND CLEANING METHOD - A method of manufacturing is disclosed. An exemplary method includes providing a substrate and forming one or more layers over the substrate. The method further includes forming a surface layer over the one or more layers. The method further includes performing a patterning process on the surface layer thereby forming a pattern on the surface layer. The method further includes performing a cleaning process using a cleaning solution to clean a top surface of the substrate. The cleaning solution includes tetra methyl ammonium hydroxide (TMAH), hydrogen peroxide (H | 02-20-2014 |
20140268074 | Lithography System with an Embedded Cleaning Module - The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism. | 09-18-2014 |
20140272678 | Structure and Method for Reflective-Type Mask - The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer formed on the substrate; a capping layer formed on the reflective multilayer and having a hardness greater than about 8; and an absorber layer formed on the capping layer and patterned according to an integrated circuit layout. | 09-18-2014 |
Patent application number | Description | Published |
20090130854 | PATTERNING STRUCTURE AND METHOD FOR SEMICONDUCTOR DEVICES - Methods for forming a pattern layer over a target layer are disclosed. The methods use a novel low temperature spacer structure which results in a pattern layer having a decreased pattern pitch versus conventional patterning using photolithography. The decreased pattern pitch allows the target layer to be divided into multiple regions separated by a small distance, which in turn allows for greater density and device miniaturization. The structure and methods may be applied to patterning a word line layer in a memory device. | 05-21-2009 |
20110042738 | NITRIDGE READ-ONLY MEMORY CELL AND METHOD OF MANUFACTURING THE SAME - A nitride read-only memory cell and a method of manufacturing the same are provided. First, a substrate is provided, and a first oxide layer is formed on the substrate. Next, a nitride layer is deposited on the first oxide layer via a first gas and a second gas. The flow ratio of the first gas to the second gas is 2:1. After that, a second oxide layer is formed on the nitride layer. Then, a bit-line region is formed at the substrate. Afterward, a gate is formed on the second oxide layer. The first oxide layer, nitride layer, the second oxide layer and the gate compose a stack structure of the cell. Further, a spacer is formed on the side-wall of the stack structure. | 02-24-2011 |
20110073937 | Method for Fabricating a Charge Trapping Memory Device - A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer. | 03-31-2011 |
Patent application number | Description | Published |
20090174097 | SYSTEM FOR MANUFACTURING MICRO-RETARDER AND METHOD FOR MANUFACTURING THE SAME - A system for manufacturing a micro-retarder and a method for manufacturing the same are provided. The system for manufacturing a micro-retarder includes a carrying device, a heating device and a movement control device. The carrying device is used for carrying a polymolecule film. The polymolecule film is selected from a polymolecule film having an arrangement direction. The heating device is used for providing a heating source. The energy formed in the central area of the heating source is smaller than that in the peripheral area of the heating source. The movement control device is used for controlling the heating source and the polymolecule film to relatively move along a first direction, so that the adjusted heating source heats at least one partial area of the polymolecule film along the first direction and resumes the partial area of the polymolecule film to be non-directional. | 07-09-2009 |
20090242661 | NOZZLE PLATE OF A SPRAY APPARATUS AND FABRICATION METHOD THEREOF - A nozzle plate for use with a spray apparatus and a fabrication method thereof are provided. The nozzle plate has a plurality of orifices each including an inlet end and an outlet end. The inlet end and the outlet end have a geometrical structure with mirror symmetry and a centroid with positional deviation from a pattern center. The pattern center is the center of an imaginary circle circumscribed about the geometrical structure. The geometrical structure controls the propagation direction of liquid spray, expands the nebulizing range per unit density of orifices, enables product miniaturization, and saves energy. | 10-01-2009 |
20090242662 | LIQUID NEBULIZATION SYSTEM - Disclosed is a liquid nebulization system comprising a power supply unit, a signal generating unit, a liquid storage unit and a nebulizing unit. The signal generating unit receives power from the power supply unit to generate a main signal and at least an auxiliary signal, wherein the main signal and the auxiliary signal are added together to constructively and destructively interfere with one another to form a driving signal, further causing the nebulizing unit to nebulize the liquid contained in the liquid storage unit using the driving signal. | 10-01-2009 |
20090250827 | SYSTEM FOR MANUFACTURING MICRO-RETARDER AND METHOD FOR MANUFACTURING THE SAME - A system for manufacturing a micro-retarder and a method for manufacturing the same are provided. The system for manufacturing a micro-retarder includes a carrying device, a heating device and a movement control device. The carrying device is used for carrying a polymolecule film. The polymolecule film is selected from a polymolecule film having an arrangement direction. The heating device is used for providing a heating source. The energy formed in the central area of the heating source is smaller than that in the peripheral area of the heating source. The movement control device is used for controlling the heating source and the polymolecule film to relatively move along a first direction, so that the adjusted heating source heats at least one partial area of the polymolecule film along the first direction and resumes the partial area of the polymolecule film to be non-directional. | 10-08-2009 |
20100001096 | MICRO-PUMP AND MICRO-PUMP SYSTEM - A micro-pump for atomizing and including a main-housing, a nozzle plate, at least an actuator, and a liquid transport pipe is provided. The main-housing has a liquid inlet, a liquid outlet, an air inlet, and a micro-droplet outlet. The nozzle plate is assembled to the main-housing and has at least one nozzle. The nozzle plate divides the interior of the main-housing into a first chamber and a second chamber. The nozzle and the liquid inlet are connected with the first chamber. The air inlet, the liquid outlet, and the micro-droplet outlet are connected with the second chamber. The actuator is disposed on at least one of the main-housing or the nozzle plate. The actuator drives the nozzle plate, so that liquid is filled into the first chamber and sprayed out through the nozzle into the second chamber. The liquid transport pipe connects the liquid inlet and the liquid outlet. | 01-07-2010 |
20100224499 | NOZZLE PLATE OF A SPRAY APPARATUS AND FABRICATION METHOD THEREOF - A nozzle plate for use with a spray apparatus and a fabrication method thereof are provided. The nozzle plate has a plurality of orifices each including an inlet end and an outlet end. The inlet end and the outlet end have a geometrical structure with mirror symmetry and a centroid with positional deviation from a pattern center. The pattern center is the center of an imaginary circle circumscribed about the geometrical structure. The geometrical structure controls the propagation direction of liquid spray, expands the nebulizing range per unit density of orifices, enables product miniaturization, and saves energy. | 09-09-2010 |
20110304909 | IMAGE DISPLAY - An image display adapted to provide a 3D image is provided. The image display includes an image displaying module, an image dividing unit, and a plurality of micro-optical structures. The image displaying module is adapted to emit a light beam including a left eye beam and a right eye beam, and the image displaying module has a displaying area. The image dividing unit is disposed on the transmission path of the light beam for dividing the left eye beam and the right eye beam from each other. The micro-optical structures are dispersed and disposed on part of the transmission path of the light beam, wherein a ratio calculated by dividing a projection area of the micro-optical structures orthogonally projected on the displaying area by the displaying area ranges from 5% to 85%. | 12-15-2011 |
20130293793 | DISPLAY APPARATUS AND CONTROL METHOD THEREOF - A display apparatus having a backlight module, a modulatable parallax barrier module, a polarizer film and a display panel is provided. The backlight module provides a linear polarized light having a first polarization direction. The modulatable parallax barrier module has an alignment state and a transparent state, and has a first alignment film with a first alignment direction on the light-emitting side. The linear polarized light passing through the modulatable parallax barrier module in the transparent state is kept in the first polarization direction, and passing through the modulatable parallax barrier module in the alignment state is transformed to a second polarization direction. The polarizer film has a transmission axis inclined toward either the first polarization direction or the second polarization direction. The modulatable parallax barrier module selects one of the alignment state and the transparent state according to an image information provided by the display panel. | 11-07-2013 |
Patent application number | Description | Published |
20110158007 | MULTI-POWER DOMAIN DESIGN - In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA. | 06-30-2011 |
20120195139 | MULTI-POWER DOMAIN DESIGN - In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA. | 08-02-2012 |
Patent application number | Description | Published |
20100059870 | CHIP PACKAGE STRUCTURE - A chip package structure including a substrate, at least one chip, a plurality of leads, a heat dissipation device, a molding compound, and at least one insulating sheet is provided. The chip is disposed on the substrate. The leads are electrically connected to the substrate. The molding compound having a top surface encapsulates the chip, the substrate, and a portion of the leads. The heat dissipation device is disposed on the top surface of the molding compound. The insulating sheet disposed between the heat dissipation device and at least one of the leads has a bending line dividing the insulating sheet into a main body disposed on the molding compound and a bending portion extending from the main body. | 03-11-2010 |
20100117216 | CHIP PACKAGE STRUCTURE - A chip package structure including a substrate, at least one chip, a heat dissipation device, at least one first conductive bar, a molding compound, and at least one second conductive bar is provided. The chip and the heat dissipation device are respectively disposed on a first and a second surface of the substrate. The first conductive bar has two opposite end surfaces, wherein one end surface is disposed on the first surface of the substrate, the other end surface is extended away from the substrate, and a fastening slot is disposed between the two end surfaces and passes through the other end surface. The molding compound encapsulates the substrate, the chip, part of the heat dissipation device, and the first conductive bar. The second conductive bar is disposed on one surface of the molding compound and has a protrusion portion fastened to the fastening slot of the first conductive bar. | 05-13-2010 |
20100125396 | HYDRAULIC CONTROL APPARATUS FOR SPEED RATIO CHANGE - The present invention provides a hydraulic control apparatus for controlling the speed ratio change of a transmission system. The apparatus, disposed on a carrier, comprises a first pulley unit, a second pulley unit, a first hydraulic drive circuit, a second hydraulic drive circuit, and a hydraulic control circuit and a controller. The first pulley unit coupled to the second pulley unit by a transmission belt, and the first pulley unit and the second pulley unit are fluidly connected to the first and the second hydraulic drive circuit respectively. The hydraulic control circuit fluidly connected to the independent first and second hydraulic drive circuit. The controller functions to switch the series or parallel connection status between the first and second hydraulic drive circuit according to the moving status of the carrier through the hydraulic control circuit so that the speed ratio change is capable of being adjusted continuously and synchronously. | 05-20-2010 |
20120262074 | DRIVING CIRCUIT OF LIGHT EMITTING DIODES HAVING AT LEAST ONE BYPASS CIRCUIT, AND DRIVING METHOD THEREOF - A driving circuit of light emitting diodes includes a power supply circuit, at least one bypass circuit, and a temperature control circuit. The power supply circuit is used for providing a driving voltage to at least one series of light emitting diodes. Each bypass circuit of the at least one bypass circuit is used for being turned on when an ambient temperature is lower than a predetermined temperature. The temperature control circuit is coupled to the at least one bypass circuit for detecting the ambient temperature, and sending a control signal to the at least one bypass circuit when the ambient temperature is lower than the predetermined temperature. Therefore, the driving voltage can still drive the at least one series of light emitting diodes when the ambient temperature is lower than the predetermined temperature. | 10-18-2012 |
Patent application number | Description | Published |
20080258309 | Three-dimensional semiconductor device - A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device. | 10-23-2008 |
20100099267 | SYSTEM AND METHOD OF VAPOR DEPOSITION - Provided is a method and system for vapor deposition of a coating material onto a semiconductor substrate. In an embodiment, photoresist is deposited. An in-situ baking process may be performed with the vapor deposition. In an embodiment, a ratio of chemical components of a material to be deposited onto the substrate is changed during the deposition. Therefore, a layer having a gradient chemical component distribution may be provided. In an embodiment, a BARC layer may be provided which includes a gradient chemical component distribution providing an n,k distribution through the layer. Other materials that may be vapor deposited include pattern freezing material. | 04-22-2010 |
20120090547 | SYSTEM AND METHOD OF VAPOR DEPOSITION - Provided is a system for vapor deposition of a coating material onto a semiconductor substrate. The system includes a chemical supply chamber, a supply nozzle operable to dispense vapor, and a heating element operable to provide heat to a substrate in-situ with the dispensing of vapor. The system may further include reaction chamber(s) and/or mixing chamber(s). | 04-19-2012 |
Patent application number | Description | Published |
20120007161 | Semiconductor Non-volatile Memory - A method of forming a charge-storing layer in a non-volatile memory cell in a logic process includes forming a select gate over an active region of a substrate, forming long polysilicon gates partially overlapping the active region of the substrate, and filling the charge-storing layer between the long polysilicon gates. | 01-12-2012 |
20120163072 | NON-VOLATILE SEMICONDUCTOR MEMORY CELL WITH DUAL FUNCTIONS - A non-volatile semiconductor memory cell with dual functions includes a substrate, a first gate, a second gate, a third gate, a charge storage layer, a first diffusion region, a second diffusion region, and a third diffusion region. The second gate and the third gate are used for receiving a first voltage corresponding to a one-time programming function of the dual function and a second voltage corresponding to a multi-time programming function of the dual function. The first diffusion region is used for receiving a third voltage corresponding to the one-time programming function and a fourth voltage corresponding to the multi-time programming function. The second diffusion region is used for receiving a fifth voltage corresponding to the multi-time programming function. | 06-28-2012 |
20120223381 | Non-volatile memory structure and method for manufacturing the same - A non-volatile memory structure is disclosed. LDD regions may be optionally formed through an ion implantation using a mask for protection of a gate channel region of an active area. Two gates are apart from each other and disposed on an isolation structure on two sides of a middle region of the active area, respectively. The two gates may be each entirely disposed on the isolation structure or partially to overlap a side portion of the middle region of the active area. A charge-trapping layer and a dielectric layer are formed between the two gates and on the active area to serve for a storage node function. They may be further formed onto all sidewalls of the two gates to serve as spacers. Source/drain regions are formed through ion implantation using a mask for protection of the gates and the charge-trapping layer. | 09-06-2012 |
20140016399 | MEMORY ARCHITECTURES HAVING DENSE LAYOUTS - One embodiment relates to a memory device including a plurality of memory units tiled together to form a memory array. A memory unit includes a plurality of memory cells, which include respective capacitors and respective transistors, disposed on a semiconductor substrate. The capacitors include respective lower plates disposed in a conductive region in the semiconductor substrate. A wordline extends over the conductive region, and a contact couples the wordline to the conductive region so as to couple the wordline to the lower plates of the respective capacitors. The respective transistors are arranged so successive gates of the transistors are arranged on alternating sides of the wordline. | 01-16-2014 |
20150016180 | MEMORY ARCHITECTURES HAVING DENSE LAYOUTS - Some embodiments relate to a memory cell to store one or more bits of data. The memory cell includes a capacitor including first and second capacitor plates which are separated from one another by a dielectric. The first capacitor plate corresponds to a doped region disposed in a semiconductor substrate, and the second capacitor plate is a polysilicon or metal layer arranged over the doped region. The memory cell also includes a transistor laterally spaced apart from the capacitor and including a gate electrode arranged between first and second source/drain regions. An interconnect structure is disposed over the semiconductor substrate and couples the gate electrode of the transistor to the second capacitor plate. | 01-15-2015 |
Patent application number | Description | Published |
20110307854 | MANIPULATING PARAMETERIZED CELL DEVICES IN A CUSTOM LAYOUT DESIGN - A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit. | 12-15-2011 |
20130091481 | METHOD OF SCHEMATIC DRIVEN LAYOUT CREATION - A computer-implemented method is disclosed for layout pattern or layout constraint reuse by identifying sub-circuits with identical or similar schematic structure based on a topology comparison strategy. The selected sub-circuit is transformed into a topology representing the relative positions among the instances of the selected sub-circuit. Based on the topology, one or more sub-circuits with identical or similar topologies in a predefined scope of a schematic are recognized and identified. Accordingly, the layout or the layout constraint of the selected sub-circuit is copied and associated to each of the identified sub-circuits. Furthermore, once the sub-circuits are identified, they can be listed on a user interface with notations to allow users to confirm each of the identified sub-circuits respectively. | 04-11-2013 |
20140304671 | MANIPULATING PARAMETERIZED CELL DEVICES IN A CUSTOM LAYOUT DESIGN - A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit. | 10-09-2014 |
Patent application number | Description | Published |
20110198721 | METHOD FOR THINNING A WAFER - A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs. | 08-18-2011 |
20120205814 | DIELECTRIC PROTECTION LAYER AS A CHEMICAL-MECHANICAL POLISHING STOP LAYER - The disclosure provides mechanisms of performing metal chemical-mechanical polishing (CMP) without significant loss of copper and a dielectric film of damascene structures. The mechanisms use a metal CMP stop layer made of a low-k dielectric film with a porogen, which significantly reduces the removal rate of the metal CMP stop layer by metal CMP. The metal CMP stop layer is converted into a porous low-k dielectric film after a cure (or curing) to remove or convert the porogen. The low-k value, such as equal to or less than about 2.6, of the metal CMP stop layer makes the impact of using of the metal CMP stop layer on RC delay from minimum to none. Further the CMP stop layer protects the porous low-k dielectric film underneath from exposure to water, organic compounds, and mobile ions in the CMP slurry. | 08-16-2012 |
20140159244 | Process to Achieve Contact Protrusion for Single Damascene Via - The present disclosure relates to a method of forming a back-end-of-the-line metal contact that eliminates RC opens caused by metal dishing during chemical mechanical polishing. The method is performed by depositing a sacrificial UV/thermal decomposition layer (UTDL) above an inter-level dielectric (ILD) layer. A metal contact is formed that extend through the ILD layer and the sacrificial UTDL. A chemical mechanical polishing (CMP) process is performed to generate a planar surface comprising the sacrificial UTDL. The sacrificial UTDL is then removed through an ultraviolet exposure or a thermal anneal, so that the metal contact protrudes from the ILD layer. | 06-12-2014 |
20140213056 | APPARATUS, METHOD, AND COMPOSITION FOR FAR EDGE WAFER CLEANING - A wafer cleaning apparatus includes a polishing unit used in chemical mechanical polishing (CMP) of a wafer and a cleaning dispensing unit arranged to direct cleaning fluids toward a far edge of the wafer after the CMP of the wafer. A wafer cleaning method includes CMP of a wafer by a polishing unit and directing cleaning fluids toward a far edge of the wafer after the CMP of the wafer by a cleaning dispensing unit. Another method can include CMP, applying deionized water, and applying pH adjuster having a pH range from about 2 to about 13. | 07-31-2014 |
20140377954 | METHOD AND APPARATUS FOR IMPROVING CMP PLANARITY - Provided is a method of planarizing a semiconductor device. A dielectric layer is formed over a substrate. A plurality of openings is formed in the dielectric layer. The openings have varying distribution densities. The openings are filled with a metal material. A first chemical-mechanical-polishing (CMP) process is performed to remove portions of the metal material over the dielectric layer. Thereafter, a sacrificial layer is formed over the dielectric layer and the metal material. The sacrificial layer has a planar surface. The sacrificial layer is formed through one of: a spin-on process or a flowable chemical vapor deposition (FCVD) process. A second CMP process is then performed to remove the sacrificial layer and portions of the dielectric layer and the metal material therebelow. The second CMP process uses a slurry configured to have a substantially similar polishing selectivity between the sacrificial layer, the dielectric layer, and the metal material. | 12-25-2014 |
Patent application number | Description | Published |
20120108040 | VAPORIZING POLYMER SPRAY DEPOSITION SYSTEM - A vaporizing spray deposition device for forming a thin film includes a processing chamber, a fluid line, and a spray head coupled to the fluid line proximate the processing chamber. The fluid line is configured to transfer a polymer fluid and solvent mixture to the spray head. The spray head is configured to receive the polymer fluid and solvent mixture and to atomize the polymer fluid and solvent mixture to emit it in a substantially vaporized form to be deposited on a surface and thereby forming a thin film of the polymer on the surface after evaporation of the solvent. In an embodiment, the vaporizing spray deposition device may include a heating device to perform a hard bake process on the polymer. In an embodiment, the vaporizing spray deposition device may be configured to provide a post deposition solvent spray trim process to the thin film polymer. | 05-03-2012 |
20130187237 | STRUCTURE AND METHOD FOR TRANSISTOR WITH LINE END EXTENSION - The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side. | 07-25-2013 |
20130210232 | CUT-MASK PATTERNING PROCESS FOR FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE - A method for patterning a plurality of features in a non-rectangular pattern, such as on an integrated circuit device, includes providing a substrate including a surface with a plurality of elongated protrusions, the elongated protrusions extending in a first direction. A first layer is formed above the surface and above the plurality of elongated protrusions, and patterned with an end cutting mask. The end cutting mask includes two nearly-adjacent patterns with a sub-resolution feature positioned and configured such that when the resulting pattern on the first layer includes the two nearly adjacent patterns and a connection there between. The method further includes cutting ends of the elongated protrusions using the pattern on the first layer. | 08-15-2013 |
20130244434 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of circuit devices over a substrate. The method includes forming an organic layer over the substrate. The organic layer is formed over the plurality of circuit devices. The method includes polishing the organic layer to planarize a surface of the organic layer. The organic layer is free of being thermally treated prior to the polishing. The organic material is un-cross-linked during the polishing. The method includes depositing a LT-film over the planarized surface of the organic layer. The depositing is performed at a temperature less than about 150 degrees Celsius. The depositing is also performed without using a spin coating process. The method includes forming a patterned photoresist layer over the LT-film. | 09-19-2013 |
20140264760 | Layout Optimization of a Main Pattern and a Cut Pattern - A method for feature pattern modification includes extracting both a main pattern and a cut pattern from a design pattern, the main pattern being laid out under a set of process guidelines that improve the process window during formation of the main pattern, and modifying at least one of: the main pattern and the cut pattern if either feature pattern is in violation of a layout rule. | 09-18-2014 |
20150072527 | METHOD FOR PATTERNING A PLURALITY OF FEATURES FOR FIN-LIKE FIELD-EFFECT TRANSISTOR (FINFET) DEVICES - Methods for patterning fins for fin-like field-effect transistor (FinFET) devices are disclosed. An exemplary method includes providing a semiconductor substrate, forming a plurality of elongated protrusions on the semiconductor substrate, the elongated protrusions extending in a first direction, and forming a mask covering a first portion of the elongated protrusions, the mask being formed of a first material having a first etch rate. The method also includes forming a spacer surrounding the mask, the spacer being formed of a second material with an etch rate lower than the etch rate of the first material, the mask and the spacer together covering a second portion of the elongated protrusions larger than the first portion of the elongated protrusions. Further, the method includes removing a remaining portion of the plurality of elongated protrusions not covered by the mask and spacer. | 03-12-2015 |
Patent application number | Description | Published |
20090052456 | Packet-processing apparatus and method - The present invention provides a packet-processing apparatus for receiving and processing N packets in a series, wherein N is a natural number, and each of the packets has a current header. Additionally, the packet-processing apparatus includes an agent, a processing unit, a monitoring unit, a lookup table, and a control unit. Particularly, the packet-processing apparatus according to the invention can process the N packets effectively and flexibly. | 02-26-2009 |
20090210577 | DIRECT MEMORY ACCESS SYSTEM AND METHOD USING THE SAME - The invention discloses a DMA system capable of being adapted to various interfaces. The DMA system includes the following advantages: 1) the software porting effort can be reduced when different interfaces are integrated into a SoC; 2) a flexible DMA that could provide protocol transparency and could be ported into different interfaces easily; 3) a scalable DMA that can support unlimited TX/RX scattering/gathering data segments; 4) a reusable DMA that provides user defined TX information (or RX information) and TX message (or RX message) field; and 5) a high performance DMA that support unaligned segment data pointers and unlimited scattering/gathering data segments, so as to reduce extra memory copies by CPU. | 08-20-2009 |
20090262739 | NETWORK DEVICE OF PROCESSING PACKETS EFFICIENTLY AND METHOD THEREOF - A network device includes a first memory, a second memory, a receiver, a CPU, a transmitter, and a header cache controller (HCC). The HCC is coupled to the first memory and the second memory. The receiver, the CPU, and the transmitter access the first memory and the second memory via the HCC. The HCC can map an address of the first memory storing a header of a packet to an address of the second memory so as to store the header of the packet in the second memory. | 10-22-2009 |
20110103245 | BUFFER SPACE ALLOCATION METHOD AND RELATED PACKET SWITCH - A buffer space allocation method for a packet switch includes periodically performing a measurement process to obtain a plurality of measurement results at different times, each measurement result indicating a total size of accumulated packets in an output queue corresponding to one of a plurality of network ports of the packet switch, and adjusting a dedicated buffer space of the output queue according to the plurality of measurement results and a reserved space value for the dedicated buffer space. | 05-05-2011 |
20120166861 | METHOD FOR ADJUSTING CLOCK FREQUENCY OF A PROCESSING UNIT OF A COMPUTER SYSTEM AND RELATED DEVICE - A method for adjusting clock frequency of a processing unit of a computer system includes calculating a busyness ratio of the processing unit according to a status signal provided by the processing unit, determining whether the busyness ratio is in a busyness ratio range, when the busyness ratio is not in the busyness ratio range, determining whether a calculation result generated according to a clock frequency of the processing unit and a frequency difference is in a frequency range, and when the calculation result is in the frequency range, adjusting the clock frequency of the processing unit according to the calculation result and outputting the adjusted clock frequency to a clock generator, wherein the busyness ratio range, the frequency range and the frequency difference are decided according to an operation state of a peripheral unit of the computer system. | 06-28-2012 |
20130058319 | Network Processor - The present invention discloses a network processor for a broadband gateway. The network processor includes a host processor; a plurality of networking interfaces, corresponding to a plurality of networking technologies, respectively; and a network address translation (NAT) engine, for accelerating packet processing from a first networking interface to a second networking interface. | 03-07-2013 |
20130254433 | DIRECT MEMORY ACCESS SYSTEM AND METHOD USING THE SAME - The invention discloses a DMA system capable of being adapted to various interfaces. The DMA system includes the following advantages: 1) the software porting effort can be reduced when different interfaces are integrated into a SoC; 2) a flexible DMA that could provide protocol transparency and could be ported into different interfaces easily; 3) a scalable DMA that can support unlimited TX/RX scattering/gathering data segments; 4) a reusable DMA that provides user defined TX information (or RX information) and TX message (or RX message) field; and 5) a high performance DMA that support unaligned segment data pointers and unlimited scattering/gathering data segments, so as to reduce extra memory copies by CPU. | 09-26-2013 |
20130272311 | Communication Device and Related Packet Processing Method - The present invention discloses a communication device, including a first network interface, for receiving a plurality of packets composed of a plurality of first packets destined to a first communication device and a plurality of second packets, a first reordering engine, for reordering the plurality of first packets, outputting the plurality of reordered first packets, and outputting the plurality of second packets, a second reordering engine, for receiving the plurality of second packets from the first reordering engine, and reordering the plurality of second packets, a second network interface, for receiving the plurality of reordered first packets from the first reordering engine, and transmitting the plurality of reordered first packets to the first communication device, and a processing module, for processing the plurality of reordered second packets. | 10-17-2013 |
20140269298 | Network Processor and Method for Processing Packet Switching in Network Switching System - A network processor for processing packet switching in a network switching system is disclosed. The network processor includes a first memory for storing a first packet among a plurality of packets; a second memory for storing a second packet among the plurality of packets; and a memory selecting unit for selecting the first memory or the second memory for storing each of the plurality of packets according to whether a traffic of the network switching system is congested; wherein attributes of the first memory and the second memory are different. | 09-18-2014 |
20140376549 | PACKET PROCESSING APPARATUS AND METHOD FOR PROCESSING INPUT PACKET ACCORDING TO PACKET PROCESSING LIST CREATED BASED ON FORWARDING DECISION MADE FOR INPUT PACKET - A packet processing method includes receiving a forwarding decision made for an input packet; and creating a packet processing list of the input packet according to the forwarding decision. When the forwarding decision indicates that the input packet is required to undergo first packet processing operations, each including a common processing operation and an individual processing operation, to generate first output packets forwarded via first egress ports, respectively, first information indicative of the first egress ports is recorded in an egress port field of a first session of the packet processing list; second information indicative of the common processing operation shared by all of the first packet processing operations is recorded in a common processing field of the first session; and third information indicative of individual processing operations of the first packet processing operations is recorded in an individual processing field of the first session. | 12-25-2014 |
Patent application number | Description | Published |
20090171148 | Capsule endoscope system having a sensing and data discriminating device and discrimination method thereof - A capsule endoscope system having a sensing and data discriminating device and the discrimination method thereof are proposed. After a sensor captures data, a data processor performs the extraction of a characteristic value from the data and then comparison and discrimination. Data are then divided into two types: one to be transmitted and the other not to be transmitted. The redundancy of data transmission can be reduced, the amount of data transmission can be lowered, and the effect of power saving can also be accomplished. | 07-02-2009 |
20090185742 | METHOD FOR IMAGE COMPENSATION - In an image compensation method, formats of images are identified based on ambient color quantity information. If the image is in text format or of high contrast, over compensation is barred to avoid edge effect. A compensation coefficient is set basing on edge eigenvalue of images. The compensation value is fine tuned based on a threshold value to obtain finer compensation result. | 07-23-2009 |
20140055354 | MULTI-MODE INTERACTIVE PROJECTION SYSTEM, POINTING DEVICE THEREOF, AND CONTROL METHOD THEREOF - A multi-mode interactive projection system includes a pointing device, an infrared capturing device, and a projection device. A timing generation module of the pointing device generates several timing signals, and controls the pointing device to execute one light emitting mode according to one timing signal. A light emitting module of the pointing device is controlled by the timing generation module, and generates infrared in a light emitting time according to the executed light emitting mode. In a detection time, the light emitting time corresponds to one light emitting mode. The infrared capturing device periodically captures the infrared. A projection module is controlled by a background image and a writing image outputted by a host device, and projects the image to screen. The host device determines the light emitting mode and continuously captures coordinate points of infrared by the infrared capturing device in the detection time. | 02-27-2014 |
Patent application number | Description | Published |
20100207266 | CHIP PACKAGE STRUCTURE - A chip package structure including a substrate, a plurality of electrodes, a chip, and a plurality of bumps is provided. Each of the electrodes has a bottom portion and an annular element, wherein the bottom portion is disposed on the substrate, the annular element is disposed on the bottom portion, and the bottom portion and the annular element define a containing recess. The chip is disposed above the substrate and has an active surface facing the substrate and a plurality of pads disposed on the active surface. The bumps are respectively disposed on the pads and respectively inserted into the containing recesses. The melting point of the electrodes is higher than that of the bumps. A chip package method is also provided. | 08-19-2010 |
20110018117 | SEALED JOINT STRUCTURE OF DEVICE AND PROCESS USING THE SAME - A sealed joint structure of device includes a buffer bump layer, conductive joint portions and a sealed joint portion. The buffer bump layer disposed between a device and a substrate includes first parts and a second part surrounding the first parts. Each of the conductive joint portions includes a first electrode covering each of the first parts and a second electrode on the substrate, and each of the first electrodes is electrically connected to the second electrode. The sealed joint portion includes a joint ring located on the substrate and is jointed with the second part to form a hermetic space between the device and the substrate. | 01-27-2011 |
20110079895 | BUMP STRUCTURE, CHIP PACKAGE STRUCTURE INCLUDING THE SAME AND METHOD OF MANUFACTURING THE SAME - A bump structure includes a first substrate, a plurality of first bond pads, a plurality of dielectric bumps, a plurality of under bump metal layers, and a plurality of metal layers. The plurality of first bond pads are spaced apart on the first substrate. The plurality of dielectric bumps disposed corresponding to the first bond pads electrically isolate the first bond pads from each other. Each under bump metal layer is formed between the respective first bond pad and the dielectric bump, extending through a side surface of the respective dielectric bump, and correspondingly forming an extension portion between two adjacent dielectric bumps, wherein each extension portion has a length along the extending direction thereof shorter than the pitch between two adjacent dielectric bumps. Each metal layer is formed on the side surface of the respective dielectric bump and the respective extension portion. | 04-07-2011 |
20110227190 | ELECTRONIC DEVICE PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - The invention provides an electronic device package structure and method of fabrication thereof. The electronic device package structure includes a chip having an active surface and a bottom surface. A dielectric layer is disposed on the active surface of the chip. At least one trench is formed through the dielectric layer. A first protection layer covers the dielectric layer and sidewalls of the trench. A second protection layer covers the first protection layer, filling the trench. | 09-22-2011 |
20120161336 | SEMICONDUCTOR DEVICE AND ASSEMBLING METHOD THEREOF - A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements. | 06-28-2012 |
20120168933 | WAFER LEVEL MOLDING STRUCTURE - A wafer level molding structure and a manufacturing method thereof are provided. A molding structure includes a first chip and a second chip and an adhesive layer there between. The first chip includes a first back side, a first front side and a plurality of lateral sides, in which a plurality of first front side bumps are disposed on the first front side. The second chip includes a second back side and a second front side, and a plurality of second back side bumps and second front side bumps are respectively disposed on the second back side and the second front side. A plurality of through-hole vias is disposed in the second chip, and electrically connected the second back side bumps to the second front side bumps. Adhesive materials covering the lateral sides of the first chip, and electrically connect the second back side bumps with the first front side bumps. The adhesive materials include a plurality of conductive particles and/or a plurality of non-conductive particles. | 07-05-2012 |
20130234320 | CHIP STACK STRUCTURE AND METHOD FOR FABRICATING THE SAME - A chip stack structure taking a wafer as a stacking base and stacking chips thereon is provided. The chip stack structure is capable of achieving high density electrode bonding and breaking the bottleneck of requiring interposer to serve as a transferring interface in three dimensional chip package. The chip stack structure is easily fabricated and compatible with wafer level process, so as to reduce processing time and manufacturing cost. A method for fabricating the chip stack structure is also provided. | 09-12-2013 |
20140124241 | TOUCH STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - A touch structure and a manufacturing method for the same are provided. The touch structure comprises first patterned electrodes, a second patterned electrode, a dielectric structure and a conductive bridge. The second patterned electrode is disposed between the first patterned electrodes, and separated from the first patterned electrodes. The dielectric structure is disposed on the first patterned electrodes and the second patterned electrode. The dielectric structure has a dielectric opening. The conductive bridge is disposed across the dielectric structure and extended in the dielectric opening. The first patterned electrodes are electrically connected to each other through the conductive bridge. | 05-08-2014 |
20140313160 | TOUCH PANEL AND MANUFACTURING METHOD THEREOF AND TOUCH DISPLAY PANEL - A touch panel and a manufacturing method thereof and a touch display panel are provided. The touch panel includes a substrate, at least one first conductive line, an insulating layer, and at least one second conductive line. The substrate has a sensing region and a periphery region. The first conductive line is disposed on the periphery region. The insulating layer is disposed on the periphery region and covers the first conductive line. The second conductive line is disposed on the periphery region. The first conductive line and the second conductive line are electrically insulated to each other. A portion of at least one second conductive line is disposed on the insulating layer located above the first conductive line. | 10-23-2014 |
Patent application number | Description | Published |
20090174071 | Semiconductor device including electrically conductive bump and method of manufacturing the same - A semiconductor device and method of manufacturing are provided that include forming an electrically conductive bump on a substrate and forming at least one passivation layer on the bump to reduce solder joint failures. | 07-09-2009 |
20100093135 | STRATIFIED UNDERFILL METHOD FOR AN IC PACKAGE - A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board. | 04-15-2010 |
20130026620 | SELF-ALIGNING CONDUCTIVE BUMP STRUCTURE AND METHOD OF MAKING THE SAME - The disclosure relates to a conductive bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface and conductive bumps distributed over the major surface of the substrate. Each of a first subset of the conductive bumps comprise a regular body, and each of a second subset of the conductive bumps comprise a ring-shaped body. | 01-31-2013 |
20130244378 | UNDERFILL CURING METHOD USING CARRIER - A method includes bonding a carrier over a top die. The method further includes curing an underfill disposed between a substrate and the top die. The method further includes applying a force over the carrier during the curing. The method further includes removing the carrier from the top die. | 09-19-2013 |
20150014844 | Die-on-Interposer Assembly with Dam Structure and Method of Manufacturing the Same - A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip. | 01-15-2015 |
Patent application number | Description | Published |
20110111490 | LIGHT TRANSFORMATION PARTICLE AND PHOTOBIOREACTOR - A light transformation particle is provided. The light transformation particle of the invention includes a light-shifting layer containing at least one light-emitting material, wherein the light-emitting layer transforms ultraviolet light, yellow-green light, or infrared light to red-orange light or blue-violet light. The light transformation particle further includes a core layer and/or a shell layer. The present invention further provides a photobioreactor containing the light transformation particle of the invention. | 05-12-2011 |
20120212797 | FLEXIBLE DISPLAY DEVICE - A flexible display device includes a flexible substrate, a display layer, a first protecting layer, and at least one light-pervious polymer film. The display layer is arranged on the flexible substrate. The first protecting layer is arranged on the display layer. The at least one light-pervious polymer film is arranged on the first protecting layer. The light-pervious polymer film is used to protect the flexible display device from being damaged by external force. | 08-23-2012 |
20130027853 | ELECTRONIC DEVICE WITH IMPACT-RESISTANT DISPLAY MODULE - An electronic device includes a shell, a display module and a cushion. The shell includes a bottom plate and a top plate. The top plate defines an opening The display module is disposed in the shell and faces the opening The display module is spaced from the bottom plate of the shell. The cushion is disposed between the display module and the bottom plate of the shell, and brought into contact with the display module for cushioning the display module when an external force is applied to the display module. | 01-31-2013 |
20130146515 | FILTRATION DEHYDRATION APPARATUS - A filtration dehydration apparatus, comprises: a filter, having a filtration layer and an absorption layer while allowing a surface of the filtration layer opposite to the absorption layer to be a first side of the filter, and allowing a surface of the absorption layer opposite to the filtration layer to be a second side of the filter; a supporting structure, for supporting and fixedly secured the filter; a solid collector, for collecting any solid object left on the first side; and an extrusion unit, for pressing the absorption layer so as to squeeze liquid containing in the absorption layer out of the same; wherein the first side is provided for a solid-liquid mixture to be placed thereon for allowing the liquid containing therein to flow into the absorption layer through the filtration layer while enabling any solid object filtered out and thus left on the first side. | 06-13-2013 |
20130146520 | FILTRATION DEHYDRATION APPARATUS - A filtration dehydration apparatus, which comprises: a filter, composed of a filtration layer and an absorption layer while allowing the filtration layer that is orientated facing toward the absorption layer to be a first side, and allowing a surface of the absorption layer that is orientated facing toward the filtration layer to be a second side; a supporting structure, for supporting and fixedly securing the filter; a solid waste collector, for collecting solid object left on the first side; and an extrusion unit, for pressing the absorption layer to squeeze out water in the absorption layer; wherein the first side is provided for a solid-liquid mixture to be placed thereon so as to allow the liquid containing in the solid-liquid mixture to flow into the absorption layer through the filtration layer while enabling solid object in the solid-liquid mixture to be filtered out and thus left on the first side. | 06-13-2013 |
20130174985 | PEELING PROCESS OF SUBSTRATE - A peeling process of substrate used for peeling a first substrate and a second substrate bonded to each other is provided. The first substrate has a first bonding surface, and the second substrate has a second bonding surface and a back surface, wherein the first bonding surface and the second bonding surface are bonded to each other. In the peeling process of substrate, a light beam is incident through the back surface of the second substrate at a first incident angle and then illuminates the first bonding surface and the second bonding surface, wherein the first incident angle is smaller than 90 degree and larger than 0 degree. After that, the second substrate is peeled off from the first substrate. | 07-11-2013 |
Patent application number | Description | Published |
20100157595 | LED MODULE AND PACKAGING METHOD THEREOF - A light-emitting diode (LED) module and an LED packaging method. As the LED module is packaged under the consideration of candela distribution, each of the lead frames of the LED chips packaged in the LED module is bended for tilting the LED chips by different angles to exhibit various lighting effects. Meanwhile, in the LED packaging method, a plurality of LED chips can be loaded on board rapidly and aligned by one operation to result in less deviation in the candela distribution curve. | 06-24-2010 |
20130005055 | LED MODULE AND PACKAGING METHOD THEREOF - A light-emitting diode (LED) module and an LED packaging method. As the LED module is packaged under the consideration of candela distribution, each of the lead frames of the LED chips packaged in the LED module is bended for tilting the LED chips by different angles to exhibit various lighting effects. Meanwhile, in the LED packaging method, a plurality of LED chips can be loaded on board rapidly and aligned by one operation to result in less deviation in the candela distribution curve. | 01-03-2013 |
20140102616 | METHOD OF DIE BONDING AND APPARATUS THEREOF - A method of die bonding, the method has steps of: heating a substrate to a predetermined temperature; sucking at least one die, the at least one die with a base temperature, the base temperature being less than the predetermined temperature; the at least one die bonding on the substrate; cooling the substrate with the bonded die; and moving the substrate with the bonded die to a loading and unloading position, heating another substrate to a predetermined temperature, and repeating the said steps. | 04-17-2014 |
Patent application number | Description | Published |
20090108921 | Timing Control circuit with power-saving function and method thereof - A timing control circuit with a power-saving function includes a receiving circuit, a processor, and a first switch. The receiving circuit receives a first set of differential signals for generating a set of command signals. The processor is coupled to the receiving circuit and generates a first control signal according to the set of command signals. The switch is coupled between the receiving circuit and the processor for selectively decoupling the receiving circuit from a first power supply according to the first control signal. | 04-30-2009 |
20090125761 | Method for controlling a DRAM - A method for controlling a DRAM includes detecting failed memory cells of the DRAM, recording the rows corresponding to the failed memory cells, receiving a control signal for accessing the memory cell with column address X and row address Y, determining if the row address Y is in the recorded failed rows list, and if yes, replacing the memory cell to be accessed with the memory cell with the column address X and row address Z which is not same as Y. | 05-14-2009 |
20090153456 | Method for generating over-drive data - A method for generating over-drive data includes storing a reduced over-drive table and a predetermined weighting table, finding first and second reference values from the reduced over-drive table according to received previous current pixel values, finding first and second weighting values from the predetermined weighting table according to the received current pixel value, and generating a corresponding over-drive data according to the first and the second reference values, and the first and the second weighting values. | 06-18-2009 |
20090244103 | Method for driving a pixel by generating an over-drive grey level and driver thereof - A method for generating an over-drive grey level for driving a pixel includes providing a corresponding over-drive function according to an original grey level for the pixel in the previous frame, and generating the over-drive grey level according to the corresponding over-drive function and the original grey level for the pixel in the current frame. | 10-01-2009 |
20090245394 | Over-drive device and method thereof - A method for data compressing includes compressing an original data with DPCM, compressing again the compressed data with Huffman's encoding for generating a bit-stream, and storing the bit-stream. | 10-01-2009 |
20100073345 | IMAGE-PROCESSING CIRCUIT, RELATED SYSTEM AND RELATED METHOD CAPABLE OF REDUCING POWER CONSUMPTION - An image processing circuit turns off the writing unit of the controller of the DRAM when the previous frame is identical to the current frame. In this way, the writing unit of the controller of the DRAM does not write the current frame into the DRAM, thereby reducing power consumption. | 03-25-2010 |
20130346679 | SYSTEM OF GENERATING SCRAMBLE DATA AND METHOD OF GENERATING SCRAMBLE DATA - A system of generating scramble data includes a linear feedback shift register and a scramble engine. The linear feedback shift register is used for generating a plurality of first scramble values according to an initial value. The scramble engine is coupled to the linear feedback shift register for utilizing at least one bit of a first scramble value of the plurality of first scramble values to execute a first logic operation on other bits of the first scramble value to generate a second scramble value corresponding to the first scramble value. A bit number of the second scramble value is the same as a bit number of the first scramble value. | 12-26-2013 |
Patent application number | Description | Published |
20120023299 | CONTROLLING APPARATUS AND DATA TRANSMITTING SYSTEM APPLYING THE CONTROLLING APPARATUS AND METHOD THEREOF - A controlling apparatus includes: a storage device arranged for storing at least one Byte Enable property compatible to a processing device; and a controlling circuit coupled to the storage device for generating at least one Byte Enable signal to the processing device according to the Byte Enable property compatible with the processing device. | 01-26-2012 |
20120117326 | APPARATUS AND METHOD FOR ACCESSING CACHE MEMORY - The present invention relates to an apparatus and a method for accessing a cache memory. The cache memory comprises a level-one memory and a level-two memory. The apparatus for accessing the cache memory according to the present invention comprises a register unit and a control unit. The control unit receives a first read command and a reject datum of the level-one memory and stores the reject datum of the level-one memory to the register unit. Then the control unit reads and stores a stored datum of the level-two memory to the level-one memory according to the first read command. | 05-10-2012 |
20120191910 | PROCESSING CIRCUIT AND METHOD FOR READING DATA - A processing circuit includes a processing unit and a data buffer. When the processing unit receives a load instruction and determines that the load instruction has a load-use condition, the processing unit stores specific data into the data buffer, where the specific data is loaded by executing the load instruction. | 07-26-2012 |
20130042076 | CACHE MEMORY ACCESS METHOD AND CACHE MEMORY APPARATUS - A cache memory access method is to be implemented by a cache memory apparatus that includes a data storage unit which includes a plurality of storage sets each including a plurality of storage elements corresponding respectively to a plurality of access ways. The method includes: receiving from a processer a target address; determining whether the data storage unit stores target data corresponding to the target address; receiving the target data from a main memory if negative; selecting a chosen way from the plurality of access ways according to whether the storage elements of the storage set which corresponds to the target address store valid data and whether the target address corresponds to a predefined lock range in the main memory; and writing the target data in the data storage unit based on the chosen way. | 02-14-2013 |
20130173862 | METHOD FOR CLEANING CACHE OF PROCESSOR AND ASSOCIATED PROCESSOR - A method for cleaning a cache of a processor includes: generating a specific command according to a request, wherein the specific command includes an operation command, a first field and a second field; obtaining an offset and a starting address according to the first field and the second field; selecting a specific segment from the cache according to the starting address and the offset; and cleaning data stored in the specific segment. | 07-04-2013 |
Patent application number | Description | Published |
20110197961 | CONDUCTIVE ALUMINUM PASTE AND THE FABRICATION METHOD THEREOF, THE SOLAR CELL AND THE MODULE THEREOF - This present disclosure relates to conductive aluminum paste for fabricating a silicon solar cell. Herein, the conductive aluminum paste is composed of organic carrier, aluminum powder, nano-scale metal particle, and glass frit, wherein the nano-scale metal particle has a particle size distribution D50 in the range from 10 nanometers to 1000 nanometers and the weight percentage of the nano-scale metal particle associated with the conductive aluminum paste is around 0.1 through 10 wt %. Furthermore, the characteristics of the conductive aluminum paste are for reducing the sheet resistance value of the electrode, increasing the adhesion in the silicon solar cell package module, and enhancing the electro-optical conversion efficiency of the silicon solar cell. | 08-18-2011 |
20140174529 | CONDUCTIVE ALUMINUM PASTE AND THE FABRICATION METHOD THEREOF, THE SOLAR CELL AND THE MODULE THEREOF - This present disclosure relates to conductive aluminum paste for fabricating a silicon solar cell. Herein, the conductive aluminum paste is composed of organic carrier, aluminum powder, nano-scale metal particle, and glass frit, wherein the nano-scale metal particle has a particle size distribution D50 in the range from 10 nanometers to 1000 nanometers and the weight percentage of the nano-scale metal particle associated with the conductive aluminum paste is around 0.1 through 10 wt %. Furthermore, the characteristics of the conductive aluminum paste are for reducing the sheet resistance value of the electrode, increasing the adhesion in the silicon solar cell package module, and enhancing the electro-optical conversion efficiency of the silicon solar cell. | 06-26-2014 |
Patent application number | Description | Published |
20120188175 | Single Finger Gesture Determination Method, Touch Control Chip, Touch Control System and Computer System - A single finger gesture determination method is disclosed. The single touch gesture determination method includes steps of detecting one or more trigger signals, determining respective categories under a plurality of gesture groups to which the one or more trigger signals belong according to the one or more trigger signals, and deciding a finger gesture represented by the one or more trigger signals according to the determined respective categories under the plurality of gesture groups. | 07-26-2012 |
20120223895 | Single-Finger and Multi-Touch Gesture Determination Method, Touch Control Chip, Touch Control System and Computer System - A single-finger and multi-touch gesture determination method is disclosed. The single touch and multi-touch gesture determination method includes steps of: for each of one or more touch points, judging a respective category under a first group to which the touch point belongs, according to an initial position of the touch point; for each of the one or more touch points, judging a respective category under a second group to which the touch point belongs, according to a moving pattern of the touch point, wherein the moving pattern is respectively defined in the judged category under the first group to which the touch point belongs; and determining a gesture represented by the one or more touch points according to the judged categories under the second group respectively to which the one or more touch points belong. | 09-06-2012 |
20120313871 | TOUCH PANEL AND DISPLAY APPARATUS - A touch panel and a display apparatus are provided. The touch panel includes a substrate, first sensing lines, second sensing lines, first extending portions, second extending portions, and insulation pads. The first sensing lines are disposed on the substrate in parallel with a first direction. The second sensing lines are disposed on the substrate in parallel with a second direction. The first sensing lines intersect the second sensing lines to define meshes. The first extending portions are connected to the first sensing lines and extended toward the meshes. The second extending portions are connected to the second sensing lines and extended toward the meshes. The first extending portions and the second extending portions are distributed next to each other in the meshes. The insulation pads are disposed at where the first sensing lines intersect the second sensing lines to insulate the first sensing lines from the second sensing lines. | 12-13-2012 |
20120314392 | CAPACITOR ARRAY SUBSTRATE - A capacitor array substrate includes a substrate, first traces, second traces, capacitors, connecting lines, and signal lines. The substrate has a first, a second, and a third side. The first side is connected with the second and the third side. The first traces are disposed on the substrate in parallel and are not vertical or parallel to the first side. The second traces are disposed on the substrate in parallel. The capacitors are disposed on the substrate at intersections of the first and the second traces and are connected to the first and the second traces. The connecting lines are disposed on the second and the third side of the substrate. Each connecting line is connected to a first and a second trace. The signal lines are disposed on the substrate. Each signal line is connected to a first or a second trace and transmits signals from the first side. | 12-13-2012 |
20120319967 | SINGLE FPC BOARD FOR CONNECTING MULTIPLE MODULES AND TOUCH SENSITIVE DISPLAY MODULE USING THE SAME - A single flexible printed circuit (FPC) board for connecting multiple modules including a thin film is provided. The thin film has a first module connecting portion, a second module connecting portion and a third module connecting portion. The first module connecting portion is located on a first side of the thin film. The second module connecting portion and the third module connecting portion are located on a second side of the thin film. The first side is opposite to the second side. At least one first line is disposed between the first module connecting portion and the second module connecting portion. At least one second line is disposed between the first module connecting portion and the third module connecting portion. | 12-20-2012 |
20150022744 | SINGLE FPC BOARD FOR CONNECTING MULTIPLE MODULES AND TOUCH SENSITIVE DISPLAY MODULE USING THE SAME - A single flexible printed circuit (FPC) board for connecting multiple modules including a thin film is provided. The thin film has a first module connecting portion, a second module connecting portion and a third module connecting portion. The first module connecting portion is located on a first side of the thin film. The second module connecting portion and the third module connecting portion are located on a second side of the thin film. The first side is opposite to the second side. At least one first line is disposed between the first module connecting portion and the second module connecting portion. At least one second line is disposed between the first module connecting portion and the third module connecting portion. | 01-22-2015 |