Patent application number | Description | Published |
20110260953 | LIGHT EMITTING DEVICE AND DISPLAY PANEL - A light emitting device includes a substrate, a patterned light-scattering layer, and an electroluminescent device. The patterned light-scattering layer is disposed on a portion of the substrate. The patterned light-scattering layer has a bottom surface in contact with the substrate, a top surface opposite to the bottom surface, and a plurality of sidewalls connecting the bottom surface and the top surface. The electroluminescent device is at least disposed on the sidewalls. | 10-27-2011 |
20120038847 | ORGANIC LIGHT EMITTING DEVICE, ILLUMINATION DEVICE AND LIQUID CRYSTAL DISPLAY DEVICE - An organic light emitting device having light emitting units on a substrate is provided. Each light emitting unit includes a first electrode layer, an organic light emitting layer, a second electrode layer, a power line, a resistor line, an insulating layer. The first electrode layer is disposed on the substrate. The organic light emitting layer is disposed on the first electrode layer. The second electrode layer is disposed on the organic light emitting layer. The power line is disposed on the substrate. The resistor line is electrically connected to the first electrode layer, wherein the resistor line partially overlaps with the power line, and an overlapping area occupies 60˜100% of a total area of the resistor line. The insulating layer is disposed between the power line and the resistor line, and a contact hole is disposed in the insulating layer to electrically connect the power line and the resistor line. | 02-16-2012 |
20120104363 | ORGANIC LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - An organic light emitting device having a light emitting unit that includes an anode layer, a second wire, an insulating layer, first and second organic light emitting layers and a cathode layer is provided. The anode layer includes first and second sub-electrodes and a first wire connecting the first and second sub-electrodes that are arranged in a first direction. The second wire is disposed between the first and second sub-electrodes. The insulating layer is disposed on the first and second sub-electrodes and the second wire, and has a plurality of openings to expose the first sub-electrode, the second sub-electrode and the second wire. The first and second organic light emitting layers are disposed in two openings. The cathode layer is disposed on the first and second organic light emitting layers, and the cathode layer fills another opening to electrically connect to the second wire through the another opening. | 05-03-2012 |
20130146908 | ILLUMINATION DEVICE - An illumination device including a substrate, a first conductive layer, a second conductive layer, a self-illuminating layer, and a first auxiliary conductive pattern layer is provided. The first conductive layer and the second conductive layer are disposed on the substrate. The self-illuminating layer is located between the first conductive layer and the second conductive layer to define an illumination region on the substrate. The first auxiliary conductive pattern layer is in contact with the first conductive layer and has an impedance smaller than that of the first conductive layer. A ratio of a perimeter (um) of the first auxiliary conductive pattern layer occupied in the illumination region to an area (um | 06-13-2013 |
20130154472 | ORGANIC ELECTROLUMINESCENT DEVICE - An organic electroluminescent device including an electrode line, a transparent impedance line, an insulating layer, a transparent electrode, an organic illumination layer and an electrode is provided. The electrode line is disposed on a substrate and next to a luminescent zone. The transparent impedance line is disposed in the luminescent zone on the substrate and electrically connected to the electrode line. The insulating layer completely covers the substrate and has a contact hole. The transparent electrode completely covers the luminescent zone and is disposed on the insulating layer. The transparent impedance line and the transparent electrode are electrically connected to each other through the contact hole. The organic illumination layer is disposed on the transparent electrode. The electrode is disposed on the organic illumination layer. Thus, the illumination of the organic electroluminescent device can be more uniform and the aperture ratio is increased. | 06-20-2013 |
Patent application number | Description | Published |
20090091241 | FULL-COLOR ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL AND FABRICATING METHOD THEREOF - A full-color OLED display panel comprises a full-color organic light-emitting device and a colored filter device stacked on the light-exit surface of the full-color organic light-emitting device. The full-color organic light-emitting device comprises a first electrode, a plurality of second electrodes, a first light-emitting layer sandwiched between the first electrode and a portion of the second electrodes, and a second light-emitting layer sandwiched between the first electrode and portions of the second electrodes and the first light-emitting layer. The colored filter device comprises a substrate, and a plurality of first color filter portions, a plurality of second color filter portions and a plurality of third color filter portions disposed on the surface of the substrate. The first color filter portions allow a first color light emitted from the first light-emitting layer to pass through, and the second color filter portions and the third color filter portions each allow rays with different wavelengths in a second color light emitted from the second light-emitting layer to pass through. | 04-09-2009 |
20130183823 | BUMPING PROCESS - A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots corresponded to the first areas of the titanium-containing metal layer, forming a plurality of copper bumps at the opening slots, proceeding a heat procedure, forming a plurality of bump isolation layers on the copper bumps, forming a plurality of connective layers on the bump isolation layers, removing the photoresist layer, removing the second areas and enabling each the first areas to form an under bump metallurgy layer. | 07-18-2013 |
20130214407 | SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF - A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances. | 08-22-2013 |
20130214419 | SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF - A semiconductor packaging method includes providing a substrate having a plurality of connection pads; mounting a chip on the substrate, wherein the chip comprises a plurality of copper-containing bumps directly coupled to the connection pads, and each of the copper-containing bumps comprises a ring surface; forming an anti-dissociation gel between the substrate and the chip, wherein the anti-dissociation gel comprises a plurality of anti-dissociation substances, and the ring surfaces of the copper-containing bumps are covered by the anti-dissociation substances. | 08-22-2013 |
20130249081 | METHOD FOR MANUFACTURING FINE-PITCH BUMPS AND STRUCTURE THEREOF - A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer. | 09-26-2013 |
20130249089 | METHOD FOR MANUFACTURING FINE-PITCH BUMPS AND STRUCTURE THEREOF - A method for manufacturing fine-pitch bumps comprises the steps of providing a silicon substrate; forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first zones and a plurality of second zones; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer to form a plurality of opening slots; forming a plurality of copper bumps at the opening slots, wherein each of the copper bumps comprises a first top surface and a ring surface; heating the photoresist layer to form a plurality of body portions and a plurality of removable portions; etching the photoresist layer; and removing the second zones to enable each of the first zones to form an under bump metallurgy layer having a bearing portion and an extending portion. | 09-26-2013 |
20130252374 | SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF - A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances. | 09-26-2013 |
20130256882 | METHOD FOR MANUFACTURING FINE-PITCH BUMPS AND STRUCTURE THEREOF - A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer. | 10-03-2013 |
Patent application number | Description | Published |
20120001266 | GATE STRUCTURES AND METHOD OF FABRICATING SAME - A method includes: forming first and second projections; forming a first structure engaging the first projection, and including: a non-metallic conductive layer, and a first opening over the conductive layer; forming a second structure engaging the second projection, and including: a second opening; and conformally depositing a pure metal in the first and second openings. A different aspect involves an apparatus including: a first device that includes a first projection and a first gate structure, the first projection extending from a substrate, and the first gate structure engaging the first projection, and including an opening, and a conformal, pure metal disposed in the opening; and a second device that includes a second projection and a second gate structure, the second projection extending from the substrate, and the second gate structure engaging the second projection, and including a silicide including a metal that is the same metal disposed in the opening. | 01-05-2012 |
20120319192 | Gate Structures - An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening. | 12-20-2012 |
20130240979 | GATE STRUCTURES - A semiconductor device is provided. The device includes a semiconductor substrate, first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein, and a first gate structure engaging the first projection adjacent the first channel region. The first gate structure includes a first dielectric material over the first channel region, a first opening over the first dielectric material and the first channel region, and a pure first metal with an n-type work function value conformally deposited in the first opening. The device also includes a second gate structure engaging the second projection adjacent the second channel region. The second gate structure includes a second dielectric material over the second channel region, a second opening over the second dielectric material and the second channel region, and a pure second metal with a p-type work function value conformally deposited in the second opening. | 09-19-2013 |
Patent application number | Description | Published |
20090161467 | MEMORY DEVICE AND REFRESH METHOD THEREOF - A memory device and a refresh method are provided herein. The memory device includes a memory array having memory rows. When an array refresh strobe (ARS) signal is received, it is determined whether the memory rows are required to be refreshed according to tag flags and reset statuses corresponding to the memory rows. When a row refresh strobe (RRS) signal is received, it is determined whether to refresh one of the memory rows according to a plurality of parameters including a value of a row to refresh counter, a value of a refresh deadline counter and/or a queue. When it is decided to start a refresh operation, one of the memory rows is selected according to the tag flag and the status, and the status of the selected memory row is updated after the selected memory row is refreshed. | 06-25-2009 |
20100238312 | IMAGE SENSOR HAVING OUTPUT OF INTEGRAL IMAGE - An image sensor having an output of an integral image is provided. The image sensor includes a pixel circuit, a line accumulator, and a volume accumulator. The pixel circuit includes a plurality of pixels for capturing pixel values of the pixels. The line accumulator is used for accumulating the pixel values of the pixels from a first pixel to a target pixel in a target pixel line of the image so as to obtain an accumulated line pixel value. The volume accumulator is used for adding the accumulated line pixel value output by the line accumulator to an integral pixel value of the pixel corresponding to the target pixel in a previous pixel line of the target pixel line, and using an adding result as the integral pixel value of the target pixel, so as to output the integral pixel value of the target pixel to form an integral image. | 09-23-2010 |
20100321905 | CARD STRUCTURE, SOCKET STRUCTURE, AND ASSEMBLY STRUCTURE THEREOF - A card structure includes a first element and a second element. The first element includes a first peripheral portion and a plurality of first contact points exposed by the first peripheral portion. The second element includes a second peripheral portion and a plurality of second contact points corresponding to the first contact points of the first element and exposed by the second peripheral portion. When the first and second elements are joined with each other, the first peripheral portion of the first element and the second peripheral portion of the second element are adjacent to each other, to juxtapose the first contact points of the first element and the second contact points of the second element to each other. The juxtaposed first and second contact points of the first and second elements are coupled to each other by a welding portion. | 12-23-2010 |
20110072242 | CONFIGURABLE PROCESSING APPARATUS AND SYSTEM THEREOF - A configurable processing apparatus includes a plurality of processing units, at least an instruction synchronization control circuit, and at least a configuration memory. Each processing apparatus has a stall-output signal generating circuit to output a stall-output signal, wherein the stall-output signal indicates that an unexpected stall is occurred in the processing unit. The processing unit has a stall-in signal, and an external circuit of the processing unit can control whether the processing unit is stalled according to the stall-in signal. The instruction synchronization control circuit generates the stall-in signals to the processing units in response to a content stored in the configuration memory and the stall-output signals of the processing units, so as to determine operation modes and instruction synchronization of the processing units. | 03-24-2011 |
20110217878 | ELECTRONIC DEVICE, ADAPTER AND RECEPTACLE - An electronic device, an adapter and a receptacle are provided. The electronic device includes a card body, a plurality of first and second terminals, and at least one stub. The card body has a front edge, a first surface and a second surface opposite to the first surface. The first terminals are between the first terminals and the front edge. The stub is disposed on the second surface and near the front edge. The adapter includes a body and a plurality of elastic terminals. The body has an accommodating portion for accommodating an electronic device. One ends of the elastic terminals are fixed to the body. When the electronic device is accommodated at the accommodating portion, a plurality of flat terminals of the electronic device are outside of the accommodating portion, and another ends of the elastic terminals are against the flat terminals correspondingly. | 09-08-2011 |
20120057867 | OPTICAL USB THIN CARD - Exemplary embodiments of optical USB thin card is disclosed, which includes a substrate, having a space formed inside its packaging layer; a seat, disposed at a position on the substrate while forming an opening on the substrate; a plurality of first contact elements, each being disposed on the seat to be used for connecting electrically with an external device; a plurality of second contact elements, each being disposed on the seat to be used for connecting electrically with an external device; and bidirectional optical transmission module, having a plurality of optical fiber, disposed inside an accommodation space formed by the enclosure of the seat and the substrate; a micro control unit, for processing signals, data and commands of the optical USB thin card. | 03-08-2012 |
20130077274 | CARD STRUCTURE, SOCKET STRUCTURE, AND ASSEMBLY STRUCTURE THEREOF - A card structure for a socket structure provided with a plurality of first elastic plates and a plurality of second elastic plates is disclosed, and the card structure includes a body, a plurality of first pad portions, and a plurality of second pad portions. The body includes a outer surface. The plurality of first and second pad portions are respectively disposed on the outer surface of the body and corresponding to the plurality of first and second elastic plates of the socket structure and respectively contact the plurality of first and second elastic plates of the socket structure when the card structure is disposed on the socket structure. | 03-28-2013 |
20130094158 | CARD STRUCTURE, SOCKET STRUCTURE, AND ASSEMBLY STRUCTURE THEREOF - A card structure includes a first substrate, a second substrate, an intermediate unit, and a connector. The first substrate includes a base surface. The second substrate is disposed on the base surface of the first substrate and coupled to the first substrate. The connector is disposed on the base surface of the first substrate to juxtapose the second substrate via the intermediate unit and coupled to the first substrate. | 04-18-2013 |
20130095674 | CARD STRUCTURE, SOCKET STRUCTURE, AND ASSEMBLY STRUCTURE THEREOF - A card structure includes a first substrate, a second substrate, and a connector. The first substrate includes a base surface, wherein at least one electronic part region and a terminal region are disposed on the base surface. The second substrate is disposed on the base surface and is coupled to the terminal region of the first substrate. The connector is disposed on the base surface to juxtapose the second substrate. The connector includes a connecting surface, a contact unit, and a plurality of contact regions disposed on the connecting surface and coupled to the contact unit and the terminal region, such that the plurality of contact regions are coupled to the second substrate via the terminal region of the first substrate. | 04-18-2013 |
20140021802 | USB SSIC THIN CARD DEVICE AND DATA TRANSFER METHOD THEREOF - A USB SSIC thin card device and a data transfer method thereof are provided. A first universal serial bus (USB) physical layer circuit is controlled by a USB device control unit to transmit data through a pair of first differential signal pins and a pair of a second differential signal pins, wherein the first USB physical layer circuit is used to transmit data complied with a USB 3.0 SSIC transmission specification. | 01-23-2014 |
20140223063 | USB SSIC REMOVABLE ELECTRONIC DEVICE AND THE ADAPTOR THEREOF - A USB SSIC removable electronic device includes a first receiving terminal pair, a first transmitting terminal pair, a MIPI/SSIC-PHY/Link layer, a function module, at least one power terminal and a ground terminal. The first receiving terminal pair receives data compatible with a USB SSIC interface. The first transmitting terminal pair transmits data compatible with the USB SSIC interface. The MIPI/SSIC-PHY/Link layer receives data compatible with the USB SSIC interface from the first receiving terminal pair, and transmits data compatible with the USB SSIC interface to the first transmitting terminal pair. The function module transmits data with the MIPI/SSIC-PHY/Link layer by the transmission protocol of the USB SSIC interface. The power terminal provides at least one source voltage for the MIPI/SSIC-PHY/Link layer and the function module. | 08-07-2014 |
Patent application number | Description | Published |
20090259138 | AUTOMATIC BIO-SIGNAL SUPERVISING SYSTEM FOR MEDICAL CARE - The present invention discloses an automatic bio-signal supervising system for medical care. The automatic bio-signal supervising system utilizes a head-mounted bio-signal acquisition device, wore upon the user's head, to acquire the bio-signals, convert them into the digital bio-signals, and transmit the digital bio-signals to a signal analysis processor to perform analysis process. And the automatic bio-signal supervising system delivers a corresponding control signal to the environment control equipment based on the result of analysis, and control the environment condition to achieve the remote supervising and medical care purpose. Furthermore, the signal analysis processor in the present invention further provides a real-time warning signal or a health index, which supervise the personal biological information to avoid the unpredictable situation. | 10-15-2009 |
20110063073 | TACTILE REMOTE CONTROL SYSTEM - The present invention discloses a tactile remote control system, which uses a processor to integrate the operation selection items of controlled devices and arrange the selection items into a graphic user interface, and which uses a microswitch to output instructions. The processor arranges the graphic user interfaces of a controlled device hierarchically. Therefore, the graphic user interfaces have organizationality, logicality and continuity. The user watches the display and operates the microswitches to remotely control the controlled devices. The present invention integrates the control functions to assist the user to control the daily-life electronic devices and household appliances. The present invention enables any one, who has been briefly instructed, to remotely control the linked devices by his will. | 03-17-2011 |
20120065478 | INTERACTIVE BIOSENSING DEVICE AND METHOD THEREOF - The present invention discloses an interactive biosensing device and a method thereof. The interactive biosensing device is arranged on a living body and comprises a physiological detection module detecting physiological signals of the living body; a physical sensation module triggering at least one physical device according to control instructions; a first wireless transmission module receiving control instructions or sends out physiological signals; a storage module storing physiological signals and control instructions; a video module capturing images of the living body; a control module processing physiological signals and control instructions and controlling operations of the video module; and a display unit presenting the images captured by the video module. | 03-15-2012 |
20130242077 | IMAGE CONTROL SYSTEM ABLE TO DETECT ELECTROOCULOGRAPHY - An image control system able to detect electrooculography (EOG) is provided. The system detects EOG signals of a user through an electrooculography detection device and wirelessly transmits the signals to an external signal processing device. The external signal processing device calculates a position the user is staring at according to the signal received and presents on a display unit a sharp image of the position. Thereby, the present invention makes the user enjoy the feeling of watching real objects although the user is viewing a photo presented on the display in fact. Thus is optimized the visional quality in viewing photos. | 09-19-2013 |
20140058243 | BIOSENSOR ELECTRODE DEVICE AND METHOD FOR FABRICATING THE SAME - A biosensor electrode device and a method for fabricating the same are disclosed. The biosensor electrode device comprises a conductive substrate; at least one conductive spring, at least one probe, and an encapsulation member. Two ends of the conductive spring respectively connect with the conductive substrate and the probe. The probe moves close to or far away from the substrate through the elastic deformation of the conductive spring. The encapsulation member wraps the conductive substrate, the conductive springs and the probes but reveals a portion of each probe. The revealed probes contact skin of a testee for biomedical measurement. The device and method of the present invention can reduce the cost in mass-production. The biosensor electrode device will be a mainstream instrument in biomedical measurement. | 02-27-2014 |
Patent application number | Description | Published |
20110019013 | METHOD FOR ADJUSTING PHOTOGRAPHING SETTINGS OF DIGITAL CAMERA THROUGH MOTION DETECTION - A method for adjusting photographing settings of a digital camera through motion detection, for determine to adjust the photographing settings of the digital camera according to vibrations of the digital camera or shaking of a photographed object. The adjusting method includes the following steps. At least two continuous pre-photographed images are captured. A central area and an edge area are set at same positions in the pre-photographed images respectively. Feature points are found in the pre-photographed images. A local motion vector and a camera motion vector are respectively determined according to a relation of the feature points on the central area and the edge area. A subject motion vector is generated according to a difference between the local motion vector and the camera motion vector. Adjustment of the photographing settings of the digital camera is determined according to a maximum value in the subject motion vector and camera motion vector. | 01-27-2011 |
20120106834 | BACKGROUND MODEL LEARNING SYSTEM FOR LIGHTING CHANGE ADAPTATION UTILIZED FOR VIDEO SURVEILLANCE - Surveillance systems often encounter great challenges from lighting variations, especially for those inspecting outdoor environments. To construct a surveillance system robust to various background scene changes, including lighting variations, a strategy of background model learning is widely adopted. Based on this strategy, many approaches have been proposed in decades to represent background scenes by statistical models and to adapt background changes over time into the models. However, the focus of most background model learning research is put on adaptation of scene vibrations in to background, as well as of gradual lighting variations. For the background model adaptation to drastic lighting changes, many background model learning approaches are often inefficient. As a result, false alarms in foreground detection are issued under such quick lighting changes. To suppress this kind of false alarms, a new system design of background model learning is proposed. | 05-03-2012 |
20120140066 | VIDEO SURVEILLANCE SYSTEM BASED ON GAUSSIAN MIXTURE MODELING WITH TWO-TYPE LEARNING RATE CONTROL SCHEME - To construct a video surveillance system, the Gaussian mixture modeling (GMM) is a popular choice among various background modeling approaches, for its capability of adaptation to background variations. However, the GMM often suffers from a tradeoff between robustness to background changes and sensitivity to foreground abnormalities, and is inefficient in managing the tradeoff for diverse surveillance scenarios. In the present invention, we identify that such a tradeoff can be easily controlled by a new computational scheme of two-type learning rate control for the GMM. Based on the proposed rate control scheme, a new video surveillance system that applies feedbacks of pixel properties computed in object-level analysis to the learning rate controls of the GMM in pixel-level background modeling is developed. Such a system gives better regularization of background adaptation and is efficient in resolving the tradeoff for many surveillance applications. | 06-07-2012 |
20120320162 | VIDEO OBJECT LOCALIZATION METHOD USING MULTIPLE CAMERAS - An efficient 3D object localization method using multiple cameras is provided. The proposed method comprises a three-dimensional object localization process that firstly generates a plurality of two-dimensional line samples originated from a pre-calibrated vanishing point in each camera view for representing foreground video objects, secondly constructs a plurality of three-dimensional line samples from the two-dimensional line samples in all the multiple camera views, and thirdly determines three-dimensional object to locations by clustering the three-dimensional line samples into object groups. | 12-20-2012 |
Patent application number | Description | Published |
20120039129 | COST SAVING ELECTRICALLY-ERASABLE-PROGRAMMABLE READ-ONLY MEMORY (EEPROM) ARRAY - A cost saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit lines; the word line includes a first and a second word lines; and the common source line includes a first common source line. And, a plurality of sub-memory arrays are provided. Each sub-memory array includes a first and a second memory cells disposed opposite to each other and located on two different sides of the first common source line; the first memory cell is connected to the first group bit lines, the first common source line, and the first word line, and the second memory cell is connected to the first group bit line, the first common source line, and the second word line. | 02-16-2012 |
20120039131 | LOW-VOLTAGE EEPROM ARRAY - A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines include a first common source line and a second common source line. The low-voltage EEPROM array also has a plurality of sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell connects with the first bit line, the first common source line and the first word line. The second memory cell connects with the first bit line, the second common source line and the second word line. The first and second memory cells are symmetrical and arranged between the first and second common source lines. | 02-16-2012 |
20120040504 | METHOD FOR INTEGRATING DRAM AND NVM - The present invention discloses a method for integrating DRAM and NVM, which comprises steps: sequentially forming on a portion of surface of a DRAM semiconductor substrate a first gate insulation layer and a first gate layer functioning as a floating gate; and implanting ion into regions of the semiconductor substrate, which are at two sides of the first gate insulation layer, to form two heavily-doped areas that are adjacent to the first gate insulation layer and respectively function as a drain and a source; respectively forming over the first gate layer a second gate insulation layer and a second gate layer functioning as a control gate. The present invention not only increases the transmission speed but also reduces the power consumption, the fabrication cost and the package cost. | 02-16-2012 |
20130181276 | NON-SELF ALIGNED NON-VOLATILE MEMORY STRUCTURE - A non-self aligned non-volatile memory structure includes a semiconductor substrate; a first gate insulation layer on said semiconductor substrate; a floating gate on first gate insulation layer; two doped regions in said semiconductor substrate, which are respectively on two sides of said first gate insulation layer, and adjoining said first gate insulation layer; a second gate insulation layer on said floating gate; and a control gate on said second gate insulation layer. Width of said control gate on said floating gate is less than that of said floating gate, and width of said control gate not on said floating gate is equal to or greater than width of said floating gate. Through the two non-self aligned gates, the non-volatile memory does not need to meet the requirement of gate line-to-line alignment, thus reducing complexity and cost of manufacturing process. | 07-18-2013 |
20130334586 | NON-SELF-ALIGNED NON-VOLATILE MEMORY STRUCTURE - A non-self-aligned non-volatile memory structure, comprising: a semiconductor substrate; a left floating gate memory cell and a right floating gate memory cell; a control gate; and a gate insulation layer disposed among said two floating gate memory cells and said control gate. Drains of said two floating gate memory cells are connected to different voltage levels. Said control gate is over said two floating gate memory cells, to cover said floating gates of said two floating gate memory cells, so as to control said two floating gates simultaneously. Said non-self-aligned non-volatile memory structure mentioned above does not require line-to-line alignment of gates, thus reducing significantly the complexity of manufacturing process, and number of layers of photo masks required, in achieving production cost reduction. | 12-19-2013 |
Patent application number | Description | Published |
20110127563 | DIE-BONDING METHOD OF LED CHIP AND LED MANUFACTURED BY THE SAME - A die-bonding method is suitable for die-bonding a LED chip having a first metal thin-film layer to a substrate. The method includes forming a second metal thin film layer on a surface of the substrate; forming a die-bonding material layer on the second metal thin film layer; placing the LED chip on the die-bonding material layer with the first metal thin film layer contacting the die-bonding material layer; heating the die-bonding material layer at a liquid-solid reaction temperature for a pre-curing time, so as to form a first intermetallic layer and a second intermetallic layer; and heating the die-bonding material layer at a solid-solid reaction temperature for a curing time, so as to perform a solid-solid reaction. The liquid-solid reaction temperature and the solid-solid reaction temperature are both lower than 110° C., and a melting point of the first and second intermetallic layers after the solid-solid reaction is higher than 200° C. | 06-02-2011 |
20110156071 | MULTI-STACK PACKAGE LED - A multi-stack package light emitting diode (LED) includes an LED chip, a first fluorescent powder layer, a first optical bandpass filter layer and a second fluorescent powder layer. The LED chip generates an LED light. The first fluorescent powder layer and the second fluorescent powder layer respectively have a first fluorescent powder and a second fluorescent powder. The first fluorescent powder and the second fluorescent powder are excited by the LED light to respectively generate a first excitation light and a second excitation light. The first optical bandpass filter layer allows the LED light and the first excitation light to pass and reflects the second excitation light. A wavelength of the LED light is shorter than a wavelength of the second excitation light. The wavelength of the second excitation light is shorter than a wavelength of the first excitation light. Therefore, the multi-stack package LED improves a light emission efficiency. | 06-30-2011 |
20120256228 | DIE-BONDED LED - An LED includes a first intermetallic layer, a first metal thin film layer, an LED chip, a substrate, a second metal thin film layer, and a second intermetallic layer. The first metal thin film layer is located on the first intermetallic layer. The LED chip is located on the first metal thin film layer. The second metal thin film layer is located on the substrate. The second intermetallic layer is located on the second metal thin film layer, and the first intermetallic layer is located on the second intermetallic layer. Materials of the first and the second metal thin film layer are selected from a group consisting of Au, Ag, Cu, and Ni. Materials of the intermetallic layers are selected from a group consisting of a Cu—In—Sn intermetallics, an Ni—In—Sn intermetallics, an Ni—Bi intermetallics, an Au—In intermetallics, an Ag—In intermetallics, an Ag—Sn intermetallics, and an Au—Bi intermetallics. | 10-11-2012 |
20150061115 | INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF - A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b). | 03-05-2015 |
Patent application number | Description | Published |
20100043780 | SOLAR CELL AND MANUFACTURING METHOD THEREOF - A solar cell includes a substrate, a chip, a convex lens structure, and an infrared filter. The substrate has a groove in which the chip is placed. The chip can transform light energy into electric energy. Furthermore, the convex lens structure is placed over the groove. The infrared filter is attached to the incident surface of the convex lens structure. | 02-25-2010 |
20100049181 | MEDICAL LIGHT DEVICE - A medical light device includes a main body, a light source, a filler, and a contact part. A cavity, receiving a light source, is disposed on the main body. The filler is composed of transparent material, filled inside the cavity, and covers the light source. The contact part, composed of soft and transparent material, is placed adjacent to the filler, covering the surface of the filler. The refractive index difference between the contact part and the filler is smaller than the refractive index difference between the filler and air. | 02-25-2010 |
20110068358 | PHOTOELECTRIC DEVICE, METHOD OF FABRICATING THE SAME AND PACKAGING APPARATUS FOR THE SAME - A method for fabricating a photoelectric device initially provides a ceramic substrate comprising a thermal dissipation layer on a bottom layer of the ceramic substrate, an electrode layer on the top surface of the ceramic substrate, and a reflective structure in cavities of the ceramic substrate. Next, a plurality of photoelectric dies is disposed on the top surface of the ceramic substrate. Then, a first packaging layer is formed on the top surfaces of the photoelectric dies. Next, the ceramic substrate is placed between an upper mold and a lower mold. Finally, a plurality of lenses is formed on the top surface of the first packaging layer by using an injection molding technique or a transfer molding technique. | 03-24-2011 |
Patent application number | Description | Published |
20110001250 | METHOD AND STRUCTURE FOR ADHESION OF INTERMETALLIC COMPOUND (IMC) ON CU PILLAR BUMP - A method and structure for good adhesion of Intermetallic Compounds (IMC) on Cu pillar bumps are provided. The method includes depositing Cu to form a Cu pillar layer, depositing a diffusion barrier layer on top of the Cu pillar layer, and depositing a Cu cap layer on top of the diffusion barrier layer, where an intermetallic compound (IMC) is formed among the diffusion barrier layer, the Cu cap layer, and a solder layer placed on top of the Cu cap layer. The IMC has good adhesion on the Cu pillar structure, the thickness of the IMC is controllable by the thickness of the Cu cap layer, and the diffusion barrier layer limits diffusion of Cu from the Cu pillar layer to the solder layer. The method can further include depositing a thin layer for wettability on top of the diffusion barrier layer prior to depositing the Cu cap layer. | 01-06-2011 |
20120024456 | SUBSTRATE BONDING SYSTEM AND METHOD OF MODIFYING THE SAME - The embodiments described provide apparatus and methods for bonding wafers to carriers with the surface contours of plates facing the substrates or carriers are modified either by re-shaping, by using height adjusters, by adding shim(s), or by zoned temperature control. The modified surface contours of such plates compensate the effects that may cause the non-planarity of bonded substrates. | 02-02-2012 |
20130134581 | PLANARIZED BUMPS FOR UNDERFILL CONTROL - The mechanisms for forming bump structures reduce variation of standoffs between chips and package substrates. By planarizing the solder layer on bump structures on chips and/or substrates after plating, the heights of bump structures are controlled to minimize variation due to within die and within wafer locations, pattern density, die size, and process variation. As a result, the standoffs between chips and substrates are controlled to be more uniform. Consequently, underfill quality is improved. | 05-30-2013 |
20130168848 | PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING THE SEMICONDUCTOR DEVICE - The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved. | 07-04-2013 |
20140127863 | METHOD OF FORMING A PLURALITY OF BUMPS ON A SUBSTRATE AND METHOD OF FORMING A CHIP PACKAGE - A method of forming a plurality of bump structures on a substrate includes forming an under bump metallurgy (UBM) layer on the substrate, wherein the UBM layer contacts metal pads on the substrate. The method further includes forming a photoresist layer over the UBM layer, wherein the photoresist layer defines openings for forming the plurality of bump structures. The method further includes plating a plurality of layers in the openings, wherein the metal layers are part of the plurality of bump structures. The method further includes planarizing the plurality of bump structures after the metal layers are plated to a targeted height from a surface of the substrate. | 05-08-2014 |
20150021784 | FRONT-TO-BACK BONDING WITH THROUGH-SUBSTRATE VIA (TSV) - Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer includes a first transistor formed in a front-side of the first semiconductor wafer, and the second semiconductor wafer includes a second transistor formed in a front-side of the second semiconductor wafer. A backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device structure further includes an interconnect structure formed over the front-side of the second semiconductor wafer, and at least one first through substrate via (TSV) directly contacts a conductive feature of the first semiconductor wafer and the interconnect structure. | 01-22-2015 |
20150021785 | HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV) - Embodiments of forming a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a first polymer material and a second conductive material embedded in a second polymer material. The first conductive material is bonded to the second conductive material and the first polymer material is bonded to the second polymer material. The semiconductor device also includes at least one through silicon via (TSV) extending from a bottom surface of the first semiconductor wafer to a metallization structure of the first semiconductor wafer. The semiconductor device structure also includes an interconnect structure formed over the bottom surface of the first semiconductor wafer, and the interconnect structure is electrically connected to the metallization structure via the TSV. | 01-22-2015 |
Patent application number | Description | Published |
20090267844 | WIDEBAND AND DUAL-BAND N-ORDER MONOPOLE ANTENNA AND PRINTED CIRCUIT BOARD THEREOF - A wideband and dual-band n-order monopole antenna comprises an antenna body, a 5 GHz band matching branch, a 5 GHz band first-order branch, a 5 GHz band second-order branch, a 2.4 GHz band branch and a 2.4 GHz band matching branch. The antenna body is shaped substantially like an inverted “L,” including a first side and a second side, wherein the first side is substantially perpendicular to the second side. The 5 GHz band matching branch extends from the first side. The 5 GHz band first-order branch extends from the first side and in parallel to the 5 GHz band matching branch. The 5 GHz band second-order branch extends from the second side and is perpendicular to the 5 GHz band first-order branch. The 2.4 GHz band branch is connected to the second side through an extending arm, the combination of the extending arm and the 2.4 GHz band branch being shaped substantially like an “L.” The 2.4 GHz band matching branch extends outward from the second side. | 10-29-2009 |
20100085270 | BALANCED PIFA AND METHOD FOR MANUFACTURING THE SAME - A balanced patched inverse F antenna comprises a radiation conductor and a balun circuit. The radiation conductor includes a main body, a first branch and a second branch. The balun circuit includes an unbalanced port, a balanced port, and first, second, third and fourth components, with the first, second, third and fourth components being serially connected. A feeding input of the unbalanced port is connected to the second and third components, a grounding wire of the unbalanced port is connected to the first and fourth components, an inverting terminal of the balanced port is connected to the first and second components, a non-inverting terminal of the balanced port is connected to the third and fourth components, and the inverting and non-inverting terminals are respectively connected to the first and second branches. | 04-08-2010 |
20110102288 | ANTENNA APPARATUS - An antenna apparatus comprises a planar monopole antenna device and an extending layer. The planar monopole antenna device includes an electromagnetic shielding box. The extending layer is composed of electric conducting material and extends outward from a feed point of the electromagnetic shielding box. | 05-05-2011 |
Patent application number | Description | Published |
20090235365 | DATA ACCESS SYSTEM - A data access system includes a host and a storage device. The host has a security setup function and includes a first identity code storage block to store a first identity code. The storage device has a security check function and includes a second identity code storage block. The host executes the security setup function to set a second identity code according to the first identity code, and the second identity code is stored into the second identity code storage block. The storage device executes the security check function to determine if the host is allowed to access the storage device according to the first and second identity codes. | 09-17-2009 |
20090270071 | MOBILE PHONE ACCESSING SYSTEM AND RELATED STORAGE DEVICE - The present invention provides a mobile phone accessing system. The mobile phone accessing system comprises: a mobile phone having a first International Mobile Equipment Identity (IMEI) code; and a storage device comprising a first storage region for storing data, a second storage region for storing a second IMEI code, and a controller coupled to the first storage region and the second storage region for executing a security check function to determine whether the mobile phone is qualified to access the first storage region according to the first IMEI code. | 10-29-2009 |
20090270129 | MOBILE PHONE ACCESSING SYSTEM AND RELATED STORAGE DEVICE - The present invention provides a mobile phone accessing system. The mobile phone accessing system comprises: a mobile phone having a first Subscriber Identity Module (SIM) specification corresponding to a SIM card; and a storage device comprising a first storage region for storing data, a second storage region for storing a second SIM specification, and a controller coupled to the first storage region and the second storage region for executing a security check function to determine whether the mobile phone is qualified to access the first storage region according to the first SIM specification. | 10-29-2009 |
20090271585 | DATA ACCESSING SYSTEM AND RELATED STORAGE DEVICE - A data accessing system includes a host computer and a storage device. The host computer has a first media access control (MAC) address, and the storage device includes a first storage region, a second storage region, and a controller. The first storage region is utilized for storing data. The second storage region stores a second media access control address. The controller couples to the first storage region and the second storage region for executing a security checking function to determine if the host computer is qualified to access the first storage region according to the first media access control address. | 10-29-2009 |
Patent application number | Description | Published |
20080310199 | POWER SUPPLY PROTECTION APPARATUS AND RELATED METHOD - A power supply protection method for a power supply device includes: detecting whether an output voltage of the power supply device reaches a voltage protection threshold to generate a detection result; generating a first control signal according to a power good input signal and the detection result; utilizing a fault protection circuit to decide whether to output a fault protection signal according to the first control signal; and using a short circuit protection circuit to receive the power good input signal and determining whether to generate a second control signal according to the power good input signal. When the power good input signal is not enabled during a specific time after the power supply device is started, the short circuit protection circuit is directly used to generate the second control signal into the fault protection circuit for triggering the fault protection circuit to output the fault protection signal. | 12-18-2008 |
20140071718 | FLY-BACK POWER CONVERTING APPARATUS - A structure of a fly-back power converting apparatus is disclosed. The structure includes a power transistor, a current detector, a pulse width modulation (PWM) signal generator and a current limiter. The power transistor is coupled to an input voltage and receives a PWM signal. The current detector detects a current output from the power transistor and generates a detecting voltage according to the current. The PWM signal generator generates the PWM signal according to a comparing result by comparing the detecting voltage and a standard voltage. The current limiter generates the standard voltage according to a turn-on time of the power transistor. | 03-13-2014 |
20140159684 | BUCK POWER CONVERTER - A buck power converter includes a power transistor, an inductor, a first diode, and an anti-ringing circuit. The power transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the power transistor receives an input voltage, and the control terminal of the power transistor receives a pulse width modulation (PWM) signal. The anti-ringing circuit detects a detection voltage on the second terminal of the power transistor. According to the detection voltage, the anti-ringing circuit provides at least one second diode serially coupled between the second terminal of the power transistor and a reference ground terminal in a forward-biased manner, so as to clamp a voltage swing of the detection voltage. | 06-12-2014 |
20140176104 | BUCK VOLATGE CONVERTING APPARATUS - A buck voltage converting apparatus is disclosed. The buck voltage converting apparatus includes a first transistor, a second transistor, an inductor, a controller and a switch. The first transistor receives an input voltage. A first terminal of the inductor is coupled to the first and second transistors. A second terminal of the inductor is coupled to an output terminal of the buck voltage converting apparatus for generating an output voltage. The controller receives the output voltage, and generates a detection voltage according to voltage amplitude of the output voltage. The switch is coupled between a first terminal of the first transistor and a control terminal of the second transistor. The switch is turned on or off according to the detection voltage. | 06-26-2014 |
Patent application number | Description | Published |
20120032322 | FLIP CHIP PACKAGE UTILIZING TRACE BUMP TRACE INTERCONNECTION - A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate. | 02-09-2012 |
20120032343 | PACKAGE SUBSTRATE FOR BUMP ON TRACE INTERCONNECTION - A package substrate including a conductive pattern disposed on a die attach surface of the package substrate; at least one bumping trace inlaid into the conductive pattern; and at least one gap disposed along with the bumping trace in the conductive pattern to separate the bumping trace from a bulk portion of the conductive pattern. The bumping trace may have a lathy shape from a plan view and a width substantially between 10 μm and 40 μm and a length substantially between 70 μm and 130 μm, for example. | 02-09-2012 |
20130140694 | FLIP CHIP PACKAGE UTILIZING TRACE BUMP TRACE INTERCONNECTION - A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate. | 06-06-2013 |
20130221536 | ENHANCED FLIP CHIP STRUCTURE USING COPPER COLUMN INTERCONNECT - A flip chip package includes a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein the copper column is disposed on one side of the capture pad about the via opening only. | 08-29-2013 |
Patent application number | Description | Published |
20090238444 | OPTICAL IMAGING APPARATUS AND METHOD FOR INSPECTING SOLAR CELLS - An optical imaging apparatus for inspecting a solar cell includes a power supply configured to apply a reverse biased voltage to the solar cell such that shunt defects in the solar cell will generate heat, a thermal imaging device configured to obtain the thermal image of the solar cell, a computing unit including a thermal image analysis module configured to identify hot spots in the thermal image, a locating module configured to locate the center positions of the hot spots, a visible image analysis module configured to identify the defect features of the hot spots, and a visible light imaging device configured to acquire visible images of the hot spots. | 09-24-2009 |
20100288012 | APPARATUS FOR TESTING BONDING STRENGTH OF ELECTRICAL CONNECTIONS AND FRICTIONLESS CALIBRATION DEVICE FOR THE SAME - An apparatus for testing bonding strength of electrical connection comprises a platform including a two-axis drive, a device holder positioned on the two-axis drive and configured to receive an electronic device, a vertical drive positioned on the platform, a cantilever positioned on the vertical drive, and a test head connected in a rotational manner with the cantilever. A frictionless calibration device for shear force testing comprises a base, two supporters positioned on the base, a shaft having two tapering ends positioned between the two supporters, and a calibration member fixed on the shaft, wherein the shaft and the calibration member contact the supporters in a rotational manner. | 11-18-2010 |
20140340068 | BANDGAP REFERENCE CIRCUIT - A bandgap reference circuit is provided and which includes an operating voltage, a current mirror, a first p-channel metal-oxide semiconductor (PMOS) transistor and an amplifier. The current mirror is coupled to the operating voltage. The first PMOS transistor is coupled to the operating voltage and the current mirror. The amplifier is coupled to the current mirror and the first PMOS transistor. When the bandgap reference circuit is activated, the operating voltage starts to supply voltage such that the first PMOS transistor is turned on first. When the operating voltage is higher than a preset voltage level, the first PMOS transistor is turned off, in order to complete an start-up process. | 11-20-2014 |
Patent application number | Description | Published |
20100034198 | METHOD AND GATEWAY FOR ROUTING INTERNATIONAL MOBILE TELEPHONE CALLS - A gateway for routing an international mobile telephone call comprises a storage device and a cost-saving routing module. The storage device is configured to store a mapping table and a call record table. The mapping table records a mobile phone number of a roaming subscriber and a fixed network number, and the call record table records a caller's phone number and the mobile phone number of the roaming subscriber. The cost-saving routing module is configured to establish a connection in accordance with the mapping table and call record table. | 02-11-2010 |
20110044306 | CALL SETUP METHOD FOR MOBILE VIRTUAL PRIVATE NETWORK AND ACCESS POINT APPARATUS THEREOF - A call setup method is provided for a MVPN which includes at least one access point apparatus, at least one database, and a plurality of users. The database records a private extension number, a user phone number, and a user identity module of each user and a link address of the corresponding access point apparatus. The access point apparatus corresponding to a MO user receives a call setup request message for setting up a call with a MT user from the MO user. The access point apparatus corresponding to the MO user determines whether the link address of the access point apparatus corresponding to the MT user is valid according to the database. If the link address of the access point apparatus corresponding to the MT user is valid, the MO user and the MT user set up the call through the access point apparatuses corresponding to the link addresses. | 02-24-2011 |
20120295599 | CALL SETUP METHOD FOR MOBILE VIRTUAL PRIVATE NETWORK AND ACCESS POINT APPARATUS THEREOF - A call setup method is provided for a MVPN which includes at least one access point apparatus, at least one database, and a plurality of users. The database records a private extension number, a user phone number, and a user identity module of each user and a link address of the corresponding access point apparatus. The access point apparatus corresponding to a MO user receives a call setup request message for setting up a call with a MT user from the MO user. The access point apparatus corresponding to the MO user determines whether the link address of the access point apparatus corresponding to the MT user is valid according to the database. If the link address of the access point apparatus corresponding to the MT user is valid, the MO user and the MT user set up the call through the access point apparatuses corresponding to the link addresses. | 11-22-2012 |
20120295627 | CALL SETUP METHOD FOR MOBILE VIRTUAL PRIVATE NETWORK AND ACCESS POINT APPARATUS THEREOF - A call setup method is provided for a MVPN which includes at least one access point apparatus, at least one database, and a plurality of users. The database records a private extension number, a user phone number, and a user identity module of each user and a link address of the corresponding access point apparatus. The access point apparatus corresponding to a MO user receives a call setup request message for setting up a call with a MT user from the MO user. The access point apparatus corresponding to the MO user determines whether the link address of the access point apparatus corresponding to the MT user is valid according to the database. If the link address of the access point apparatus corresponding to the MT user is valid, the MO user and the MT user set up the call through the access point apparatuses corresponding to the link addresses. | 11-22-2012 |
20130040644 | MOVEMENT PREDICTING METHOD - A movement predicting method is disclosed. The method utilizes at least one phone communicating in and moving between neighboring cells of base stations to predict population movement in a prediction interval. Firstly, obtain the traffic volumes in the cells generated by the phone and the handover information generated by the phone moving between the cells in a day. Next, calculate the traffic volumes and the handover information to obtain a movement probability for the population moving between the cells and an average residence time that the population stays in the region of each cell in the different periods of the day. Finally, according to the data obtained, predict an appearance probability that the population appears in each region at the end point of the prediction interval. | 02-14-2013 |
20140140207 | SYSTEM AND METHOD FOR REDUCING LOADS OF MOBILITY MANAGEMENT ENTITY (MME) IN CORE NETWORKS - The present invention provides a system and method for reducing loads of a mobility management entity in core networks. An object sending a connection-request message asking for network access to a base station through a wireless network; the base station receiving the connection-request message and sending it to core networks through a network; a mobility management entity (MME) in the core network receive the connection-request message. If the core network is busy and refuses to interconnect with the object, MME calculating according to a management rule a back-off time; MME transmitting a response message including the back-off time to the object through the base station, and the object sending out a connection-request message again after the back-off time has elapsed according to the response message. | 05-22-2014 |
Patent application number | Description | Published |
20110163994 | TOUCH SENSING SYSTEM, CAPACITANCE SENSING APPARATUS AND CAPACITANCE SENSING METHOD THEREOF - A touch sensing system includes a touch input interface and at least one capacitance sensing apparatus. The capacitance sensing apparatus includes a plurality of switch units and a differential sensing circuit. Each of the switch units is coupled to a corresponding sensing capacitor. A sensing input end of the differential sensing circuit receives a capacitance under test provided by at least one of the sensing capacitors. A reference input end of the differential sensing circuit receives a reference capacitance provided by at least one of the sensing capacitors. The differential sensing circuit compares the capacitance under test and the reference capacitance to output a first difference between the capacitance under test and the reference capacitance through an output end of the differential sensing circuit. A capacitance sensing method is also provided. | 07-07-2011 |
20110187390 | TOUCH SENSING SYSTEM, CAPACITANCE SENSING CIRCUIT, AND CAPACITANCE SENSING METHOD - A touch sensing system including a touch input interface and a capacitance sensing circuit is provided. The touch input interface includes a plurality of sensing capacitors for outputting a capacitance under test and a reference capacitance. The capacitance sensing circuit includes a first sensing channel, a second sensing channel, and a difference comparing unit. During a first period of the sensing period, the first sensing channel senses the capacitance under test, and the second sensing channel senses the reference capacitance. During a second period of the sensing period, the first sensing channel senses the reference capacitance, and the second sensing channel senses the capacitance under test. The difference comparing unit outputs a difference according to the capacitance under test and the reference capacitance. Additionally, a capacitance sensing method is also provided. | 08-04-2011 |
20110187663 | OBJECT SENSING APPARATUS, TOUCH SENSING SYSTEM, AND TOUCH SENSING METHOD - An object sensing apparatus including an object sensing unit, a signal selecting unit, at least one signal sensing unit, and a control unit is provided. The object sensing unit outputs a plurality of sensing signals. The signal selecting unit selects at least one of the sensing signals as a signal under test and selects at least one of the unselected sensing signals as a reference signal. The signal sensing unit outputs a difference signal according to the signal under test and the reference signal. The control unit determines an object position relative to the object sensing unit according to the difference signal. Additionally, a touch sensing apparatus and a method thereof are also provided. | 08-04-2011 |
20110193571 | TOUCH SENSING SYSTEM, CAPACITANCE SENSING CIRCUIT AND CAPACITANCE SENSING METHOD THEREOF - A touch sensing system which includes a touch input interface and a capacitance sensing circuit is provided. The touch input interface includes a plurality of sensing capacitors which output at least one waveform under test and at least one reference waveform. The capacitance sensing circuit includes a difference comparing unit. The difference comparing unit receives the waveform under test and the reference waveform and outputs a differential signal according to at least one positive edge difference and at least one negative edge difference between the waveform under test and the reference waveform. Furthermore, a capacitance sensing method is also provided. | 08-11-2011 |
20110210930 | SENSING AND DRIVING APPARATUS, TOUCH SENSING SYSTEM, AND SENSING AND DRIVING METHOD - A sensing and driving apparatus suitable for a sensing interface is provided. The sensing and driving apparatus includes a driving module and a sensing unit. The driving module outputs a first reference signal and a second reference signal which have different polarities with each other, and respectively transmits the first reference signal and the second reference signal to a first driving line and a second driving line of the sensing interface so as to generate a first sensing signal during a first period. The sensing unit receives the first sensing signal and detects a change of the first signal so as to generate a sensing result. A sensing and driving method, a touch sensing system and a device using the same are also provided herein. | 09-01-2011 |
20140002115 | CAPACITANCE SENSING METHOD | 01-02-2014 |
Patent application number | Description | Published |
20110254596 | SPREAD SPECTRUM CIRCUIT - A spread-spectrum circuit including an inverter, a current source, a control unit and a shaping circuit is provided. An input terminal of the inverter receives an original clock signal. The current source is coupled to a current transmission terminal of the inverter. The control unit includes a control circuit, and changes the current magnitude of the current source according to the original clock signal to control the charging/discharging speed of an output terminal of the inverter, so that the output terminal outputs a voltage signal. The shaping circuit shapes the voltage signal into a spread-spectrum clock signal. | 10-20-2011 |
20120075022 | DIFFERENTIAL AMPLIFIER - A differential amplifier includes a pair of input transistors, a pair of load transistors, a pair of impedance devices, a pair of auxiliary input transistors, and a pair of shield transistors is provided. The input transistors provide two input terminals. The load transistors provide two output terminals and two first terminals connected to first voltage. The impedance devices are coupled between the output terminals in series. The auxiliary input transistors have two control terminals respectively connected to the input terminals, two first terminals, and two second terminals. The input transistors and the auxiliary input transistors have reverse conductive type. The shield transistors has a pair of control terminals, a pair of first terminals respectively connected to the second terminals of the auxiliary input transistors and coupled to a second voltage through a pair of current sources, and a pair of second terminals respectively connected to the output terminals. | 03-29-2012 |
Patent application number | Description | Published |
20090157782 | RANDOM NUMBER GENERATOR AND RANDOM NUMBER GENERATING METHOD THEREOF - A random number generator and a random number generating method thereof are provided. The random number generator includes a signal generating unit and a sampling unit. The signal generating unit is adapted for memorizing a status of a noise generated during a transient of an output signal of an output buffer, and accordingly generating a frequency conversion signal which changes according to time and ambient factors. The sampling unit is coupled to the signal generating unit for receiving the frequency conversion signal, and sampling the frequency conversion signal according to a sampling clock pulse, so as to obtain a plurality of sets of unpredictable random number codes. | 06-18-2009 |
20090237852 | HOT PLUG ELECTRONIC DEVICE WITH HIGH USING SAFETY AND OVER-THERMAL PROTECTION DEVICE THEREOF - A hot plug electronic device with high using safety is provided. The hot plug electronic device includes an operation circuit, a voltage regulator and an over-thermal protection device. The operation circuit is used for communicating with an external host. The voltage regulator is coupled to the operation circuit for supplying power to the operation circuit. The over-thermal protection device is coupled to the voltage regulator for sensing the present temperature of the hot plug electronic device, and accordingly controlling the voltage regulator to normally supply/stop supplying the power to the operation circuit. | 09-24-2009 |
20100066458 | OSCILLATOR AND DRIVING CIRCUIT AND OSCILLATION METHOD THEREOF - An oscillator, a driving circuit and an oscillation method are provided. The driving circuit and a crystal are coupled in parallel to generate a clock signal. The driving circuit includes a buffer unit and a control unit. The buffer unit is coupled in parallel to the crystal, and used to amplify an oscillation signal outputted from the crystal to generate the clock signal. The control unit is coupled to the buffer unit, and used to generate a control signal to the buffer unit. The control unit determines a voltage level of the control signal by detecting whether the clock signal or the oscillation signal satisfies an oscillation condition of the crystal, so as to control a gain value of the buffer unit. Therefore, noise of different frequency bands loaded into the clock signal can be avoided. | 03-18-2010 |
20100252931 | FLASH MEMORY STORAGE APPARATUS - A flash memory storage apparatus is provided. The flash memory storage apparatus includes a substrate, a control and storage circuit unit, a ground lead, at least a signal lead, and a power lead. The control and storage circuit unit, the power lead, the signal lead, and the ground lead are disposed on the substrate, in which the power lead, the signal lead, and the ground lead respectively electrically connect to the control and storage circuit unit. Moreover, the flash memory storage apparatus further includes an extra ground lead electrically connected to the ground lead or a protrusion on the substrate, such that the ground lead first electrically connects to a host when the flash memory storage apparatus is plugged into the host. | 10-07-2010 |
20100264999 | OSCILLATION CIRCUIT, DRIVING CIRCUIT THEREOF, AND DRIVING METHOD THEREOF - An oscillation circuit, a driving circuit thereof, and a driving method thereof are provided. The driving circuit generates a second enable signal according to an output signal of an oscillator and a first enable signal. The second enable signal is transmitted to the oscillator. When a wave number of the output signal is smaller than a predetermined value during a predetermined period, the driving circuit adjusts a voltage level of the second enable signal. A voltage level of the first enable signal is equal to an enable voltage level. Through variations in voltage levels of the second enable signal, the oscillator is triggered to oscillate. | 10-21-2010 |
20110148475 | DRIVING CIRCUIT OF INPUT/OUTPUT INTERFACE - A driving circuit of an input/output (I/O) interface is provided. The driving circuit includes a main output stage and an enhancing unit. The main output stage receives at least one driving signal and outputs an output signal corresponding to an input signal accordingly. The enhancing unit is coupled to the main output stage. The enhancing unit receives and detects the level of the output signal so as to drive the output force of the main output stage in a first output level or a second output level, wherein the first output level is higher than the second output level. | 06-23-2011 |
20120230102 | FLASH MEMORY STORAGE APPARATUS - A flash memory storage apparatus is provided. The flash memory storage apparatus includes a substrate, a control and storage circuit unit, a ground lead, at least a signal lead, and a power lead. The control and storage circuit unit, the power lead, the signal lead, and the ground lead are disposed on the substrate, in which the power lead, the signal lead, and the ground lead respectively electrically connect to the control and storage circuit unit. Moreover, the flash memory storage apparatus further includes an extra ground lead electrically connected to the ground lead or a protrusion on the substrate, such that the ground lead first electrically connects to a host when the flash memory storage apparatus is plugged into the host. | 09-13-2012 |