Patent application number | Description | Published |
20140339626 | MEMORY DEVICE HAVING STITCHED ARRAYS OF 4 F+hu 2 +l MEMORY CELLS - A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts. | 11-20-2014 |
20150014800 | MTJ MEMORY CELL WITH PROTECTION SLEEVE AND METHOD FOR MAKING SAME - Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment of the present invention as applied to a memory cell comprises a top electrode layer, an upper magnetic layer, a barrier layer, a lower magnetic layer and a bottom electrode layer in a pillar formed on a landing pad; and a sleeve of dielectric material generally surrounding sidewalls of at least the barrier layer and the lower magnetic layer and partially surrounding the bottom electrode layer. The bottom electrode layer includes a ledge that extends under the sleeve of dielectric material and separates the sleeve of dielectric material from the landing pad under the bottom electrode layer. | 01-15-2015 |
20150014801 | Redeposition Control in MRAM Fabrication Process - Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode. | 01-15-2015 |
20150214278 | MEMORY DEVICE HAVING STITCHED ARRAYS OF 4 F+hu 2 +l MEMORY CELLS - A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts. | 07-30-2015 |
Patent application number | Description | Published |
20120241826 | ACCESS TRANSISTOR WITH A BURIED GATE - A magnetic memory cell is formed including a magneto tunnel junction (MTJ) and an access transistor, which is used to access the MTJ in operation. The access transistor, which is formed on a silicon substrate, includes a gate, drain and source with the gate position substantially perpendicular to the plane of the silicon substrate thereby burying the gate and allowing more surface area on the silicon substrate for formation of additional memory cells. | 09-27-2012 |
20120306005 | Trough channel transistor and methods for making the same - The present invention relates to transistor devices having a trough channel structure through which electrical current flows and methods for making the same. A transistor device having a semiconductor trough structure comprises a semiconductor substrate of a first conductivity type having a top surface; a semiconductor trough protruded from the top surface of the substrate along a first direction and having two top surfaces, two outer lateral surfaces, and an inner surface; a layer of isolation insulator disposed on the substrate and abutting the outer lateral surfaces of the semiconductor trough; a gate dielectric layer lining the inner surface and the top surfaces of the semiconductor trough; and a gate electrode disposed on top of the isolation insulator and extending over and filling the semiconductor trough with the gate dielectric layer interposed therebetween. The gate electrode extends along a second direction not parallel to the first direction provided in the semiconductor trough. Regions of the semiconductor trough not directly beneath the gate electrode have a second conductivity type opposite to the first conductivity type provided in the substrate. | 12-06-2012 |
20120306033 | VIALESS MEMORY STRUCTURE AND METHOD OF MANUFACTURING SAME - A method of manufacturing a magnetic memory cell, including a magnetic tunnel junction (MTJ), includes using silicon nitride layer and silicon oxide layer to form a trench for depositing copper to be employed for connecting the MTJ to other circuitry without the use of a via. | 12-06-2012 |
20130032775 | MRAM with sidewall protection and method of fabrication - BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching. | 02-07-2013 |
20130032907 | MRAM with sidewall protection and method of fabrication - BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching. | 02-07-2013 |
20130056698 | RESISTIVE MEMORY DEVICE HAVING VERTICAL TRANSISTORS AND METHOD FOR MAKING THE SAME - The present invention relates to resistive memory devices incorporating therein vertical selection transistors and methods for making the same. A resistive memory device comprises a semiconductor substrate having a first type conductivity; a plurality of vertical selection transistors formed on the semiconductor substrate in an array, each of the plurality of vertical selection transistors including a semiconductor pillar protruded from the semiconductor substrate, top region of the semiconductor pillar having a second type conductivity opposite to the first type conductivity provided in the semiconductor substrate; and a gate electrode surrounding the semiconductor pillar with a gate dielectric layer interposed therebetween, the gate electrode being lower in height than the semiconductor pillar; a plurality of contact studs disposed on top of the vertical selection transistors; a plurality of resistive memory elements disposed on top of the contact studs; a plurality of parallel word lines connecting the vertical selection transistors by way of respective gate electrodes, the parallel word lines extending along a first direction; a plurality of parallel bit lines connecting the resistive memory elements, the parallel bit lines extending along a second direction different from the first direction provided in the parallel word lines; and a plurality of parallel source lines with the second type conductivity formed in top regions of the semiconductor substrate in between rows of the semiconductor pillars, wherein the source lines and the top regions of the semiconductor pillars function as source and drain, respectively. | 03-07-2013 |
20130075840 | METHOD FOR FABRICATION OF A MAGNETIC RANDOM ACCESS MEMORY (MRAM) USING A HIGH SELECTIVITY HARD MASK - A self-aligned via of a MRAM cell that connects a memory element including a top electrode, a memory element stack having a plurality of layers, and a bottom electrode to a bit line running over array of the memory elements. The self-aligned via also serves as a hard mask for memory element etching. The hard mask material has high selectivity in the etching ambient to maintain enough remaining thickness. It is also selectively removed during dual damascene process to form a self-aligned via hole. In one embodiment, Aluminum oxide or Magnesium oxide is adapted as the hard mask. | 03-28-2013 |
20130126819 | MEMORY DEVICE HAVING VERTICAL SELECTION TRANSISTORS WITH SHARED CHANNEL STRUCTURE AND METHOD FOR MAKING THE SAME - The present invention relates to resistive memory devices incorporating therein vertical selection transistors and methods for making the same. A memory device comprises a semiconductor substrate having a first type conductivity and a plurality of parallel trenches therein; a plurality of parallel common source lines having a second type conductivity opposite to the first type conductivity formed in the trench bottoms; a plurality of parallel gate electrodes formed on the trench sidewalls with a gate dielectric layer interposed therebetween, the gate electrodes being lower in height than the trench sidewalls; and a plurality of drain regions having the second type conductivity formed in top regions of the trench sidewalls, at least two of the drain regions being formed in each of the trench sidewalls and sharing a respective common channel formed in the each of the trench sidewalls and a respective one of the source lines. | 05-23-2013 |
20130126823 | MEMORY DEVICE INCLUDING TRANSISTOR ARRAY WITH SHARED PLATE CHANNEL AND METHOD FOR MAKING THE SAME - The present invention relates to memory devices incorporating therein a novel memory cell architecture which includes an array of selection transistors sharing a common channel and method for making the same. A memory device comprises a semiconductor substrate having a first type conductivity, a plurality of drain regions and a common source region separated by a common plate channel in the substrate, and a selection gate disposed on top of the plate channel with a gate dielectric layer interposed therebetween. The plurality of drain regions and the common source region have a second type conductivity opposite to the first type provided in the substrate. | 05-23-2013 |
20130244344 | METHOD FOR MANUFACTURING HIGH DENSITY NON-VOLATILE MAGNETIC MEMORY - Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited. | 09-19-2013 |
20130267042 | MRAM Fabrication Method with Sidewall Cleaning - Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described. | 10-10-2013 |
20130337582 | MRAM ETCHING PROCESSES - Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes. | 12-19-2013 |
20130341801 | Redeposition Control in MRAM Fabrication Process - Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode. | 12-26-2013 |
20140027830 | ACCESS TRANSISTOR WITH A BURIED GATE - A magnetic memory cell is formed including a magneto tunnel junction (MTJ) and an access transistor, which is used to access the MTJ in operation. The access transistor, which is formed on a silicon substrate, includes a gate, drain and source with the gate position substantially perpendicular to the plane of the silicon substrate thereby burying the gate and allowing more surface area on the silicon substrate for formation of additional memory cells. | 01-30-2014 |
20140035069 | FIELD EFFECT TRANSISTOR HAVING A TROUGH CHANNEL - The present invention is directed to a field effect transistor having a trough channel structure. The transistor comprises a semiconductor substrate of a first conductivity type having a trough structure therein with the trough structure extending along a first direction; an insulating layer formed on top of the trough structure; a gate formed on top of the insulator layer in a second direction perpendicular to the first direction and extending over and into the trough structure with a gate dielectric layer interposed therebetween; a source and a drain of a second conductivity type opposite to the first conductivity type formed in the trough structure on opposite sides of the gate. | 02-06-2014 |
20140042567 | MTJ MRAM WITH STUD PATTERNING - Use of a multilayer etching mask that includes a stud mask and a removable spacer sleeve for MTJ etching to form a bottom electrode that is wider than the rest of the MTJ pillar is described. The first embodiment of the invention described includes a top electrode and a stud mask. In the second and third embodiments the stud mask is a conductive material and also serves as the top electrode. In embodiments after the stud mask is formed a spacer sleeve is formed around it to initially increase the masking width for a phase of etching. The spacer is removed for further etching, to create step structures that are progressively transferred down into the layers forming the MTJ pillar. In one embodiment the spacer sleeve is formed by net polymer deposition during an etching phase. | 02-13-2014 |
20140138600 | MEMORY DEVICE HAVING STITCHED ARRAYS OF 4 F MEMORY CELLS - A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts. | 05-22-2014 |
20140138609 | HIGH DENSITY RESISTIVE MEMORY HAVING A VERTICAL DUAL CHANNEL TRANSISTOR - Resistive memory cell array fabricated with unit areas able to be scaled down to 4 F | 05-22-2014 |
20140170776 | MTJ STACK AND BOTTOM ELECTRODE PATTERNING PROCESS WITH ION BEAM ETCHING USING A SINGLE MASK - Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step. | 06-19-2014 |
20140210103 | MRAM with Sidewall Protection and Method of Fabrication - BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching. In either the first or second embodiments a single layer or a dual layer etch stop layer structure can be deposited over the wafer after the sidewall protection sleeve has been formed and before the inter-layer dielectric (ILD) is deposited. | 07-31-2014 |
20150084140 | LANDING PAD IN PERIPHERAL CIRCUIT FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM) - The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings. | 03-26-2015 |
20150104882 | FABRICATION METHOD FOR HIGH-DENSITY MRAM USING THIN HARD MASK - Embodiments of the invention are described that use a thin metallic hard mask, which can be a bi-layer film, to increase the incident IBE angle for MTJ sidewall cleaning without losing the process margin for the subsequent interconnection process. The patterned metallic hard mask pads also serve as the top electrode for the MTJ cells. Using a thin metallic hard mask is possible when the hard mask material acts as a CMP stopper without substantial loss of thickness. In the first embodiment, the single layer hard mask is preferably ruthenium. In the second embodiment, the lower layer of the bi-layer hard mask is preferably ruthenium. The wafer is preferably rotated during the IBE process for uniform etching. A capping layer under the hard mask is preferably used as the etch stopper during hard mask etch process in order not to damage or etch through the upper magnetic layer. | 04-16-2015 |
Patent application number | Description | Published |
20090108198 | BROAD RIBBON BEAM ION IMPLANTER ARCHITECTURE WITH HIGH MASS-ENERGY CAPABILITY - A ribbon ion beam system, comprising an ion source configured to generate a ribbon ion beam along a first beam path, wherein the ribbon ion beam enters a mass analysis magnet having a height dimension (h | 04-30-2009 |
20090272918 | SYSTEM AND METHOD OF PERFORMING UNIFORM DOSE IMPLANTATION UNDER ADVERSE CONDITIONS - An ion implantation system and associated method includes a scanner configured to scan a pencil shaped ion beam into a ribbon shaped ion beam, and a beam bending element configured to receive the ribbon shaped ion beam having a first direction, and bend the ribbon shaped ion beam to travel in a second direction. The system further includes an end station positioned downstream of the beam bending element, wherein the end station is configured to receive the ribbon shaped ion beam traveling in the second direction, and secure a workpiece for implantation thereof. In addition, the system includes a beam current measurement system located at an exit opening of the beam bending element that is configured to measure a beam current of the ribbon shaped ion beam at the exit opening of the beam bending element. | 11-05-2009 |
20090321657 | SYSTEM AND METHOD OF CONTROLLING BROAD BEAM UNIFORMITY - An ion beam uniformity control system, wherein the uniformity control system comprising a differential pumping chamber that encloses an array of individually controlled gas jets, wherein the gas pressure of the individually controlled gas jets are powered by a controller to change the fraction of charge exchanged ions, and wherein the charge exchange reactions between the gas and ions change the fraction of the ions with original charge state of a broad ion beam, wherein the charge exchanged portion of the broad ion beam is removed utilizing an deflector that generates a magnetic field, a Faraday cup profiler for measuring the broad ion beam profile; and adjusting the individually controlled gas jets based upon feedback provided to the controller to obtain the desired broad ion beam. | 12-31-2009 |
20100038553 | SYSTEM AND METHOD OF BEAM ENERGY IDENTIFICATION FOR SINGLE WAFER ION IMPLANTATION - The present invention involves a beam energy identification system, comprising an accelerated ion beam, wherein the accelerated ion beam is scanned in a fast scan axis within a beam scanner, wherein the beam scanner is utilized to deflect the accelerated ion beam into narrow faraday cups downstream of the scanner, wherein a difference in scanner voltage or current to position the beam into the Faraday cups is utilized to calculated the energy of ion beam. | 02-18-2010 |
20100072402 | EXTRACTION ELECTRODE MANIPULATOR - An extraction electrode manipulator system, comprising an ion source, a suppression electrode and a ground electrode, wherein the two electrode are supported by coaxially arranged two water cooled support tubes. A high voltage insulator ring is located on the other end of the coaxial support tube system to act as a mechanical support of the inner tube and also as a high voltage vacuum feedthrough to prevent sputtering and coating of the insulating surface. | 03-25-2010 |
20110101213 | METHOD AND SYSTEM FOR INCREASING BEAM CURRENT ABOVE A MAXIMUM ENERGY FOR A CHARGE STATE - Methods and a system of an ion implantation system are disclosed that are capable of increasing beam current above a maximum kinetic energy of a first charge state from an ion source without changing the charge state at the ion source. Positive ions having a first positive charge state are selected into an accelerator. The positive ions of the first positive charge state are accelerated in acceleration stages and stripped to convert them to positive ions of a second charge state. A second kinetic energy level higher than the maximum kinetic energy level of the first charge state can be obtained. | 05-05-2011 |
20110215262 | Method for Improving Implant Uniformity During Photoresist Outgassing - A method and apparatus is provided for improving implant uniformity of an ion beam experiencing pressure increase along the beam line. The method comprises generating a main scan waveform that moves an ion beam at a substantially constant velocity across a workpiece. A compensation waveform (e.g., quadratic waveform), having a fixed height and waveform, is also generated and mixed with the main scan waveform (e.g., through a variable mixer) to form a beam scanning waveform. The mixture ratio may be adjusted by an instantaneous vacuum pressure signal, which can be performed at much higher speed and ease than continuously modifying scan waveform. The mixture provides a beam scanning waveform comprising a non-constant slope that changes an ion beam's velocity as it moves across a workpiece. Therefore, the resultant beam scanning waveform, with a non-constant slope, is able to account for pressure non-uniformities in dose along the fast scan direction. | 09-08-2011 |
20120025107 | Versatile Beam Glitch Detection System - A glitch duration threshold is determined based on an allowable dose uniformity, a number of passes of a workpiece through an ion beam, a translation velocity, and a beam size. A beam dropout checking routine repeatedly measures beam current during implantation. A beam dropout counter is reset each time beam current is sufficient. On a first observation of beam dropout, a counter is incremented and a position of the workpiece is recorded. On each succeeding measurement, the counter is incremented if beam dropout continues, or reset if beam is sufficient. Thus, the counter indicates a length of each dropout in a unit associated with the measurement interval. The implant routine stops only when the counter exceeds the glitch duration threshold and a repair routine is performed, comprising recalculating the glitch duration threshold based on one fewer translations of the workpiece through the beam, and performing the implant routine starting at the stored position. | 02-02-2012 |
20140065730 | IMPLANT-INDUCED DAMAGE CONTROL IN ION IMPLANTATION - An ion implantation system is provided having an ion implantation apparatus configured to provide a spot ion beam having a beam density to a workpiece, wherein the workpiece has a crystalline structure associated therewith. A scanning system iteratively scans one or more of the spot ion beam and workpiece with respect to one another along one or more axes. A controller is also provided and configured to establish a predetermined localized temperature of the workpiece as a predetermined location on the workpiece is exposed to the spot ion beam. A predetermined localized disorder of the crystalline structure of the workpiece is thereby achieved at the predetermined location, wherein the controller is configured to control one or more of the beam density of the spot ion beam and a duty cycle associated with the scanning system to establish the localized temperature of the workpiece at the predetermined location on the workpiece. | 03-06-2014 |
20150214005 | METHOD FOR ENHANCING BEAM UTILIZATION IN A SCANNED BEAM ION IMPLANTER - A dosimetry system and method are provided for increasing utilization of an ion beam, wherein one or more side Faraday cups are positioned along a path of the ion beam and configured to sense a current thereof. The one or more side Faraday cups are separated by a distance associated with a diameter of the workpiece. The ion beam reciprocally scans across the workpiece, interlacing narrow scans and wide scans, wherein narrow scans are defined by reversing direction of the scanning near an edge of the workpiece, and wide scans are defined by reversing direction of the scanning at a position associated with an outboard region of the side Faraday cups. A beam current is sensed by the side Faraday cups concurrent with scanning the beam, wherein the side Faraday cups are connected to a dosimeter only concurrent with a wide scan of the ion beam, and are disconnected concurrent with narrow scans of the ion beam. The side Faraday cups are further connected to ground concurrent with narrow scans of the ion beam. | 07-30-2015 |