Patent application number | Description | Published |
20080246159 | PLANARIZED PASSIVATION LAYER FOR SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device. | 10-09-2008 |
20090146296 | Method of forming high-k dielectric stop layer for contact hole opening - A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow. | 06-11-2009 |
20090250762 | INTEGRATED CIRCUIT SYSTEM EMPLOYING SACRIFICIAL SPACERS - An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming a second dielectric layer over the integrated circuit system; forming a first device source/drain and a second device source/drain adjacent the second spacer and through the second dielectric layer; removing the second spacer without damaging the substrate; forming a third dielectric layer over the integrated circuit system before annealing; and forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof. | 10-08-2009 |
20090250764 | STRESSED DIELECTRIC LAYER WITH STABLE STRESS - An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation region or the pre-metal dielectric layer includes a O | 10-08-2009 |
20090289284 | High shrinkage stress silicon nitride (SiN) layer for NFET improvement - A method (and semiconductor device) of forming a high shrinkage stressed silicon nitride layer for use as a contact etch stop layer (CESL) or capping layer in a stress management technique (SMT) provides increased tensile stress to a channel of an nFET device to enhance carrier mobility. A spin-on polysilazane-based dielectric material is applied to a semiconductor substrate and baked to form a film layer. The film layer is cured to remove hydrogen from the film which causes shrinkage in the film when it recrystallizes into silicon nitride. The resulting silicon nitride stressed layer introduces an increased level of tensile stress to the transistor channel region. | 11-26-2009 |
20090289309 | METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS - A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts. | 11-26-2009 |
20090302391 | STRESS LINER FOR STRESS ENGINEERING - A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies. | 12-10-2009 |
20090315121 | STABLE STRESS DIELECTRIC LAYER - An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric (PMD) layer is disposed over the substrate and the transistor. At least one of the isolation region or the PMD layer includes O | 12-24-2009 |
20090325359 | INTEGRATED CIRCUIT SYSTEM EMPLOYING A MODIFIED ISOLATION STRUCTURE - An integrated circuit system that includes: providing a substrate; forming a trench within the substrate; forming a liner on a sidewall of the trench; and forming a dielectric material at a trench bottom with a dielectric width dimension that exceeds that of a width dimension of the trench. | 12-31-2009 |
20100109155 | RELIABLE INTERCONNECT INTEGRATION - A semiconductor device includes a dielectric layer in which an upper portion is densified. An interconnection is disposed in the dielectric layer. The densified portion reduces undercut during subsequent processing, improving reliability of the interconnection. | 05-06-2010 |
20100267236 | METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS - A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts. | 10-21-2010 |
20100283448 | REFERENCE CIRCUIT WITH REDUCED CURRENT STARTUP - An apparatus is provided. The apparatus comprises a reference circuit and a startup circuit. The reference circuit is adapted to provide a startup current, while the startup circuit receives the startup current and outputs an output voltage. The startup circuit includes a current mirror, a first NMOS transistor, a second NMOS transistor, diodes, and a third NMOS transistor, and a control circuit. The first and second NMOS transistors are coupled to the current mirror at their sources and are coupled to one another and to the reference circuit at their gates. The diodes are coupled between the gate of the second NMOS transistor and the source of the second NMOS transistor, and the third NMOS transistor is coupled to the source of the second NMOS transistor at its gate (which also provides the output voltage at its source). The control circuit is then coupled to the drains of the first and second NMOS transistors. | 11-11-2010 |
20100301461 | RELIABLE INTERCONNECTION - Embodiments relate to a method for forming reliable interconnects by the use of a device layer that can serve as a barrier or an etch stop layer, among other applications. The device layer is UV resistant in that its dielectric constant and stress remain stable or relatively stable when subjected to UV curing. | 12-02-2010 |
20110266688 | PLANARIZED PASSIVATION LAYER FOR SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device. | 11-03-2011 |
20110316085 | INTEGRATED CIRCUIT INCLUDING A STRESSED DIELECTRIC LAYER WITH STABLE STRESS - An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation region or the pre-metal dielectric layer includes a O | 12-29-2011 |
20130325442 | Methods and Systems for Automated Text Correction - The present embodiments demonstrate systems and methods for automated text correction. In certain embodiments, the methods and systems may be implemented through analysis according to a single text correction model. In a particular embodiment, the single text correction model may be generated through analysis of both a corpus of learner text and a corpus of non-learner text. | 12-05-2013 |
20140163963 | Methods and Systems for Automated Text Correction - The present embodiments demonstrate systems and methods for automated text correction. In certain embodiments, the methods and systems may be implemented through analysis according to a single text correction model. In a particular embodiment, the single text correction model may be generated through analysis of both a corpus of learner text and a corpus of non-learner text. | 06-12-2014 |
20140264911 | THROUGH SILICON VIAS - A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface. | 09-18-2014 |
20150087133 | WAFER PROCESSING - Methods for forming a device are presented. A substrate having top and bottom pad stacks is provided. Each pad stack includes at least first and second pad layers. The second pad layers of the top and bottom pad stacks include an initial thickness T | 03-26-2015 |