Patent application number | Description | Published |
20120207783 | HIV VACCINE FORMULATIONS - Provided herein are HIV vaccines comprising HIV polypeptide-encoding DNA adsorbed to PLG and/or HIV proteins. Also provided are methods of using these vaccines to generate immune responses in a subject. | 08-16-2012 |
20130195898 | MICROEMULSIONS WITH ADSORBED MACROMOLECULES AND MICROPARTICLES - Microparticles with adsorbent surfaces, methods of making such microparticles, and uses thereof, are disclosed. The microparticles comprise a polymer, such as a poly(α-hydroxy acid), a polyhydroxy butyric acid, a polycaprolactone, a polyorthoester, a polyanhydride, and the like, and are formed using cationic, anionic, or nonionic detergents. The surface of the microparticles efficiently adsorb biologically active macromolecules, such as DNA, polypeptides, antigens, and adjuvants. Also provided are compositions of an oil droplet emulsion having a metabolizable oil and an emulsifying agent. Immunogenic compositions having an immunostimulating amount of an antigenic substance, and an immunostimulating amount of an adjuvant composition are also provided. Methods of stimulating an immune response, methods of immunizing a host animal against a viral, bacterial, or parasitic infection, and methods of increasing a Th1 immune response in a host animal by administering to the animal an immunogenic composition of the microparticles, and/or microemulsions of the invention, are also provided. | 08-01-2013 |
20130195923 | MICROEMULSIONS WITH ADSORBED MACROMOLECULES AND MICROPARTICLES - Microparticles with adsorbent surfaces, methods of making such microparticles, and uses thereof, are disclosed. The microparticles comprise a polymer, such as a poly(α-hydroxy acid), a polyhydroxy butyric acid, a polycaprolactone, a polyorthoester, a polyanhydride, and the like, and are formed using cationic, anionic, or nonionic detergents. The surface of the microparticles efficiently adsorb biologically active macromolecules, such as DNA, polypeptides, antigens, and adjuvants. Also provided are compositions of an oil droplet emulsion having a metabolizable oil and an emulsifying agent. Immunogenic compositions having an immunostimulating amount of an antigenic substance, and an immunostimulating amount of an adjuvant composition are also provided. Methods of stimulating an immune response, methods of immunizing a host animal against a viral, bacterial, or parasitic infection, and methods of increasing a Th1 immune response in a host animal by administering to the animal an immunogenic composition of the microparticles, and/or microemulsions of the invention, are also provided. | 08-01-2013 |
20130196352 | BACTERICIDAL ANTIBODY ASSAYS TO ASSESS IMMUNOGENICITY AND POTENCY OF MENINGOCOCCAL CAPSULAR SACCHARIDE VACCINES - The disclosure provides compositions, methods and kits for assessing immunogenicity, potency, or both, of meningococcal capsular saccharide vaccines. The assessment is based upon measurement of binding of a bactericidal antibody to a capsular saccharide component in the vaccine. | 08-01-2013 |
Patent application number | Description | Published |
20100150290 | Clock-Data Recovery ("CDR") Circuit, Apparatus And Method For Variable Frequency Data - A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the clock circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time. | 06-17-2010 |
20110286280 | Pulse Control For NonVolatile Memory - This disclosure provides a nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage (selected in response to the bitline) is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about (20) nanoseconds, while a “rest period” between pulses typically is chosen to be on the order of about a hundred nanoseconds or greater (e.g., one microsecond). Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of (50) nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); if desired, segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust. | 11-24-2011 |
20140247656 | Pulse Control For NonVolatile Memory - A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust. | 09-04-2014 |
20160027515 | Pulse Control For Non-Volatile Memory - A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust. | 01-28-2016 |
Patent application number | Description | Published |
20090248971 | System and Dynamic Random Access Memory Device Having a Receiver - A dynamic random access memory device (DRAM) receiver circuit includes an input to receive a data signal, and also includes decision circuitry to make a decision about the received data signal based on a present sampled data signal and a coefficient value corresponding to at least one of a previously sampled data signals. | 10-01-2009 |
20090327789 | Memory System with Calibrated Data Communication - A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit. | 12-31-2009 |
20100134153 | Low Latency Multi-Level Communication Interface - A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver. | 06-03-2010 |
20100230807 | Method and Apparatus to Repair Defects in Nonvolatile Semiconductor Memory Devices - A method of repairing a nonvolatile semiconductor memory device to eliminate defects includes monitoring a memory endurance indicator for a nonvolatile semiconductor memory device contained in a semiconductor package. It is determined whether that the memory endurance indicator exceeds a predefined limit. Finally, in response to determining that the memory endurance indicator exceeds the predefined limit, the device is annealed. | 09-16-2010 |
20100296566 | METHOD AND APPARATUS FOR DETERMINING A CALIBRATION SIGNAL - Embodiments of a system for determining and optimizing the performance a signaling system are described. During operation, the system captures or measures a single-bit response (SBR) for the signaling system. Next, the system constructs an idealized inter-symbol-interference-free (ISI-free) SBR for the signaling system which is substantially free of inter-symbol-interference (ISI). The system then calculates an ISI-residual from the captured SBR and the idealized ISI-free SBR. Next, the system constructs a calibration bit pattern for the signaling system that is based substantially on the ISI-residual. Finally, the system uses the calibration bit pattern to calibrate, optimize and determine an aspect of the performance of the signaling system. | 11-25-2010 |
20110140741 | INTEGRATING RECEIVER WITH PRECHARGE CIRCUITRY - A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver. | 06-16-2011 |
20110289245 | Memory Controller and Method Utilizing Equalization Co-Efficient Setting - A chip includes a transmitter circuit and a register provided to store a value representative of an equalization co-efficient setting. The transmitter circuit includes an output driver configured to adjust an output data signal based at least in part on the equalization co-efficient setting. | 11-24-2011 |
20110299317 | INTEGRATED CIRCUIT HEATING TO EFFECT IN-SITU ANNEALING - In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device. | 12-08-2011 |
20110305271 | High-Speed Signaling Systems With Adaptable Pre-Emphasis and Equalization - A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate. | 12-15-2011 |
20110310949 | High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization - A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate. | 12-22-2011 |
20120044984 | High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization - A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate. | 02-23-2012 |
20120204054 | Memory System with Calibrated Data Communication - An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values. | 08-09-2012 |
20120207196 | High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization - A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate. | 08-16-2012 |
20120236668 | MEMORY MODULE WITH DISCRETE HEATING ELEMENT - A memory module includes multiple memory devices mounted to a substrate and one or more discrete heating elements disposed in thermal contact with the memory devices. Each of the memory devices includes charge-storing memory cells subject to operation-induced defects that degrade ability of the memory cells to store data. The discrete heating elements, or single discrete heating element, heats the memory devices to a temperature that anneals the defects. | 09-20-2012 |
20120268199 | Chip Having Register to Store Value that Represents Adjustment to Reference Voltage - A chip includes a receiver circuit that uses a reference voltage to receive a data signal such that a logic level of the received data signal is determined using the reference voltage, and a register to store a value that represents an adjustment to the reference voltage. | 10-25-2012 |
20130010855 | Multiphase receiver with equalization circuitry - An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal. | 01-10-2013 |
20130227214 | Chip Having Register to Store Value that Represents Adjustment to Reference Voltage - An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting. | 08-29-2013 |
20130322506 | HIGH-SPEED SIGNALING SYSTEMS WITH ADAPTABLE PRE-EMPHASIS AND EQUALIZATION - A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate. | 12-05-2013 |
20140286389 | Multiphase Receiver with Equalization Circuitry - An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level. | 09-25-2014 |
20150212954 | CHIP HAVING PORT TO RECEIVE VALUE THAT REPRESENTS ADJUSTMENT TO TRANSMISSION PARAMETER - An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting. | 07-30-2015 |
20150212968 | CHIP HAVING PORT TO RECEIVE VALUE THAT REPRESENTS ADJUSTMENT TO OUTPUT DRIVER PARAMETER - An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting. | 07-30-2015 |
20150213852 | CHIP HAVING REGISTER TO STORE VALUE THAT REPRESENTS ADJUSTMENT TO OUTPUT DRIVE STRENGTH - An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting. | 07-30-2015 |
20150220270 | CHIP STORING A VALUE THAT REPRESENTS ADJUSTMENT TO OUTPUT DRIVE STRENGTH - An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting. | 08-06-2015 |
20160026599 | FLASH CONTROLLER TO PROVIDE A VALUE THAT REPRESENTS A PARAMETER TO A FLASH MEMORY - An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting. | 01-28-2016 |