Patent application number | Description | Published |
20090319977 | Interconnect-Driven Physical Synthesis Using Persistent Virtual Routing - A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one embodiment, the nets can be re-ranked after synthesis. Finally, these routes can be preserved across the subsequent global routing of the remaining nets. | 12-24-2009 |
20110061038 | Pre-Route And Post-Route Net Correlation With Defined Patterns - A method of improving pre-route and post-route correlation can include performing an initial placement, virtual routing, and lower-effort actual routing for the design. The results of the virtual routing and lower-effort actual routing can be compared to identify nets having miscorrelation. Based on the nets having at least a predetermined miscorrelation, one or more patterns can be defined. At this point, net routing constraints and/or scaling factors can be assigned to nets matching the defined patterns. These net routing constraints and scaling factors can be applied to the nets of the design that match the patterns. Optimized placement and a higher-effort actual routing of the design can be performed using the nets with the applied net routing constraints and scaling factors. An optimized, routed design can be generated as output. | 03-10-2011 |
20130346936 | Method and Apparatus to Generate Pattern-Based Estimated RC Data with Analysis of Route Information - A method and apparatus for improving physical synthesis of a circuit design is described. In one exemplary embodiment, post-route information of nets in the circuit design is analyzed. The post-route information includes, for each of the nets, a predicted route property, a post-route property, and a set of physical and/or timing attributes for that net. For each of the attributes, a set of attribute ranges is derived for the corresponding attribute to bin the nets into a Gaussian distribution for that attribute. Net routing constraints are generated for the circuit design based on the attribute ranges derived. The net routing constraints are applied to one or more of the nets during subsequent placement-based optimizations of the circuit design. | 12-26-2013 |
20130346937 | METHOD AND APPARATUS TO GENERATE PATTERN-BASED ESTIMATED RC DATA WITH ANALYSIS OF ROUTE INFORMATION - A method and apparatus for improving physical synthesis of a circuit design is described. In one exemplary embodiment, preliminary routing information of nets in the circuit design is analyzed. The preliminary routing information includes track assignment information. Timing-critical nets are identified based on statistical distribution of the preliminary routing information of the nets. The identified timing-critical nets are assigned to a set of routing layers and removed from future net pattern matching. The remaining nets are clustered into multiple net patterns based on their physical attributes. The scaling factor for each net pattern is updated based on the scaling factor standard deviation and net length of the net pattern. Nets that are outside multiple standard deviations of a net pattern are assigned to routing layers. The scaling factors of the net patterns and the layer assignments are applied to the next phase of placement-based optimizations. | 12-26-2013 |
Patent application number | Description | Published |
20080207138 | Phase Detector - A phase detector includes a plurality of phase detectors located in a phase correction loop, each phase detector configured to receive as input a radio frequency (RF) input signal and an RF reference signal, each of the plurality of phase detectors also configured to provide a signal representing a different phase offset based on the phase difference between the RE input signal and the RF reference signal; and a switch configured to receive an output of each of the plurality of phase detectors and configured to select the output representing the phase offset, that is closest to a phase of an output of an amplifier. | 08-28-2008 |
20100039153 | DIVIDE-BY-THREE QUADRATURE FREQUENCY DIVIDER - A local oscillator includes a programmable frequency divider coupled to the output of a VCO. The frequency divider can be set to frequency divide by three. Regardless of the divisor, the frequency divider outputs quadrature signals (I, Q) that differ from each other in phase by ninety degrees. To divide by three, the frequency divider includes a divide-by-three frequency divider. The divide-by-three frequency divider includes a divide-by-three circuit, a delay circuit, and a feedback circuit. The divide-by-three circuit frequency divides a signal from the VCO and generates therefrom three signals C, A′ and B that differ from each other in phase by one hundred twenty degrees. The delay circuit delays signal A′ to generate a delayed version A of the signal A′. The feedback circuit controls the delay circuit such that the delayed version A (I) is ninety degrees out of phase with respect to the signal C (Q). | 02-18-2010 |
20100240323 | FREQUENCY DIVIDER WITH SYNCHRONIZED OUTPUTS - A synchronized frequency divider that can divide a clock signal in frequency and provide differential output signals having good signal characteristics is described. In one exemplary design, the synchronized frequency divider includes a single-ended frequency divider and a synchronization circuit. The single-ended frequency divider divides the clock signal in frequency and provides first and second single-ended signals, which may be complementary signals having timing skew. The synchronization circuit resamples the first and second single-ended signals based on the clock signal and provides differential output signals having reduced timing skew. In one exemplary design, the synchronization circuit includes first and second switches and first and second inverters. The first switch and the first inverter form a first sample-and-hold circuit or a first latch that resamples the first single-ended signal. The second switch and the second inverter form a second sample-and-hold circuit or a second latch that resamples the second single-ended signal. | 09-23-2010 |
20110012647 | FREQUENCY DIVIDER WITH A CONFIGURABLE DIVIDING RATIO - A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clocked switches inside the frequency divider are operated to select one of multiple dividing ratios. An output signal is output with a second frequency that is the first frequency divided by the selected dividing ratio. | 01-20-2011 |
20110012648 | SYSTEMS AND METHODS FOR REDUCING AVERAGE CURRENT CONSUMPTION IN A LOCAL OSCILLATOR PATH - A method for reducing average current consumption in a local oscillator (LO) path is disclosed. An LO signal is received at a master frequency divider and a slave frequency divider. Output from the master frequency divider is mixed with an input signal to produce a first mixed output. Output from the slave frequency divider is mixed with the input signal to produce a second mixed output. The second mixed output is forced to be in phase with the first mixed output. | 01-20-2011 |
20110200161 | DIFFERENTIAL QUADRATURE DIVIDE-BY-THREE CIRCUIT WITH DUAL FEEDBACK PATH - A divide-by-three circuit includes a chain of three dynamic flip-flops and a feedback circuit of combinatorial logic. The divide-by-three circuit receives a clock signal that synchronously clocks each dynamic flip-flop. The feedback circuit supplies a feedback signal onto the first dynamic-flop of the chain. In a first mode, a signal from a slave stage of the first flip-flop and a signal from a slave stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. In a second mode, a signal from a master stage of the first flip-flop and a signal from a master stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. By proper selection of the mode, the frequency range of the overall divider is extended. Combinatorial logic converts thirty-three percent duty cycle signals from the flip-flop chain into fifty percent duty cycle quadrature signals. | 08-18-2011 |
20120001666 | PARALLEL PATH FREQUENCY DIVIDER CIRCUIT - A parallel path frequency divider (PPFD) includes a low power frequency divider and a high speed latch. A first portion of an oscillating input signal present on an input node of the PPFD is communicated to the divider and a second portion is communicated to the latch. The divider generates a frequency divided enable signal that is communicated to the latch. The latch generates a divided down output signal based on the oscillating input signal and the enable signal. The output signal is insensitive to phase noise present on the enable signal as long as the phase noise on the enable signal is less than one-half of the period of oscillation of the oscillating input signal. Because the noise generated by the low power frequency divider is not propagated to the output signal generated by the PPFD, the PPFD generates low noise, frequency divided signals with relatively low power consumption. | 01-05-2012 |
Patent application number | Description | Published |
20090094258 | OFF-LOADING STAR JOIN OPERATIONS TO A STORAGE SERVER - A method, storage server, and computer readable medium for off-loading star-join operations from a host information processing system to a storage server. At least a first and second set of keys from a first and second dimension table, respectively are received from a host system. Each of the first and second set of keys is associated with at least one fact table. A set of locations associated with a set of foreign key indexes are received from the host system. A set of fact table indexes are traversed. At least a first set of Row Identifiers (“RIDs”) associated with the first set of keys and at least a second set of RIDs associated with the second set of keys are identified. An operation is performed on the first and second sets of RIDs to identify an intersecting set of RIDs. The intersecting set of RIDs are then stored. | 04-09-2009 |
20090249023 | APPLYING VARIOUS HASH METHODS USED IN CONJUNCTION WITH A QUERY WITH A GROUP BY CLAUSE - A novel method is described for applying various hash methods used in conjunction with a query with a Group By clause. A plurality of drawers are identified, wherein each of the drawers is made up of a collection of cells from a single partition of a Group By column and each of the drawers being defined for a specific query. A separate hash table is independently computed for each of the drawers and a hashing scheme (picked from among a plurality of hashing schemes) is independently applied for each of the drawers. | 10-01-2009 |
20090292714 | ADAPTIVE LAZY MERGING - A query processing method intersects two or more unsorted lists based on a conjunction of predicates. Each list comprises a union of multiple sorted segments. The method performs lazy segment merging and an adaptive n-ary intersecting process. The lazy segment merging comprises starting with each list being a union of completely unmerged segments, such that lookups into a given list involve separate lookups into each segment of the given list. The method intersects the lists according to the predicates while performing the lazy segment merging, such that the lazy segment merging reads in only those portions of each segment that are needed for the intersecting. As the intersecting proceeds and the lookups are performed, the intersecting selectively merges the segments together, based on a cost-benefit analysis of the cost of merging compared to the benefit produced by reducing a number of lookups. | 11-26-2009 |
20100049730 | EFFICIENT PREDICATE EVALUATION VIA IN-LIST - A predicate over a single column of a table is converted into at least one IN-list, wherein the IN-list is generated for a set of tuples of the column, and the generation is done over a data structure representing a set of distinct values of the column where the predicate applies and having a smaller cardinality than the table. The generated IN-list is evaluated over the set of tuples and the results of the evaluation are outputted as an evaluation of the predicate. | 02-25-2010 |
20110040744 | SYSTEM, METHOD, AND APPARATUS FOR SCAN-SHARING FOR BUSINESS INTELLIGENCE QUERIES IN AN IN-MEMORY DATABASE - A computer-implemented method for scan sharing across multiple cores in a business intelligence (BI) query. The method includes receiving a plurality of BI queries, storing a block of data in a first cache, scanning the block of data in the first cache against a first batch of queries on a first processor core, and scanning the block of data against a second batch of queries on a second processor core. The first cache is associated with a first processor core. The block of data includes a subset of data stored in an in-memory database (IMDB). The first batch of queries includes two or more of the BI queries. The second batch of queries includes one or more of the BI queries that are not included in the first batch of queries. | 02-17-2011 |
20120078980 | COMPACT AGGREGATION WORKING AREAS FOR EFFICIENT GROUPING AND AGGREGATION USING MULTI-CORE CPUS - A system is described for creating compact aggregation working areas for efficient grouping and aggregation using multi-core CPUs. The system implements operations including computing a running aggregate for a group within a business intelligence (BI) query, and identifying a location to store running aggregate information within an aggregation working area of a cache. The aggregation working area includes first and second data structures. The first data structure stores running aggregate information that is associated with a group that is accessed frequently relative to a threshold. The second data structure stores running aggregate information that is associated with a group that is accessed infrequently relative to the threshold. The operations also include storing the running aggregate information in either the first or second data structure of the aggregation working area based on a characterization of the group as a frequently or infrequently accessed group. | 03-29-2012 |
20130138923 | MULTITHREADED DATA MERGING FOR MULTI-CORE PROCESSING UNIT - Described herein are methods, systems, apparatuses and products for multithreaded data merging for multi-core central and graphical processing units. An aspect provides for executing a plurality of threads on at least one central processing unit comprising a plurality of cores, each thread comprising an input data set (IDS) and being executed on one of the plurality of cores; initializing at least one local data set (LDS) comprising a size and a threshold; inserting IDS data elements into the at least one LDS such that each inserted IDS data element increases the size of the at least one LDS; and merging the at least one LDS into a global data set (GDS) responsive to the size of the at least one LDS being greater than the threshold. Other aspects are disclosed herein. | 05-30-2013 |
20130325900 | INTRA-BLOCK PARTITIONING FOR DATABASE MANAGEMENT - A method for storing database information includes storing a table having data values in a column major order. The data values are stored in a list of blocks. The method also includes assigning a tuple sequence number (TSN) to each data value in each column of the table according to a sequence order in the table. The data values that correspond to each other across a plurality of columns of the table have equivalent TSNs. The method also includes assigning each data value to a partition based on a representation of the data value. The method also includes assigning a tuple map value to each data value. The tuple map value identifies the partition in which each data value is located. | 12-05-2013 |
20130325901 | INTRA-BLOCK PARTITIONING FOR DATABASE MANAGEMENT - A method for storing database information, including: storing a table having data values in a column major order, wherein the data values are stored in a list of blocks, assigning a tuple sequence number (TSN) to each data value in each column of the table according to a sequence order in the table, wherein data values that correspond to each other across a plurality of columns of the table have equivalent TSNs; assigning each data value to a partition based on a representation of the data value; and assigning a tuple map value to each data value, wherein the tuple map value identifies the partition in which each data value is located. | 12-05-2013 |
20140006379 | EFFICIENT PARTITIONED JOINS IN A DATABASE WITH COLUMN-MAJOR LAYOUT | 01-02-2014 |
20140006380 | EFFICIENT PARTITIONED JOINS IN A DATABASE WITH COLUMN-MAJOR LAYOUT | 01-02-2014 |
20140006381 | PREDICATE PUSHDOWN WITH LATE MATERIALIZATION IN DATABASE QUERY PROCESSING | 01-02-2014 |
20140006382 | PREDICATE PUSHDOWN WITH LATE MATERIALIZATION IN DATABASE QUERY PROCESSING | 01-02-2014 |
20140032569 | SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR REDUCING HASH TABLE WORKING-SET SIZE FOR IMPROVED LATENCY AND SCALABILITY IN A PROCESSING SYSTEM - System, method and computer program products for storing data by computing a plurality of hash functions of data values in a data item, and determining a corresponding memory location for one of the plurality of hash functions of data values in the data item. Each memory location is of a cacheline size wherein a data item is stored in a memory location. Each memory location can store a plurality of data items. A key portion of all data items is contiguously stored within the memory location, and a payload portion is contiguously stored within the memory location. Payload portions are packed as bit-aligned in a fixed-sized memory location, comprising a bucket in a bucketized hash table, each bucket sized to store multiple key portions and payload portions that are packed as bit-aligned in a fixed-sized bucket. Corresponding key portions are stored as compressed keys in said fixed-sized bucket. | 01-30-2014 |
20140074818 | MULTIPLICATION-BASED METHOD FOR STITCHING RESULTS OF PREDICATE EVALUATION IN COLUMN STORES - A system joins predicate evaluated column bitmaps having varying lengths. The system includes a column unifier for querying column values with a predicate and generating an indicator bit for each of the column values that is then joined with the respective column value. The system also includes a bitmap generator for creating a column-major linear bitmap from the column values and indicator bits. The column unifier also determines an offset between adjacent indicator bits. The system also includes a converter for multiplying the column-major linear bitmap with a multiplier to shift the indicator bits into consecutive positions in the linear bitmap. | 03-13-2014 |
20140372389 | Data Encoding and Processing Columnar Data - Aspects of the invention are provided for accessing a plurality of data elements. A page of column data is stored in a format that includes compressed and/or non-compressed elements, with the format including a plurality of arrays and a vector. Each of the arrays stores elements with common characteristics, with the vector functioning as a mapping to the stored data elements. The vector is leveraged to identify an array and determine an offset to support access to one or more of the data elements. | 12-18-2014 |
20150261751 | SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR PROBING A HASH TABLE FOR IMPROVED LATENCY AND SCALABILITY IN A PROCESSING SYSTEM - System, method and computer program products for probing a hash table by receiving a compressed input key, computing a hash value for the compressed input key and probing one or more buckets in a hash table for a match. Each bucket includes multiple chunks. For a bucket in the hash table, chunks are searched in that bucket by comparing in parallel the hash value with multiple slots in each chunk, such that if a value in a chunk equals the hash value of the compressed input key, then a match is declared and a vector is returned with a significant bit of a matching slot in the bucket set to a value. If a value stored in a chunk corresponds to an empty slot, then a mismatch is declared, and the vector is returned as the result with the significant bit of a matching empty slot set to the value. | 09-17-2015 |
Patent application number | Description | Published |
20110118834 | FLUIDIC INTRAOCULAR LENS SYSTEMS AND METHODS - The present invention relates to a fluidic intraocular lens inserted into a capsular bag of an eye to replace a crystalline lens. The fluidic intraocular lens may be shaped by elastic membranes bonded to a support ring. The space inside the device may be filled with optically transparent fluid or gel having an index of refraction greater than the index of vitreous humor. The device may be such designed so that the focusing power of the lens can be changed by the deformation of the capsular bag, which may be subsequently controlled by a ciliary muscle. | 05-19-2011 |
20130285477 | WIRELESS POWER MECHANISMS FOR LAB-ON-A-CHIP DEVICES - Methods, devices and systems are provided for wirelessly powering and controlling a lab-on-a-chip device. Direct current (DC) and alternating current (AC) signals can be produced at the lab-on-a-chip device in a wireless manner. In some configurations, integrated RF components and optoelectronic components of the lab-on-a-chip device are used to collaboratively produce the DC and AC signals. In other configurations only optoelectronic components on the lab-on-a-chip system can produce the DC and/or AC signals in response to incident light. By modulating the incident light, AC signals of various frequencies and waveforms can be generated. The DC and AC signals can be used by additional integrated electronic circuits and by a microfluidic chip lactated on the lab-on-a-chip device to control the behavior of the bioparticles in the microfluidic device. | 10-31-2013 |
20140061049 | MICROFLUIDICS WITH WIRELESSLY POWERED ELECTRONIC CIRCUITS - Techniques, devices and systems are described for incorporating a printed circuit with a microfluidic device and wirelessly powering the microfluidic device. In one aspect, a microfluidic device includes a substrate with a fluidic channel to provide a path for a fluid with particles. The fluidic channel includes fluid inlet and outlet. A pair of electrodes near the inlet and the outlet guides the particles toward a center of the fluidic channel using negative-dielectrophoresis (DEP) effect in response to an alternating current (AC) frequency voltage received at the pairs of electrodes. Additional pairs of electrodes are disposed along a border of the fluidic channel between the pairs of electrodes near the inlet and the outlet of the fluidic channel to isolate a subpopulation of the particles using positive and negative DEP effects in response to AC voltages of different frequencies received at different ones of the additional pairs of electrodes. | 03-06-2014 |
20150361483 | LABEL FREE MOLECULAR DETECTION METHODS, SYSTEMS AND DEVICES - Methods, systems, and devices are disclosed for capturing, concentrating, isolating, and detecting molecules. In one aspect, a molecular probe device includes a molecular probe having a complimentary base pair region initially zipped and structured to include a binding agent to chemically attach the molecular probe to an outer surface of a magnetic bead, and a binding molecule to chemically attach the molecular probe to a substrate of a microfluidic device, in which the complimentary base pair region is configured to hybridize to a complementary nucleic acid sequence of a DNA or RNA molecule. | 12-17-2015 |
20150368635 | MICROFLUIDIC DEVICES TO EXTRACT, CONCENTRATE AND ISOLATE MOLECULES - Methods, systems, and devices are disclosed for capturing, concentrating, and isolating molecules in a fluid. In one aspect, a device includes a substrate formed of a material that is electrically insulating, a microfluidic channel made of an electrically insulating material formed on the substrate to carry a biofluid containing molecules including nucleic acids, an array of electrodes formed on the surface along a parallel direction of the microfluidic channel constituting a capture region, in which the array of electrodes are operable to produce an electric field across the microfluidic channel that creates an electrostatic attractive force on the nucleic acids to immobilize them in the capture region, and a chamber formed on the substrate of the electrically insulating material and connected to the microfluidic channel, the chamber configured to have a volume less than that of the microfluidic channel, in which, when the nucleic acids are released from immobilization in the capture region, the released nucleic acids are collected in the chamber. | 12-24-2015 |