Patent application number | Description | Published |
20090003060 | High density NOR flash array architecture - In one embodiment of the invention, a memory includes wordline jogs and adjacent spacers. Spacers from different wordlines may contact one another on either side of a drain contact and consequently isolate and self-align the contact in the horizontal and vertical directions. | 01-01-2009 |
20110080792 | PARALLEL BITLINE NONVOLATILE MEMORY EMPLOYING CHANNEL-BASED PROCESSING TECHNOLOGY - Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories. | 04-07-2011 |
20110082694 | REAL-TIME DATA PATTERN ANALYSIS SYSTEM AND METHOD OF OPERATION THEREOF - A method for real-time data-pattern analysis. The method includes receiving and queuing at least one data-pattern analysis request by a data-pattern analysis unit controller. At least one data stream portion is also received and stored by the data-pattern analysis unit controller, each data stream portion corresponding to a received data-pattern analysis request. Next, a received data-pattern analysis request is selected by the data-pattern analysis unit controller along with a corresponding data stream portion. A data-pattern analysis is performed based on the selected data-pattern analysis request and the corresponding data stream portion, wherein the data-pattern analysis is performed by one of a plurality of data-pattern analysis units. | 04-07-2011 |
20110149630 | HIGH READ SPEED ELECTRONIC MEMORY WITH SERIAL ARRAY TRANSISTORS - Providing a serial array semiconductor architecture achieving fast program, erase and read times is disclosed herein. By way of example, a memory architecture can comprise a serial array of semiconductors coupled to a metal bitline of an electronic memory device at one end of the array, and a gate of a pass transistor at an opposite end of the array. Furthermore, a second metal bitline is coupled to a drain of the pass transistor. A sensing circuit that measures current or voltage at the second metal bitline, which is modulated by a gate potential of the pass transistor, can determine a state of transistors of the serial array. Because of low capacitance of the pass transistor, the serial array can charge or discharge the gate of the pass transistor quickly, resulting in read times that are significantly reduced as compared with conventional serial semiconductor array devices. | 06-23-2011 |
20110156122 | High Density NOR Flash Array Architecture - In one embodiment of the invention, a memory includes wordline jogs and adjacent spacers. Spacers from different wordlines may contact one another on either side of a drain contact and consequently isolate and self-align the contact in the horizontal and vertical directions. | 06-30-2011 |
20110317466 | HIGH READ SPEED MEMORY WITH GATE ISOLATION - Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture. | 12-29-2011 |
20120327717 | HIGH READ SPEED MEMORY WITH GATE ISOLATION - Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture. | 12-27-2012 |
20130158996 | Acoustic Processing Unit - Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. The apparatus can include a senone scoring unit (SSU) control module, a distance calculator, and an addition module. The SSU control module can be configured to receive a feature vector. The distance calculator can be configured to receive a plurality of Gaussian probability distributions via a data bus having a width of at least one Gaussian probability distribution and the feature vector from the SSU control module. The distance calculator can include a plurality of arithmetic logic units to calculate a plurality of dimension distance scores and an accumulator to sum the dimension distance scores to generate a Gaussian distance score. Further, the addition module is configured to sum a plurality of Gaussian distance scores to generate a senone score. | 06-20-2013 |
20130159371 | Arithmetic Logic Unit Architecture - Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, an arithmetic logic unit for computing a one-dimensional score between a feature vector and a Gaussian probability distribution vector is provided. The arithmetic logic unit includes a computational logic unit configured to compute a first value based on a mean value and a variance value associated with a dimension of the Gaussian probability distribution vector and a dimension of a feature vector, a look up table module configured to output a second value based on the variance value, and a combination module configured to combine the first value and the second value to generate the one-dimensional score. | 06-20-2013 |
20140129218 | Recognition of Speech With Different Accents - Computer-based speech recognition can be improved by recognizing words with an accurate accent model. In order to provide a large number of possible accents, while providing real-time speech recognition, a language tree data structure of possible accents is provided in one embodiment such that a computerized speech recognition system can benefit from choosing among accent categories when searching for an appropriate accent model for speech recognition. | 05-08-2014 |
20140146606 | PARALLEL BITLINE NONVOLATILE MEMORY EMPLOYING CHANNEL-BASED PROCESSING TECHNOLOGY - Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories. | 05-29-2014 |
20140304205 | COMBINING OF RESULTS FROM MULTIPLE DECODERS - Embodiments include a method, apparatus, and a computer program product for combining results from multiple decoders. For example, the method can include generating a network of paths based on one or more outputs associated with each of the multiple decoders. The network of paths can be scored to find an initial path with the highest path score based on scores associated with the one or more outputs. A weighting factor can be calculated for each of the multiple decoders based on a number of outputs from each of the multiple decoders included in the initial path with the highest path score. Further, the network of paths can be re-scored to find a new path with the highest path score based on the scores associated with the one or more outputs and the weighting factor for each of the multiple decoders. | 10-09-2014 |
Patent application number | Description | Published |
20090242956 | TUNNEL DIELECTRICS FOR SEMICONDUCTOR DEVICES - Tunnel dielectrics for semiconductor devices are generally described. In one example, an apparatus includes a semiconductor substrate, a first tunnel dielectric having a first bandgap coupled to the semiconductor substrate, a second tunnel dielectric having a second bandgap coupled to the first tunnel dielectric, and a third tunnel dielectric having a third bandgap coupled to the second tunnel dielectric wherein the second bandgap is relatively smaller than the first bandgap and the third bandgap. | 10-01-2009 |
20110208519 | REAL-TIME DATA PATTERN ANALYSIS SYSTEM AND METHOD OF OPERATION THEREOF - A method of operation of a real-time data-pattern analysis system includes: providing a memory module, a computational unit, and an integrated data transfer module arranged within an integrated circuit die; storing a data pattern within the memory module; transferring the data pattern from the memory module to the computational unit using the integrated data transfer module; and comparing processed data to the data pattern using the computational unit. | 08-25-2011 |
20140038378 | APPARATUS AND METHOD FOR A METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SOURCE SIDE PUNCH-THROUGH PROTECTION IMPLANT - A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the semiconductor substrate. The protection implant comprises a second p-type doping concentration, and is formed in the semiconductor substrate under the source region and surrounds the source region in order to protect the source region from the depletion region corresponding to the drain region. | 02-06-2014 |
20140180690 | Hybrid Hashing Scheme for Active HMMS - Embodiments of the present invention include a data storage device and a method for storing data in a hash table. The data storage device can include a first memory device, a second memory device, and a processing device. The first memory device is configured to store one or more data elements. The second memory device is configured to store one or more status bits at one or more respective table indices. In addition, each of the table indices is mapped to a corresponding table index in the first memory device. The processing device is configured to calculate one or more hash values based on the one or more data elements. | 06-26-2014 |
20140180694 | Phoneme Score Accelerator - Embodiments of the present invention include an acoustic processing device and a method for traversing a Hidden Markov Model (HMM). The acoustic processing device can include a senone scoring unit (SSU), a memory device, a HMM module, and an interface module. The SSU is configured to receive feature vectors from an external computing device and to calculate senones. The memory device is configured to store the senone scores and HMM information, where the HMM information includes HMM IDs and HMM state scores. The HMM module is configured to traverse the HMM based on the senone scores and the HMM information. Further, the interface module is configured to transfer one or more HMM scoring requests from the external computing device to the HMM module and to transfer the HMM state scores to the external computing device. | 06-26-2014 |