Patent application number | Description | Published |
20080288950 | Concurrent Management of Adaptive Programs - A method for concurrent management of adaptive programs is disclosed wherein changes in a set of modifiable references are initially identified. A list of uses of the changed references is next computed using records made in structures of the references. The list is next inserted into an elimination queue. Comparison is next made of each of the uses to the other uses to determine independence or dependence thereon. Determined dependent uses are eliminated and the preceding steps are repeated for all determined independent uses until all dependencies have been eliminated. | 11-20-2008 |
20090172294 | Method and apparatus for supporting scalable coherence on many-core products through restricted exposure - In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed. | 07-02-2009 |
20110238926 | Method And Apparatus For Supporting Scalable Coherence On Many-Core Products Through Restricted Exposure - In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed. | 09-29-2011 |
Patent application number | Description | Published |
20130136195 | SYSTEM AND METHOD OF DATA COMMUNICATIONS BETWEEN ELECTRONIC DEVICES - A system and method of data communications between a first device and a second device is disclosed. The method includes generating a first clock signal at the first device and generating a second clock signal having a phase offset from the first clock signal. The clock signals are transmitted from the first device to the second device. The method further includes regulating transmission of a read strobe signal sent from the second device to the first device utilizing the first clock signal. The method also includes regulating transmission of a data transfer signal sent from the second device to the first device utilizing the second clock signal. | 05-30-2013 |
20130159584 | DATA BUS INVERSION CODING - Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY. | 06-20-2013 |
20130159587 | Interconnect Redundancy for Multi-Interconnect Device - A multi-interconnect integrated circuit device includes an input/output (I/O) circuit for conveying a plurality of interleaved data channel groups by configuring the I/O circuit to convey a first data channel group over a default fixed interconnect signal paths if there are no connection failures in the default fixed interconnect signal paths, and to convey the first data channel group over a second plurality of default fixed interconnect signal paths if there is at least one connection failure in the first plurality of default fixed interconnect signal paths, where the second plurality of default fixed interconnect signal paths includes a redundant fixed interconnect signal path for replacing a failed interconnect signal path from the first plurality of default fixed interconnect signal paths. | 06-20-2013 |
20130159818 | Unified Data Masking, Data Poisoning, and Data Bus Inversion Signaling - Provided herein is a method and system for providing and analyzing unified data signaling that includes setting, or analyzing a state of a single indicator signal, generating or analyzing a data pattern of a plurality of data bits, and signal, or determine, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned. | 06-20-2013 |
20130258627 | INTERPOSER-BASED DAMPING RESISTOR - Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer. | 10-03-2013 |
20140325105 | MEMORY SYSTEM COMPONENTS FOR SPLIT CHANNEL ARCHITECTURE - In one form, a memory module includes a first plurality of memory devices comprising a first rank and having a first group and a second group, and first and second chip select conductors. The first chip select conductor interconnects chip select input terminals of each memory device of the first group, and the second chip select conductor interconnects chip select input terminals of each memory device of the second group. In another form, a system includes a memory controller that performs a first burst access using both first and second portions of a data bus and first and second chip select signals in response to a first access request, and a second burst access using a selected one of the first and second portions of the data bus and a corresponding one of the first and second chip select signals in response to a second access request. | 10-30-2014 |
20150378603 | INTEGRATED CONTROLLER FOR TRAINING MEMORY PHYSICAL LAYER INTERFACE - A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm. | 12-31-2015 |
Patent application number | Description | Published |
20100040537 | Prostaglandin E2 Binding Proteins and Uses Thereof - The present invention encompasses prostaglandin E | 02-18-2010 |
20100266531 | IL-17 BINDING PROTEINS - Proteins that bind IL-17 and/or IL-17F are described along with there use in composition and methods for treating, preventing, and diagnosing IL-17 related diseases and for detecting IL-17 in cells, tissues, samples, and compositions. | 10-21-2010 |
20130243763 | TREATMENT OF HIDRADENITIS SUPPURATIVA (HS) USING TNFalpha ANTIBODIES - Methods of treating TNFα-related disorders comprising administering TNFα inhibitors, including TNFα antibodies are described. | 09-19-2013 |
20130243786 | TREATMENT OF JUVENILE RHEUMATOID ARTHRITIS (JRA) - Methods of treating TNFα-related disorders comprising administering TNFα inhibitors, including TNFα antibodies are described. | 09-19-2013 |
20140017246 | IL-17 BINDING PROTEINS - Proteins that bind IL-17 and/or IL-17F are described along with there use in composition and methods for treating, preventing, and diagnosing IL-17 related diseases and for detecting IL-17 in cells, tissues, samples, and compositions. | 01-16-2014 |
20140286939 | TREATMENT OF TNFALPHA RELATED DISORDERS - Methods of treating TNFα-related disorders comprising administering TNFα inhibitors, including TNFα antibodies are described. | 09-25-2014 |
20140286940 | TREATMENT OF TNFALPHA RELATED DISORDERS - Methods of treating TNFα-related disorders comprising administering TNFα inhibitors, including TNFα antibodies are described. | 09-25-2014 |
20140286941 | TREATMENT OF TNFALPHA RELATED DISORDERS - Methods of treating TNFα-related disorders comprising administering TNFα inhibitors, including TNFα antibodies are described. | 09-25-2014 |
20140335564 | IL-17 BINDING PROTEINS - Proteins that bind IL-17 and/or IL-17F are described along with there use in composition and methods for treating, preventing, and diagnosing IL-17 related diseases and for detecting IL-17 in cells, tissues, samples, and compositions. | 11-13-2014 |
20140343267 | IL-17 BINDING PROTEINS - Proteins that bind IL-17 and/or IL-17F are described along with there use in composition and methods for treating, preventing, and diagnosing IL-17 related diseases and for detecting IL-17 in cells, tissues, samples, and compositions. | 11-20-2014 |
20140348834 | IL-17 BINDING PROTEINS - Proteins that bind IL-17 and/or IL-17F are described along with their use in composition and methods for treating, preventing, and diagnosing IL-17 related diseases and for detecting IL-17 in cells, tissues, samples, and compositions. | 11-27-2014 |
20140348856 | IL-17 BINDING PROTEINS - Proteins that bind IL-17 and/or IL-17F are described along with their use in composition and methods for treating, preventing, and diagnosing IL-17 related diseases and for detecting IL-17 in cells, tissues, samples, and compositions. | 11-27-2014 |
20140356909 | IL-17 BINDING PROTEINS - Proteins that bind IL-17 and/or IL-17F are described along with their use in composition and methods for treating, preventing, and diagnosing IL-17 related diseases and for detecting IL-17 in cells, tissues, samples, and compositions. | 12-04-2014 |
20150218268 | Use of TNFalpha Inhibitor for Treatment of Psoriasis - The invention describes methods of treating erosive polyarthritis comprising administering a TNFα antibody, or antigen-binding portion thereof. The invention also describes a method for testing the efficacy of a TNFα antibody, or antigen-binding portion thereof, for the treatment of erosive polyarthritis. | 08-06-2015 |
20150218269 | USE OF TNFALPHA INHIBITOR FOR TREATMENT OF PSORIATIC ARTHRITIS - The invention describes methods of treating erosive polyarthritis comprising administering a TNFα antibody, or antigen-binding portion thereof. The invention also describes a method for testing the efficacy of a TNFα antibody, or antigen-binding portion thereof, for the treatment of erosive polyarthritis. | 08-06-2015 |
20150368335 | TREATMENT OF TNF-ALPHA RELATED DISORDERS - Methods of treating TNFα-related disorders comprising administering TNFα inhibitors, including TNFα antibodies are described. | 12-24-2015 |
Patent application number | Description | Published |
20130232318 | METHODS, APPARATUS, AND INSTRUCTIONS FOR CONVERTING VECTOR DATA - A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed. | 09-05-2013 |
20150074354 | DEVICE, SYSTEM AND METHOD FOR USING A MASK REGISTER TO TRACK PROGRESS OF GATHERING ELEMENTS FROM MEMORY - A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed. | 03-12-2015 |
20150100746 | SYSTEM AND METHOD FOR UNIFORM INTERLEAVING OF DATA ACROSS A MULTIPLE-CHANNEL MEMORY ARCHITECTURE WITH ASYMMETRIC STORAGE CAPACITY - Systems and methods for uniformly interleaving memory accesses across physical channels of a memory space with a non-uniform storage capacity across the physical channels are disclosed. An interleaver is arranged in communication with one or more processors and a system memory. The interleaver identifies locations in a memory space supported by the memory channels and is responsive to logic that defines virtual sectors having a desired storage capacity. The interleaver accesses the asymmetric storage capacity uniformly across the virtual sectors in response to requests to access the memory space. | 04-09-2015 |
20150370707 | DISUNITED SHARED-INFORMATION AND PRIVATE-INFORMATION CACHES - Systems and methods pertain to a multiprocessor system comprising disunited cache structures. A first private-information cache is coupled to a first processor of the multiprocessor system. The first private-information cache is configured to store information that is private to the first processor. A first shared-information cache which is disunited from the first private-information cache is also coupled to the first processor. The first shared-information cache is configured to store information that is shared/shareable between the first processor and one or more other processors of the multiprocessor system. | 12-24-2015 |
Patent application number | Description | Published |
20090171994 | DEVICE, SYSTEM, AND METHOD FOR IMPROVING PROCESSING EFFICIENCY BY COLLECTIVELY APPLYING OPERATIONS - A system and method for generating a single compressed vector including two or more predetermined attribute values. For each of a plurality of data points such as pixels, if a first and a second attribute values of the data point are equal to a first and a second, respectively, of the two or more predetermined attribute values, the compressed vector is used to operate on the data point. Other embodiments are described and claimed. | 07-02-2009 |
20090172291 | MECHANISM FOR EFFECTIVELY CACHING STREAMING AND NON-STREAMING DATA PATTERNS - A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data. | 07-02-2009 |
20090172349 | METHODS, APPARATUS, AND INSTRUCTIONS FOR CONVERTING VECTOR DATA - A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed. | 07-02-2009 |
20090172364 | DEVICE, SYSTEM, AND METHOD FOR GATHERING ELEMENTS FROM MEMORY - A system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed. | 07-02-2009 |
20110099333 | MECHANISM FOR EFFECTIVELY CACHING STREAMING AND NON-STREAMING DATA PATTERNS - A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data. | 04-28-2011 |
20110264863 | DEVICE, SYSTEM, AND METHOD FOR USING A MASK REGISTER TO TRACK PROGRESS OF GATHERING ELEMENTS FROM MEMORY - A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed. | 10-27-2011 |
20140019720 | METHODS, APPARATUS, AND INSTRUCTIONS FOR CONVERTING VECTOR DATA - A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed. | 01-16-2014 |
Patent application number | Description | Published |
20100180989 | Aluminum alloy - The aluminum alloy is an aluminum-magnesium-scandium-zirconium alloy having a long term corrosion resistance combined with high strength as compared to standard AA 5052 alloy, and is suitable for use in marine and salt water environments with a minimum of corrosion. The aluminum alloy contains about 2.2-3.0 wt. % magnesium, about 0.1-0.97 wt. % scandium, and about 0.14-0.9 wt. % zirconium. The alloy may also contain about 0.1-0.4% wt. % iron, 0.001-0.2 wt. % chromium, 0.02-0.94 wt. % titanium, and silicon, copper, zinc and manganese up to about 0.20 wt. %, 0.1 wt. %, 0.1 wt. %, and 0.01 wt. %, respectively, either as additives intentionally added during processing or as impurities, the remainder being aluminum. | 07-22-2010 |
20150353658 | SUPPORTED METALLOCENE CATALYST FOR OLEFIN POLYMERIZATION - The supported metallocene catalyst for olefin polymerization is ( | 12-10-2015 |
20150353659 | SUPPORTED METALLOCENE CATALYST FOR OLEFIN POLYMERIZATION - The supported metallocene catalyst for olefin polymerization is ( | 12-10-2015 |