Ichige, JP
Atsushi Ichige, Hitachinaka JP
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20080285841 | IMAGE PROCESSING UNIT FOR WAFER INSPECTION TOOL - An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection. | 11-20-2008 |
20140232830 | STEREOSCOPIC IMAGING APPARATUS - In order to provide a stereoscopic imaging apparatus that can acquire, in a case in which a brightness different is large, parallax information containing a parallax image in all image capturing frames, provided are an image acquisition unit that acquires a first image and a second image different from the first image in exposure time, a gain and offset correction unit | 08-21-2014 |
Eita Ichige, Tsukuba-Shi, Ibaraki JP
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20160053285 | GENETICALLY MODIFIED CLOSTRIDIUM SACCHAROPERBUTYLACETONICUM - The present invention provides a means for producing butanol in butanol fermentation with high efficiency. The present invention relates to a genetically modified microorganism of | 02-25-2016 |
Eita Ichige, Ibaraki JP
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20090239273 | NOVEL HIGH-ACTIVITY MODIFIED S-HYDROXYNITRILE LYASE - This invention relates to a novel high-activity modified S-hydroxynitrile lyase (SHNL). More particularly, this invention relates to novel high-activity modified SHNL that is obtained by substituting amino acids at given sites (14, 44, 66, 94, 103, 118, 122, 125, 127, 129, 147, 148, 152, 212, and 216) or inserting amino acid at a given site (between amino acids 128 and 129) of the amino acid sequence (SEQ ID NO: 2) of wild-type SHNL. | 09-24-2009 |
Hideaki Ichige, Tokyo JP
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20130214171 | RADIOACTIVITY EVALUATION METHOD AND RADIOACTIVITY EVALUATION SYSTEM - According to an embodiment, a radioactivity evaluation method has: a first input step; a selection step in which the calculating section selects a representative neutron energy spectrum and a representative neutron fluence rate; a second input step; an radioactivity calculating step in which the calculating section calculates quantities of the radioactivity that correspond to the representative neutron energy spectra and the representative neutron fluence rates; a data storing step; a nuclide-by-nuclide radioactivation reaction rate calculating step in which the calculating section calculates a radioactivation reaction rate of each nuclide based on the neutron energy spectra at the position of each of the object sections; an object-by-object adding-up step; a nuclide determining step; and an object position determining step. | 08-22-2013 |
Hidetoshi Ichige, Tsukuba-Shi JP
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20110000067 | METHOD FOR MANUFACTURING ELECTROPHOTOGRAPHIC ELASTIC ROLLER - A method for manufacturing a low-cost electrophotographic elastic roller having a good dimensional precision is provided. In that method, in which both end parts of a shaft core body are gripped and fixed in a vertical direction, an inclination of a central axis is corrected, a circular coating head including a circular slit is used so that the shaft core body is moved in the direction, and a elastic layer material is ejected from the slit to be coated on the shaft core body, the method includes: a maximum deflection coordinate in a longitudinal direction of the shaft core body is detected with a central axis of the shaft core body as a base point coordinate before coating; a central position of the head is moved at constant from the base point to the maximum during coating, and the position is moved to the base point after the head has reached the maximum. | 01-06-2011 |
Keisuke Ichige, Aichi-Ken JP
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20110046861 | HYDRAULIC CONTROL APPARATUS - A switching apparatus is provided in a hydraulic control apparatus having a fluid transmission apparatus; a lockup clutch; a switching valve that controls engagement of the lockup clutch; and a control oil pressure generation apparatus that pressurizes oil and outputs a control oil pressure to control activation of the switching valve. The switching apparatus executes a control to warm the oil input into the control oil pressure generation apparatus if the temperature of the oil is below a predetermined temperature and prohibits execution of the control to warm the oil input into the control oil pressure generation apparatus if the temperature of the oil equals or exceeds the predetermined temperature. | 02-24-2011 |
20120024392 | LUBRICATING DEVICE - This lubricating device | 02-02-2012 |
Keisuke Ichige, Nagoya-Shi JP
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20140326092 | TOOTHED WHEELS AND TRANSMISSION - A pair of toothed wheels that mesh with each other includes a plateau portion. The surface of the plateau portion is a plateau-structure surface formed on each tooth face of each of the pair of the toothed wheels, with peak portions of convexities, out of a plurality of concavities and the convexities provided on the each tooth face, being flat. A reduced valley depth Rvk of the plateau portion of one of the pair of the toothed wheels as defined in JISB0671-2 is greater than the reduced valley depth Rvk of the plateau portion of the other of the pair of the toothed wheels. The area occupied by the concavities in the plateau portion of the one of the toothed wheels is larger than the area occupied by the concavities in the plateau portion of the other toothed wheel. | 11-06-2014 |
20150028719 | SLIP RING SYSTEM - In a slip ring system ( | 01-29-2015 |
Kenji Ichige, Yokohama JP
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20110242304 | BIOMETERIC AUTHENTICATION APPARATUS - A biometric authentication apparatus, for enabling to detect a counterfeit when counterfeited information is inputted, thereby preventing from a mischievous authentication, comprises: a registration unit for register a biometric information pattern; a lighting unit for irradiating a lighting upon a photographing target; an image sensor for photographing the photographing target, upon which the lighting is irradiated by the lighting unit; an authentication process unit for extracting the biometric information pattern from a video signal, being outputted from the image sensor, and thereby comparing it to a biometric information pattern, being registered in the registration unit; and a control unit for controlling a lighting intensity of the lighting irradiated by the lighting unit, wherein the control unit changes the lighting intensity of the lighting irradiated by the lighting unit, and determines on whether the photographing target is a living body or not, with using the change of brightness of the video signal outputted by the image sensor. | 10-06-2011 |
20130201386 | IMAGE SIGNAL PROCESSING APPARATUS AND IMAGE SIGNAL PROCESSING METHOD - An image signal processing apparatus is disclosed. This device includes a divided area setup unit which sets rows and columns of divided areas in an area defined by a focal evaluation value calculation area setup unit, a high-brightness pixel presence/absence check unit which determines whether a high-brightness pixel exists in each divided area defined by the divided area setup unit, a high-brightness pixel judgment threshold setup unit which sets a threshold for use in the high-brightness pixel presence/absence checker, and an area-selective focal point evaluation value calculation unit which selects a divided area that was determined by the high-brightness pixel checker to contain no high-brightness pixels as a focal evaluation value calculation target and then calculates a focal evaluation value. Variable control of the high-brightness pixel judgment threshold that is set by the high-brightness pixel judgment threshold setup unit is started and stopped at specified timings. | 08-08-2013 |
Masayuki Ichige, Kanagawa-Ken JP
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20120007192 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a plurality of memory cell blocks, a plurality of first wirings, a plurality of second wirings, and a contact. Each of the memory cell blocks includes a plurality of memory cell units. Each of the plurality of memory cell units includes a plurality of memory cells and is provided in a first direction at a prescribed spacing. The plurality of memory cell blocks is arranged in a second direction intersecting with the first direction. The plurality of first wirings extends in the second direction and is provided in the first direction at a prescribed spacing. The plurality of second wirings is provided at least one of above and below the first wiring. The contact is provided at both end portions of the second wiring in the second direction and connects the first wiring to the second wiring. A width dimension of the second wiring along the first direction is larger than a width dimension of the first wiring along the first direction. | 01-12-2012 |
20130015518 | SEMICONDUCTOR MEMORY DEVICEAANM SATO; HiroyasuAACI Kanagawa-kenAACO JPAAGP SATO; Hiroyasu Kanagawa-ken JPAANM NISHIHARA; KiyohitoAACI Kanagawa-kenAACO JPAAGP NISHIHARA; Kiyohito Kanagawa-ken JPAANM NAWATA; HidefumiAACI Kanagawa-kenAACO JPAAGP NAWATA; Hidefumi Kanagawa-ken JPAANM ICHIGE; MasayukiAACI Kanagawa-kenAACO JPAAGP ICHIGE; Masayuki Kanagawa-ken JPAANM OHBA; RyujiAACI Kanagawa-kenAACO JPAAGP OHBA; Ryuji Kanagawa-ken JP - In general, according to one embodiment, a semiconductor memory device includes active areas extending in a first direction, tunnel films provided on the active areas, floating gate electrodes provided on the tunnel films, an interelectrode insulating film provided on the floating gate electrodes and extending in a second direction, a control gate electrode provided on the interelectrode insulating film and extending in the second direction, a lower insulating portion provided between the active areas, between the tunnel films, and between the floating gate electrodes adjacent in the second direction, and an upper insulating portion provided between the lower insulating portion and the interelectrode insulating film. The lower insulating portion includes a void. Relative dielectric constant of the upper insulating portion is higher than that of the lower insulating portion. Relative dielectric constant of the interelectrode insulating film is higher than that of the upper insulating portion. | 01-17-2013 |
20130077461 | STORAGE DEVICE - A storage device includes a recording medium, a probe, a substrate, and a processing unit. The recording medium stores a signal. The probe reads or writes the signal to/from the recording medium. The substrate is provided with the probe via a conductive anchor interposed therebetween and a first connection terminal connected to the probe. The processing unit is provided on the substrate and has a second connection terminal. The second connection terminal is connected to the first connection terminal. | 03-28-2013 |
Masayuki Ichige, Yokohama-Shi JP
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20090154214 | SEMICONDUCTOR MEMORY - Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AA | 06-18-2009 |
20100155814 | EEPROM ARRAY WITH WELL CONTACTS - A semiconductor integrated circuit device includes a cell well, a memory cell array formed on the cell well and having a memory cell area and cell well contact area, first wiring bodies arranged in the memory cell area, and second wiring bodies arranged in the cell well contact area. The layout pattern of the second wiring bodies is the same as the layout pattern of the first wiring bodies. The cell well contact area comprises cell well contacts that have the same dopant type as the cell well and that function as source/drain regions of dummy transistors formed in the cell well contact area. | 06-24-2010 |
20100173471 | NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME - A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor. | 07-08-2010 |
20100309708 | SEMICONDUCTOR MEMORY - Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AA | 12-09-2010 |
20120119304 | SEMICONDUCTOR MEMORY - A semiconductor memory includes: a plurality of active regions AA | 05-17-2012 |
20120235218 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a device includes a semiconductor substrate, a first region including a first well which is formed in substrate, a second well which is formed in substrate and on first well, and a memory cell which is formed on second well, and a second region including a third well which is formed in substrate, and a first transistor which is formed on third well. The device includes a third region including a second transistor which is formed on semiconductor substrate, and a fourth region including a fourth well which is formed in semiconductor substrate, a fifth well which is formed in substrate and on fourth well, and a third transistor which is formed on fifth well. Bottoms of first well and fourth well are lower than a bottom of third well, and bottom of third well is lower than bottoms of second well and fifth well. | 09-20-2012 |
20140056048 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element. A third line extends through a plurality of the memory mats. A second variable resistance element is connected between the third line and the second line of each of the plurality of memory mats. | 02-27-2014 |
20150092468 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element. A third line extends through a plurality of the memory mats. A second variable resistance element is connected between the third line and the second line of each of the plurality of memory mats. | 04-02-2015 |
Masayuki Ichige, Yokkaichi-Shi JP
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20110108905 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells. | 05-12-2011 |
20120181598 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells. | 07-19-2012 |
20150070999 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a nonvolatile semiconductor memory device includes a plurality of memory cells and a control circuit. The memory cell includes a semiconductor layer, a gate insulating layer, a floating gate, a lower control gate, and an upper control gate. The semiconductor layer extends in a certain direction. The lower control gate is formed on the floating gate via an insulating layer. The upper control gate is formed on the lower control gate via an insulating layer. In addition, the control circuit, when performing a write operation, applies a first pass voltage to the upper control gate in a selected memory cell, and applies a first write voltage which is larger than the first pass voltage to the upper control gate in an adjacent memory cell formed on an identical semiconductor layer to the selected memory cell and adjacent to the selected memory cell. | 03-12-2015 |
Masayuki Ichige, Minato-Ku JP
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20120037976 | NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME - A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor. | 02-16-2012 |
Masayuki Ichige, Yokkaichi JP
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20150262671 | NON-VOLATILE MEMORY DEVICE - A nonvolatile memory device according to an embodiment includes: a semiconductor substrate; a memory cell array unit provided on an upper side of the semiconductor substrate; an integrated circuit unit provided between the memory cell array unit and the semiconductor substrate; and a peripheral circuit unit provided on the semiconductor substrate. The integrated circuit unit includes: a first contact electrode electrically connected to one of plurality of first interconnection layers; a second contact electrode connected to the peripheral circuit unit; and a first switching element connected between the first contact electrode and the second contact electrode, and conduction between the first contact electrode and the second contact electrode being controlled by a control circuit unit provided in the peripheral circuit unit. | 09-17-2015 |
20160035420 | NONVOLATILE MEMORY DEVICE AND METHOD FOR CONTROLLING SAME - According to one embodiment, a device includes: word lines extending in a first direction, widths of the word lines in a second direction intersecting the first direction having a first width and a second width greater than the first width; bit lines provided above or under the word lines, the bit lines extending in the second direction, widths of the bit lines in the first direction having a third width and a forth width greater than the third width; storage elements; and a control circuit applying a potential for at least one of a plurality of non-selected word lines and a plurality of non-selected bit lines other than a selected word line and a selected bit line connected to a selected storage element, among the word lines and the bit lines, the potential applied thereto according to a width thereof. | 02-04-2016 |
Takahiro Ichige, Tokyo JP
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20140213786 | Method for Producing Coumarin Derivative - The present invention provides a novel method for producing a compound represented by general formula (VII) below or a pharmaceutically acceptable salt thereof or a synthetic intermediate thereof: | 07-31-2014 |
Tatsuo Ichige, Saitama JP
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20090193909 | CHASSIS DYNAMOMETER - A chassis dynamometer for a vehicle has a motor having a rotor, rollers on which wheels of the vehicle are disposed, a flange portion extending inward in a radial direction from each of the rollers, and a rotor bracket for supporting the rotor of the motor. The flange portion and the rotor bracket are connected via a torque meter capable of measuring at least an outer peripheral tangential force of said roller. | 08-06-2009 |
20120060596 | CHASSIS DYNAMOMETER - A chassis dynamometer for a vehicle has a base seat, a fixed shaft having one end thereof attached to the base seat, a rotary proximal portion rotatably supported to the fixed shaft, a roller connected to the rotary proximal portion, for loading a wheel of a vehicle, and a motor connected to the roller so that power can be transmitted therebetween. The roller has a single flange portion connected to the rotary proximal portion and extending obliquely to the axis, and an outer peripheral portion extending both axial directions from an outer periphery of the flange portion and disposed outward in the radial direction of the motor. | 03-15-2012 |
Tatsuo Ichige, Kitamoto-Shi JP
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20150128725 | AXIAL FORCE SENSOR - [Object] To provide a low-cost, compact, high-precision axial force sensor. | 05-14-2015 |
Tatsurou Ichige, Tokyo JP
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20080227784 | N-(3,4-disubstituted phenyl) salicylamide derivatives - A compound represented by the following formula (I) or a salt thereof: | 09-18-2008 |
Tomoya Ichige, Sakura-Shi JP
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20160043525 | AMPLIFICATION OPTICAL FIBER AND FIBER LASER DEVICE USING THE SAME - The refractive index of the first core portion | 02-11-2016 |
Toshiaki Ichige, Hitachi-Shi, Ibaraki JP
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20160079646 | SIGNAL TRANSMISSION FLAT CABLE - A signal transmission flat cable is provided with an upper electrically insulating thin-film layer ( | 03-17-2016 |
Toukichi Ichige, Tokyo JP
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20090090793 | BUBBLE-GENERATING STRUCTURE, AND SHOWERHEAD THAT INCLUDES THAT STRUCTURE - Using a simple structure, a new function is added to a liquid such as tap water by taking a gas into the liquid. The bubble-generating structure of the present invention includes (1) a water-discharging nozzle, which is provided inside a pipe, (2) a receiving member, which is situated a specified distance from the water-discharging nozzle and which includes a flow path for passing liquid emitted from the water-discharging nozzle, and (3) an air hole provided in such a way as to take air into a space between the water-discharging nozzle and the receiving member. By taking in air due to a suction force that is generated when the liquid passes along the flow path, bubbles are generated in the liquid. When such a structure for generating bubbles in the liquid is included in a showerhead, a person taking a shower using the showerhead can have a healthy and comfortable feeling while showering. | 04-09-2009 |
Toukichi Ichige, Chiyoda-Ku Tokyo JP
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20090071409 | PIG FARMING METHOD - A pig-raising method is provided that decreases the bad odors of pig excreta, improves pig-raising efficiency, and stimulates the growth of the pigs so as to improve the quality of their meat so as to enable pig farmers to obtain good-quality meat. With the pig-raising method of the present invention (1) a pig house is provided with a water-supply system that passes water through first ceramic particles, with said activated water then supplied to pigs for drinking, and (2) pigs are fed a blended feed that consists of ordinary feed and second ceramic particles whose main component is silica obtained from plant materials and which constitutes 0.1%-3.0% of the weight of said blended feed. Further, there is spread over the floors of the pig houses a floor covering that consists of a mixture of sawdust and the second ceramic particles, with said second ceramic particles constituting 1.0%-10% of the weight of said floor covering. | 03-19-2009 |
Yasuhiro Ichige, Ibaraki JP
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20140370707 | POLISHING LIQUID FOR METAL AND POLISHING METHOD - The present invention relates to a metal polishing liquid for polishing at least a part of metal in a substrate having the metal, comprising, component A: a metal solubilizer containing amino acids, component B: compounds having the benzotriazole skeleton, and component C: an acrylic acid polymer having the weight average molecular weight of 10,000 or more, and having the mass ratio between the component B and the component C, (component B:component C), to be 1:1 to 1:5. Use of the metal polishing liquid can simultaneously yield high polishing rates and low etching rates at higher level, enabling to form an embedded pattern with higher reliability. | 12-18-2014 |
Yukiko Ichige, Tokyo JP
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20120253672 | INFORMATION DISPLAY TERMINAL - An information display terminal allows a user to grasp rapidly and surely the direction to a destination, and can guide the user to the destination without placing a burden on the user. The information display terminal is provided at a passage, and its display screen displays a route guidance screen that guides a route to the destination. The route guidance screen displays a pseudo-action image that shows the walking motion, and a destination display information image indicating a destination name such as “Subway Ticket Gate”. The action image shows the motion of walking toward the destination, but the display position does not change. The destination display information image is displayed in front of the action image in the advancing direction. | 10-04-2012 |
20150053596 | DESALINATION SYSTEM - There is provided a desalination system capable of monitoring a situation of a semipermeable membrane element in real time. | 02-26-2015 |