Patent application number | Description | Published |
20090237054 | Digital Control of Power Converters - A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, and comparing the digital error signal to at least a first threshold value. If the digital error signal is less than the first threshold value, a pulse is generated to control the power converter. Another embodiment includes multiple thresholds that may be compared against the digital error signal. | 09-24-2009 |
20090237959 | Digital Control of Power Converters - A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, a digital pulse generator, and a pre-driver to control the power converter. Another embodiment also includes a digital filter as part of the control loop that may be used to control the loop characteristics of the control circuit. Yet another embodiment replaces the differential circuit with a sigma-delta analog-to-digital modulator and a decimator. | 09-24-2009 |
20090237966 | DIGITAL CONTROL OF POWER CONVERTERS - A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, and comparing the digital error signal to at least a first threshold value. If the digital error signal is less than the first threshold value, a pulse is generated to control the power converter. Another embodiment includes multiple thresholds that may be compared against the digital error signal. | 09-24-2009 |
20090316461 | Method and Apparatus for Performing Variable Word Width Searches in a Content Addressable Memory - A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR. | 12-24-2009 |
20100033216 | SYNCHRONIZATION CIRCUIT AND METHOD WITH TRANSPARENT LATCHES - A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock. | 02-11-2010 |
20100045376 | CLASS D AMPLIFIER CONTROL CIRCUIT AND METHOD - Circuit and method for a Class D amplifier. In one exemplary embodiment, an audio amplifier is disclosed. A closed loop configuration for driving high and low side driver transistors is provided, each circuit is compatible with advanced sub micron semiconductor processes. The analog time varying input is coupled to one input of a sigma delta analog to digital converter. A feedback signal from the output is also input to the analog to digital converter. A bit stream is output by the analog to digital converter. A decimator receives this bit stream and downconverts the samples to digital values at a lower frequency. A digital filter with adaptable coefficients is used to filter that signal and a digital pulse width modulator then develops an analog differential PWM signal. A predriver inputs the PWM signal and derives the output gating signals to control the high and low side drivers of a Class D amplifier. | 02-25-2010 |
20110006844 | Class D Amplifier Control Circuit and Method - Circuit and method for a Class D amplifier. In one exemplary embodiment, an audio amplifier is disclosed. A closed loop configuration for driving high and low side driver transistors is provided, each circuit is compatible with advanced sub micron semiconductor processes. The analog time varying input is coupled to one input of a sigma delta analog to digital converter. A feedback signal from the output is also input to the analog to digital converter. A bit stream is output by the analog to digital converter. A decimator receives this bit stream and downconverts the samples to digital values at a lower frequency. A digital filter with adaptable coefficients is used to filter that signal and a digital pulse width modulator then develops an analog differential PWM signal. A predriver inputs the PWM signal and derives the output gating signals to control the high and low side drivers of a Class D amplifier. | 01-13-2011 |
20110089916 | LDO REGULATORS FOR INTEGRATED APPLICATIONS - Embodiments of the invention are related to LDO regulators. In an embodiment, an amplifier drives the gate of a master source follower and of at least one slave source follower to form an LDO regulator. In an alternative embodiment, a charge pump drives the master source follower to form the regulator. Additional slave source followers may be used in conjunction with the charge pump and the master source follower to improve the regulator performance. Other embodiments are also disclosed. | 04-21-2011 |
20110228626 | SYNCHRONIZATION CIRCUIT AND METHOD WITH TRANSPARENT LATCHES - A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock. | 09-22-2011 |
20130024717 | Double Data Rate Output Circuit and Method - A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock. | 01-24-2013 |