Voldman, US
Bella Voldman, San Francisco, CA US
Patent application number | Description | Published |
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20080250420 | Jobstream Planner Considering Network Contention & Resource Availability - Disclosed is a computer-implemented planning process that aids a system administrator in the task of creating a job schedule. The process treats enterprise computing resources as a grid of resources, which provides greater flexibility in assigning resources to jobs. During the planning process, an administrator or other user, or software, builds a job-dependency tree. Jobs are then ranked according to priority, pickiness, and network centricity Difficult and problematic jobs then are assigned resources and scheduled first, with less difficult jobs assigned resources and scheduled afterwards. The resources assigned to the most problematic jobs then are changed iteratively to determine if the plan improves. This iterative approach not only increases the efficiency of the original job schedule, but also allows the planning process to react and adapt to new, ad-hoc jobs, as well as unexpected interruptions in resource availability. | 10-09-2008 |
Joel Voldman, Belmont, MA US
Patent application number | Description | Published |
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20090071831 | Methods and systems for producing arrays of particles - The invention provides apparatus and methods for arraying particles on a surface using dielectrophoresis. | 03-19-2009 |
20090258383 | OPTO-FLUIDIC ARCHITECTURE FOR PARTICLE MANIPULATION AND SORTING - This invention provides an apparatus for particle sorting, particle patterning, and methods of using the same. The sorting or patterning is opto-fluidics based, in that particles are applied to individual chambers in the device, detection and/or analysis of the particles is carried out, such that a cell or population whose removal or conveyance is desired is defined, and the cell or population is removed or conveyed via application of an optical force and flow-mediated conveyance or removal of the part. | 10-15-2009 |
20090294291 | ISO-DIELECTRIC SEPARATION APPARATUS AND METHODS OF USE - The present invention is directed to an iso-dielectric separation apparatus for separating particles based upon their electrical properties, and methods of using the apparatus. | 12-03-2009 |
20110045994 | PARTICLE CAPTURE DEVICES AND METHODS OF USE THEREOF - The present invention provides a device and methods of use thereof in microscale particle capturing and particle pairing. This invention provides particle patterning device, which mechanically traps individual particles within first chambers of capture units, transfer the particles to second chambers of opposing capture units, and traps a second type of particle in the same second chamber. The device and methods allow for high yield assaying of trapped cells, high yield fusion of trapped, paired cells, for controlled binding of particles to cells and for specific chemical reactions between particle interfaces and particle contents. The device and method provide means of identification of the particle population and a facile route to particle collection. | 02-24-2011 |
20140093911 | METHOD AND APPARATUS FOR IMAGE-BASED PREDICTION AND SORTING OF HIGH-PERFORMING CLONES - A method of predictive identification and separation of high-performing cells from a mixed population of cells includes distributing cells belonging to the mixed population to a plurality of open chambers; identifying open chambers containing desired cells and open chambers containing undesired cells; selectively sealing at least one open chamber containing undesired cells; and recovering the desired cells from the open chambers. Cells can be predictively assigned as desired or undesired based on an automated image analysis algorithm. | 04-03-2014 |
20140199745 | ELECTROKINETIC CONFINEMENT OF NEURITE GROWTH FOR DYNAMICALLY CONFIGURABLE NEURAL NETWORKS - Systems and methods for altering neurite growth are generally described. In some embodiments, a system may include a neuron comprising a neurite and electrodes able to generate a physical guidance cue. The physical guidance cue may be used to alter the growth of the neurite and may be temporally and spatially dynamic, such that neurite growth may be altered in a spatial and/or temporal manner. Dynamic control of neurite growth may be used to form directional neural connections, intersections, and/or overlaps. | 07-17-2014 |
20140199746 | ELECTROKINETIC CONFINEMENT OF NEURITE GROWTH FOR DYNAMICALLY CONFIGURABLE NEURAL NETWORKS - Systems and methods for altering neurite growth are generally described. In some embodiments, a system may include a neuron comprising a neurite and electrodes able to generate a physical guidance cue. The physical guidance cue may be used to alter the growth of the neurite and may be temporally and spatially dynamic, such that neurite growth may be altered in a spatial and/or temporal manner. Dynamic control of neurite growth may be used to form directional neural connections, intersections, and/or overlaps. | 07-17-2014 |
Joel Voldman, Somerville, MA US
Patent application number | Description | Published |
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20080289966 | Microscale sorting cytometer - The present invention provides a device and methods of use thereof in microscale cell sorting. This invention provides sorting cytometers, which trap individual cells within vessels following exposure to dielectrophoresis, allow for the assaying of trapped cells, such that a population is identified whose isolation is desired, and their isolation. | 11-27-2008 |
Steven Voldman, South Burlington, VT US
Patent application number | Description | Published |
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20080201677 | Integrated Circuit (IC) Chip Input/Output (I/O) Cell Design Optimization Method And IC chip With Optimized I/O Cells - A method of fabricating an integrated circuit (IC) chip. A standard cell macro (e.g., an Off Chip Interface (OCI) cell) is defined with circuit elements identified as in a macro domain. A variable macro boundary is defined for the standard cell macro. Shapes are selectively added to design layers in the macro boundary to occupy existing white space. Each supplemented layer is checked for technology rules violations in the macro boundary. Each layer is also checked for known sensitivities in the macro boundary. | 08-21-2008 |
Steven H. Voldman, Essex Junction, NY US
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20110117714 | Integration of Multiple Gate Oxides with Shallow Trench Isolation Methods to Minimize Divot Formation - A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer. | 05-19-2011 |
Steven Howard Voldman, Essex Junction, VT US
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20090236662 | GUARD RING STRUCTURES FOR HIGH VOLTAGE CMOS/LOW VOLTAGE CMOS TECHNOLOGY USING LDMOS (LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR) DEVICE FABRICATION - A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first transistor on the semiconductor substrate, and a guard ring on the semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The guard ring includes a semiconductor material doped with a doping polarity. A first doping profile of a first doped transistor region of the first transistor in the reference direction and a second doping profile of a first doped guard-ring region of the guard ring in the reference direction are essentially a same doping profile. The guard ring forms a closed loop around the first transistor. | 09-24-2009 |
20110039378 | METHOD OF FABRICATING ESD DEVICES USING MOSFET AND LDMOS ION IMPLANTATIONS - A method of forming complementary metal-oxide-silicon logic field effect transistors, high power transistors and electrostatic discharge protection diodes and/or electrostatic discharge protection shunt transistors on the same integrated circuit chip using ion implantations used to fabricate the field effect transistors and high-power transistor to simultaneously fabricate the electrostatic discharge protection diodes and/or electrostatic discharge protection shunt transistors. | 02-17-2011 |