Patent application number | Description | Published |
20090235116 | Systems and Methods for Regenerating Data from a Defective Medium - Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for data regeneration is disclosed that includes a data input derived from the medium. A data detector and a data recovery system receive the data input. The data detector provides a first soft output, and the data recovery system provides a second soft output. The first soft output and the second soft output are provided to a multiplexer. A media defect detector performs a media defect detection process, and provides a defect flag that indicates whether the data input is derived form a defective portion of the medium. The defect flag is provided to the multiplexer where it is used to select whether the first soft output or the second soft output is provides as an extrinsic output. | 09-17-2009 |
20090268575 | Systems and Methods for Reducing Attenuation of Information Derived from a Defective Medium - Various embodiments of the present invention provide systems and methods for data regeneration. For example, a method for data regeneration is disclosed that includes receiving a data input derived from a medium, determining a media defect corresponding to the data input, and determining an attenuation factor associated with the defective medium. Based at least in part on the determination that the medium is defective, amplifying the data input by a derivative of the attenuation factor to regenerate the data. | 10-29-2009 |
20090268848 | Systems and Methods for Filter Based Media Defect Detection - Various embodiments of the present invention provide systems and methods for media defect detection. For example, a data receiving system is disclosed that includes a data signal provided from a medium that may include a defective portion. An absolute value circuit receives the data signal and provides an output corresponding to an absolute value of the data signal. The output corresponding to the absolute value of the data signal is input to a filter that filters it and provides a filtered output. In some cases, the filter is a digital filter operable to integrate the absolute value of the data signal. A comparator receives the output from the filter and compares it with a threshold value. The result of the comparison indicates a defect status of the medium. | 10-29-2009 |
20090271670 | Systems and Methods for Media Defect Detection Utilizing Correlated DFIR and LLR Data - Various embodiments of the present invention provide systems and methods for media defect detection. For example, a method for detecting a media defect is disclosed. The method includes deriving a data input from a medium and performing a MAP detection on the data input. The MAP detection provides an NRZ output and an LLR output corresponding to the data input. A product of the NRZ output is correlated with a product of the LLR output to produce a correlated output. The correlated output is compared with a threshold value, and a media defect output is asserted based at least in part on the result of the comparison of the correlated output with the threshold value. | 10-29-2009 |
20090273492 | Systems and Methods for Queue Based Data Detection and Decoding - Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes at least a first detector, a second detector, a decoder, and a queuing buffer. The first detector is operable to perform a data detection on an input data set at a first time. The decoder receives a derivation of an output from the first detector and performs a decoding process. Where the decoding process fails to converge, the decoder output is passed to the second detector for a subsequent detection and decoding process at a second time. | 11-05-2009 |
20100070837 | Power Reduced Queue Based Data Detection and Decoding Systems and Methods for Using Such - Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes a first detector, a second detector, a decoder and a unified memory buffer. An input data set is received by the first detector that performs a data detection and provides a first detected data set. The decoder receives a derivative of the first detected data set and performs a decoding operation that yields a decoded data set. In some cases, the derivative of the first detected data set is an interleaved version of the first detected data set. The decoded data set is written to a unified memory buffer. The first decoded data set is retrievable from the unified memory buffer and a derivative thereof is provided to the second detector. In some cases, the derivative of the decoded is a de-interleaved version of the decoded data set. The second detector is operable to perform a data detection on the derivative of the decoded data set and to provide a second detected data set that is written to the unified memory buffer. | 03-18-2010 |
20100083075 | Methods and Apparatus for Selective Data Retention Decoding in a Hard Disk Drive - Methods and apparatus are provided for improved physical re-read operations in a hard disk drive. The disclosed methods and apparatus selectively retain data in a hard disk drive. A signal is read in an iterative read channel by assigning a reliability metric to each of a plurality of segments in a read signal; repeating the assigning step for a plurality of read operations; and selectively retaining the segments based on the assigned reliability metric. The read signal can be obtained by positioning a transducer over a storage media. The reliability metric may be based on soft bit decisions; log likelihood ratios or a noise estimation of a given segment. | 04-01-2010 |
20100226033 | Systems and Methods for Enhanced Media Defect Detection - Various embodiments of the present invention provide systems and methods for detecting storage medium defects. As one example, a media defect detection system is disclosed that includes a data detector circuit that applies a detection algorithm to the data input and provides a hard output and a soft output. A first circuit combines a first derivative of the hard output with a derivative of the data input to yield a first combined signal. A second circuit combines a second derivative of the hard output with a derivative of the first combined signal to yield a second combined signal. A third circuit combines a derivative of the soft output with the second combined signal and a threshold value to yield a defect signal. | 09-09-2010 |
20100229031 | Systems and Methods for Recovering Information from a Defective Medium - Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for regenerating data is disclosed. The system includes a media defect detector that is operable to identify a potential media defect associated with a medium from which an input signal is derived, an attenuation amplitude detector that generates an attenuation factor, and a data detector. The data detector includes a first data path and a second data path. The first data path includes a bank of two or more selectable noise prediction filters and the second data path includes a fixed noise prediction filter and the attenuation factor. The data detector processes a derivative of the input signal using the second data path when the potential media defect is indicated, and processes the derivative of the input signal using the first data path when a media defect is not indicated. | 09-09-2010 |
20100265608 | Systems and Methods for Storage Channel Testing - Various embodiments of the present invention provide systems and methods for validating elements of storage devices. A an example, various embodiments of the present invention provide semiconductor devices that include a write path circuit, a read path circuit and a validation circuit. The write path circuit is operable to receive a data input and to convert the data input into write data suitable for storage to a storage medium. The read path circuit is operable to receive read data and to convert the read data into a data output. The validation circuit is operable to: receive the write data, augment the write data with a first noise sequence to yield a first augmented data series; and augment a derivative of the first augmented data series with a second noise sequence to yield the read data. | 10-21-2010 |
20100268996 | Systems and Methods for Predicting Failure of a Storage Medium - Various embodiments of the present invention provide systems and methods for determining storage medium health. For example, a storage device is disclosed that includes a storage medium and a data processing circuit. The data processing circuit receives a data set derived from the storage medium. The data processing circuit includes a data detector circuit, a data decoder circuit, and a health detection circuit. The data detector circuit receives the data set and provides a detected output. The data decoder circuit receives a derivative of the detected output and provides a decoded output. The health detection circuit receives an indication of a number of times that the data set is processed through the combination of the data detector circuit and the data decoder circuit. Further, the health detection circuit generates an indirect health status of the storage medium based at least in part on the number of times that the data set is processed through the combination of the data detector circuit and the data decoder circuit. | 10-21-2010 |
20100269023 | Systems and Methods for Multilevel Media Defect Detection - Various embodiments of the present invention provide systems and methods for deriving data from a defective media region. As an example, a method for deriving data from a defective media region is disclosed that includes providing a storage medium and performing a media defect detection that indicates a defective region on the storage medium. A first data decode is performed on data corresponding to the defective region. The first data decode yields a first output. It is determined that the first output failed to converge and based at least in part on the failure of the first output to converge, a second data decode is performed on the data corresponding to the defective region. The second data decode includes zeroing out any soft data corresponding to the defective region and providing a second output. | 10-21-2010 |
20100275096 | Systems and Methods for Hard Decision Assisted Decoding - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a processing loop circuit having a data detector and a soft decision decoder. The data detector provides a detected output, and the soft decision decoder applies a soft decoding algorithm to a derivative of the detected output to yield a soft decision output and a first hard decision output. The systems further include a queuing buffer and a hard decision decoder. The queuing buffer is operable to store the soft decision output, and the hard decision decoder accesses the soft decision output and applies a hard decoding algorithm to yield a second hard decision output. The data detector is operable to perform a data detection on a derivative of the soft decision output if the soft decision decoder and the hard decision decoder fail to converge | 10-28-2010 |
20100322048 | Systems and Methods for Codec Usage Control During Storage Pre-read - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an increased iteration enable signal, a first detector circuit, a second detector circuit, and a data decoding circuit. The first detector circuit receives a data set and performs a data detection on the data set to provide a detected data set. The data decoding circuit receives a derivative of the detected data set and performs a decoding process to provide a decoded data set. The decoded data set is provided to the second detector circuit based at least in part on an assertion level of the increased iteration enable signal. | 12-23-2010 |
20110029826 | Systems and Methods for Re-using Decoding Parity in a Detector Circuit - Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving an LDPC codeword, and grouping active bits from the LDPC codeword into a series of data bits including one or more user data bits including and at least one LDPC parity bit. The series of data bits satisfies an LDPC parity equation. | 02-03-2011 |
20110029835 | Systems and Methods for Quasi-Cyclic LDPC Code Production and Decoding - Various embodiments of the present invention provide systems and methods for generating a parity check matrix used in data processing. As an example, a method for generating a parity check matrix including selecting a non-affiliated variable node; identifying a check node of the lowest degree; connecting a first edge of the non-affiliated variable node to the identified check node; and connecting one or more additional edges of the non-affiliated variable node to check nodes in accordance with a quasi-cyclic constraint associated with a circulant is disclosed. | 02-03-2011 |
20110029837 | Systems and Methods for Phase Dependent Data Detection in Iterative Decoding - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes a first data detection circuit that applies a phase dependent data detection algorithm to a data set such that a first output of the first data detection circuit varies depending upon a phase of the data set presented to the first data detection circuit. A first phase of the data set is presented to the first data detection circuit. The circuits further include a decoder circuit that applies a decoding algorithm to the first output to yield a decoded output, and a phase shift circuit that phase shifts the decoded output such that a second phase of the data set is provided as a phase shifted output. A second detection circuit applies a phase dependent data detection algorithm to the phase shifted output such that a second output of the second data detection circuit varies from the first output at least in part due to a different phase of the data set presented to the second data detection circuit. | 02-03-2011 |
20110029839 | Systems and Methods for Utilizing Circulant Parity in a Data Processing System - Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving a codeword that has at least a first circulant with a plurality of data bits and a first circulant parity bit, a second circulant with a plurality of data bits and a second circulant parity bit, and one or more codeword parity bits. The methods further include decoding the codeword using the one or more codeword parity bits to access the first circulant and the second circulant, performing a first circulant parity check on the first circulant, and performing a second circulant parity check on the second circulant. | 02-03-2011 |
20110058631 | Systems and Methods for Enhanced Flaw Scan in a Data Processing Device - Various embodiments of the present invention provide systems and methods for flaw scan in a data processing system. As one example, a data processing system is disclosed that includes a data detector circuit, a bit sign inverting circuit, and an LDPC decoder circuit. The data detector circuit receives a verification data set that is an invalid LDPC codeword, and applies a data detection algorithm to the verification data set to yield a detected output. The bit sign inverting circuit modifies the sign of one or more elements of a first derivative of the detected output to yield a second derivative of the detected output. The second derivative of the detected output is an expected valid LDPC codeword. The LDPC decoder circuit applies a decoding algorithm to the second derivative of the detected output to yield a decoded output. | 03-10-2011 |
20110060973 | Systems and Methods for Stepped Data Retry in a Storage System - Various embodiments of the present invention provide systems and methods for data processing retries. As an example, a data processing retry circuit is discussed that includes a stepped erasure window register, and an erasure flag set circuit. The stepped erasure window register includes: an erasure flag location, an erasure flag length, and a step size. The erasure flag set circuit is operable to assert a first erasure flag beginning at the erasure flag location and having the erasure flag length at a first time. In addition, the erasure flag set circuit is operable to assert a second erasure flag beginning at the erasure flag location plus the step size, and having the erasure flag length at a second time. | 03-10-2011 |
20110080211 | Systems and Methods for Noise Reduced Data Detection - Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide noise reduced data processing circuits. Such circuits include a selector circuit, a sample set averaging circuit, and a data detection circuit. The selector circuit provides either a new sample set or an averaged sample set as a sample output based on a select control signal. The sample set averaging circuit receives the new sample set and provides the averaged sample set. The averaged sample set is based upon two or more instances of the new sample set. The data detection circuit receives the sample output, and performs a data detection algorithm on the sample output and provides the select control signal and a data output. | 04-07-2011 |
20110161633 | Systems and Methods for Monitoring Out of Order Data Decoding - Various embodiments of the present invention provide systems and methods for monitoring out of order data decoding. For example, a method for monitoring out of order data processing is provided that includes receiving a plurality of data sets that is associated with a plurality of identifiers with each of the plurality of identifiers indicates a respective one of the plurality of data sets; storing each of the plurality of identifiers in a FIFO memory in an order that the corresponding data sets of the plurality of data sets was received; processing the plurality of data sets such that at least one of the plurality of data sets is provided as an output data set; accessing the next available identifier from the FIFO memory; and asserting an out of order signal when the next available identifier is not the same as the identifier associated with the output data set. | 06-30-2011 |
20110164669 | Systems and Methods for Determining Noise Components in a Signal Set - Various embodiments of the present invention provide systems and methods for estimating noise components in a received signal set. For example, one embodiment of the present invention provides a noise estimation circuit that includes a data detector circuit and a noise component calculation circuit. The data detector circuit receives a series of data samples and provides a detected output, and the noise component calculation circuit provides an electronics noise power output and a media noise power output each calculated based at least in part on the detected output and the series of data samples. | 07-07-2011 |
20110167227 | Systems and Methods for Updating Detector Parameters in a Data Processing Circuit - Various embodiments of the present invention provide systems and methods for updating detector parameters in a data processing circuit. For example, a data processing circuit is disclosed that includes a first detector circuit, a second detector circuit, and a calibration circuit. The first detector circuit is operable to receive a first data set and to apply a data detection algorithm to the first data set, and the second detector circuit is operable to receive a second data set and to apply the data detection algorithm to the second data set. The calibration circuit is operable to calculate a data detection parameter based upon a third data set. The data detection parameter is used by the first detector circuit in applying the data detection algorithm to the first data set during a period that the data detection parameter is used by the second detector circuit in applying the data detection algorithm to the second data set. | 07-07-2011 |
20110167246 | Systems and Methods for Data Detection Including Dynamic Scaling - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a channel detector circuit. The channel detector circuit includes a branch metric calculator circuit that is operable to receive a number of violated checks from a preceding stage, and to scale an intrinsic branch metric using a scalar selected based at least in part on the number of violated checks to yield a scaled intrinsic branch metric. | 07-07-2011 |
20110205653 | Systems and Methods for Data Recovery - Various embodiments of the present invention provide systems and methods for identifying a reproducible location on a storage medium. As an example, a circuit is described that include a media defect detector and an anchor fixing circuit. The media defect detector is operable to identify a media defect, and the anchor fixing circuit is operable to identify a location relative to the media defect. The location is reproducible. | 08-25-2011 |
20110209026 | Systems and Methods for Data Recovery Using Enhanced Sync Mark Location - Various embodiments of the present invention provide systems and methods for identifying a reproducible location on a storage medium. As an example, a circuit is discussed that includes a data storage circuit, a pattern comparison circuit, and a threshold comparison circuit. The data storage circuit is operable to store a first set of data samples corresponding to a region of interest. The pattern comparison circuit is operable to compare a subset of the first set of data samples with a subset of a second set of data samples corresponding to the region of interest. The pattern comparison circuit is operable to yield a match value corresponding to a degree of similarity between the first set of data samples with the subset of a second set of data samples. The threshold comparison circuit is operable to indicate an anchor point based at least in part on the magnitude of the match value relative to a threshold value. | 08-25-2011 |
20110258508 | Systems and Methods for Dynamic Scaling in a Data Decoding System - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a decoder circuit and a scalar circuit. The decoder circuit is operable to perform a data decoding algorithm by processing at least one decoder message, and the scalar circuit is operable to multiply the decoder message by a variable scalar value. | 10-20-2011 |
20110264980 | Systems and Methods for Low Density Parity Check Data Decoding - Various embodiments of the present invention provide systems and methods for decoding data. As an example, a data processing circuit is disclosed that includes a multi-tier decoding circuit having a first tier decoding circuit operable to decode portions of an encoded data set exhibiting low row weight, and a second tier decoding circuit operable to decode portions of an encoded data set exhibiting high row weight. | 10-27-2011 |
20110264987 | Systems and Methods for Low Density Parity Check Data Encoding - Various embodiments of the present invention provide systems and methods for encoding data. As an example, a data encoding circuit is disclosed that includes a first stage data encoder circuit and a second stage data encoder circuit. The first stage data encoder circuit is operable to provide a first stage output. The first stage data encoder circuit includes a first vector multiplier circuit operable to receive a data input and to multiply the data input by a first sparse matrix to yield a first interim value. The second stage encoder circuit includes a second vector multiplier circuit operable to multiply the first stage output by a second sparse matrix to yield a second interim value. | 10-27-2011 |
20120033320 | Systems and Methods for Dynamic Scaling in a Read Data Processing System - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a decoder circuit providing a decoded output, and a dynamic scalar calculation circuit that determines a first dynamic scaling value and a second dynamic scaling value based at least in part on the decoded output. A first multiplier circuit multiplies the decoded output by the first dynamic scaling value and provides a first scaled output. A detector circuit receives the first scaled output and provides a detected output. A second multiplier circuit multiplies the detected output by the second dynamic scaling value and provides a second scaled output. | 02-09-2012 |
20120084336 | Systems and Methods for Retry Sync Mark Detection - Various embodiments of the present invention provide systems and methods for sync mark detection. As an example, a sync mark detection circuit is discussed that includes a storage circuit, a plurality of noise predictive filter circuits, and a controller circuit. The storage circuit is operable to store a data input as a stored input. The plurality of noise predictive filters are operable to receive a processing input. At least one of the noise predictive filters is selectably modifiable to either increase the probability of finding a sync mark in the processing input or to maintain a baseline probability of finding the sync mark in the processing input. The controller circuit is operable to determine an operational mode that may be a standard operational mode, a bit flipping mode, or a filter modification mode. | 04-05-2012 |
20120102261 | Systems and Methods for Tiered Non-Volatile Storage - Various embodiments of the present invention provide systems and methods for tiered non-volatile storage. As an example, a multi-tiered non-volatile storage device is disclosed that includes a hard disk storage; a solid state, non-volatile storage that caches a subset of data included on the hard disk storage; and a controller circuit that is operable to control data transfer between the solid state, non-volatile storage and the hard disk storage | 04-26-2012 |
20120106607 | Systems and Methods for Variable Thresholding in a Pattern Detector - Various embodiments of the present invention provide systems and methods for pattern identification. As an example, a pattern detection circuit is discussed that include: a distance calculation circuit operable to calculate a distance value corresponding to a difference between a first pattern and a second pattern; a threshold comparator circuit operable to compare the distance value to a variable threshold value; and a threshold value calculation circuit. The threshold value calculation circuit is operable to modify the variable threshold value based at least in part on the distance value. | 05-03-2012 |
20120226958 | METHOD FOR DETECTING SHORT BURST ERRORS IN LDPC SYSTEM - The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gat is operable for receiving the first signal vial the first signal input, receiving the second signal via the second signal input, and generating a logic output gate signal based on the received first signal and the second signal. Furthermore, the device includes a filter, wherein the filter is configured for receiving the logic output gate signal from the logic gate and generates a filter output signal based upon the received logic output gate signal, wherein the filter output signal is operable for flagging errors. | 09-06-2012 |
20120254679 | Systems and Methods for Enhanced Media Defect Detection - Various embodiments of the present invention provide systems and methods for detecting storage medium defects. As one example, a media defect detection system is disclosed that includes a data detector circuit that applies a detection algorithm to the data input and provides a hard output and a soft output. A first circuit combines a first derivative of the hard output with a derivative of the data input to yield a first combined signal. A second circuit combines a second derivative of the hard output with a derivative of the first combined signal to yield a second combined signal. A third circuit combines a derivative of the soft output with the second combined signal and a threshold value to yield a defect signal. | 10-04-2012 |
20120284585 | Systems and Methods for Queue Based Data Detection and Decoding - Various embodiments of the present invention provide systems and methods for variable iteration data processing. | 11-08-2012 |
20120330584 | Systems and Methods for Power Monitoring in a Variable Data Processing System - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a data detector circuit, a data decoder circuit, and a power monitor circuit. The data detector circuit is operable to apply a data detection algorithm to a data input and a decoded output to yield a detected output. The data decoder circuit is operable to apply a data decoding algorithm to the detected output to yield the decoded output. The power monitor circuit is operable to receive a first power status signal from the data detector circuit and a second power status from the data decoder circuit, and to calculate a power usage of a combination of at least the data detector circuit and the data decoder circuit. In such a system, a number of global iterations through a combination of the data decoder circuit and the data detector circuit is variable and both of the first power status signal and the second power status signal varies at least in part as a function of the number of global iterations. | 12-27-2012 |
20130007551 | Stochastic Stream Decoding of Binary LDPC Codes - Various embodiments of the present invention provide systems and methods for stochastic stream decoding of binary LDPC codes. For example, a data decoder circuit is discussed that includes a number of variable nodes and check nodes, with serial connections between the variable nodes and the check nodes. The variable nodes are each operable to perform a real-valued computation of a variable node to check node message for each neighboring check node. The check nodes are operable to perform a real-valued computation of a check node to variable node message for each neighboring variable node. The messages are passed iteratively between the variable nodes and the check nodes. | 01-03-2013 |
20130063835 | Systems and Methods for Generating Predictable Degradation Bias - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit and a bias calculation circuit. The data detector circuit is operable to apply a data detection algorithm to a first data set to yield a first series of soft decision data, and to apply the data detection algorithm to a second data set to yield a second series of soft decision data. The bias calculation circuit operable to calculate a series of bias values based at least in part on the first series of soft decision data and the second series of soft decision data. The series of bias values correspond to a conversion between the first series of soft decision data and the second series of soft decision data. | 03-14-2013 |
20130067247 | Systems and Methods for Governing Power Usage in an Iterative Decoding System - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a data decoder circuit, and a gating circuit. | 03-14-2013 |
20130067297 | Systems and Methods for Non-Binary Decoding Biasing Control - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a biasing circuit, and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a series of symbols to yield a detected output, and the detected output includes a series of soft decision data corresponding to non-binary symbols. The biasing circuit is operable apply a bias to each of the series of soft decision data to yield a series of biased soft decision data. The data decoder circuit is operable to apply a data decoding algorithm to the series of biased soft decision data corresponding to the non-binary symbols. | 03-14-2013 |
20130086438 | Systems and Methods for Efficient Parameter Modification - Various embodiments of the present invention provide systems and methods for data processing. | 04-04-2013 |
20130086439 | Systems and Methods for Parameter Selection Using Reliability Information - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, and a reliability monitor circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output that includes soft data. The reliability monitor circuit is operable to determine a proxy error count based at least in part on the soft data, and to modify a parameter governing an operation of the data processing system based at least in part on the proxy error count. | 04-04-2013 |
20130091400 | Systems and Methods for Parity Shared Data Encoding - Various embodiments of the present invention provide systems and methods for data processing. For example, a low density parity check encoding system is described that includes: a low density parity check encoder circuit, and a combining circuit. The low density parity check encoder circuit is operable to encode a first data set to yield a first low density parity check encoded sub-codeword, and to encode a second data set to yield a second low density parity check encoded sub-codeword. The combining circuit is operable to: generate a composite low density parity check sub-codeword by mathematically combining at least the first low density parity check encoded sub-codeword and the second low density parity check encoded sub-codeword; and combine at least the first low density parity check encoded sub-codeword and the composite low density parity check sub-codeword into an overall codeword. | 04-11-2013 |
20130170063 | Systems and Methods for Channel Quality Determination - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a filter circuit, and a mean squared calculation circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output. The filter circuit is operable to filter the detected output to yield a filtered output. The mean squared calculation circuit is operable to calculate a mean squared error value based at least in part on the data set and the filtered output. A quality indicator is generated at least in part on the mean squared error value. | 07-04-2013 |
20130173932 | Systems and Methods for Decimation Based Over-Current Control - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In some such systems and methods, the operation of one or more calibration circuits is modified when it is determined that too many data processing circuits are active. | 07-04-2013 |
20130198554 | Systems and Methods for Idle Clock Insertion Based Power Control - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. | 08-01-2013 |
20130208376 | Systems and Methods for Parameter Modification During Data Processing Retry - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: a buffer circuit, an equalizer circuit, a data processing circuit, and a retry determination circuit. The buffer is operable to store digital samples as a buffered output, and the equalizer circuit is operable to equalize the buffered output using a first equalization target to yield a first equalized output, and to yield a second equalized output using a second equalization target. The retry determination circuit is operable to select the second equalization target based at least in part on an occurrence of an error. | 08-15-2013 |
20130232155 | Systems and Methods for Out of Order Data Reporting - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for out of order reporting of results from data processing. | 09-05-2013 |
20130235920 | Systems and Methods for Data Processing Including Pre-Equalizer Noise Suppression - The present inventions are related to systems and methods for pre-equalizer noise suppression in a data processing system. As an example, a data processing system is discussed that includes: a sample averaging circuit, a selector circuit, an equalizer circuit, and a mark detector circuit. The sample averaging circuit is operable to average corresponding data samples from at least a first read of a codeword and a second read of the codeword to yield an averaged output based at least in part on a framing signal. The selector circuit is operable to select one of the averaged output and the first read of the codeword as a selected output. The equalizer circuit is operable to equalize the selected output to yield an equalized output, and the mark detector circuit is operable to identify a location mark in the equalized output to yield the framing signal. | 09-12-2013 |
20130246888 | Systems and Methods for Out of Order Processing in a Data Retry - Various embodiments of the present invention provide systems and methods for data processing that includes selectively reporting results out of order or in order. | 09-19-2013 |
20130254616 | Systems and Methods for Variable Rate Coding in a Data Processing System - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate coding in a data processing system. | 09-26-2013 |
20130254623 | Systems and Methods for Variable Redundancy Data Protection - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate coding in a data processing system. | 09-26-2013 |
20130283107 | Systems and Methods for Calibration Coasting in a Data Processing System - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for coasting one or more calibration loops based upon identification of a probability of data inaccuracies. | 10-24-2013 |
20130283113 | Systems and Methods for Back Step Data Decoding - Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include: a data decoder circuit, a decoder log, a mis-correction detection circuit, and a controller circuit. | 10-24-2013 |
20130283114 | Systems and Methods for Locating and Correcting Decoder Mis-Corrections - Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit. | 10-24-2013 |
20130311845 | SYSTEMS AND METHODS FOR NON-BINARY LDPC ENCODING - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding. | 11-21-2013 |
20130311846 | Systems and Methods for Hardware Flexible Low Density Parity Check Conversion - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding. | 11-21-2013 |
20140019695 | Systems and Methods for Rapid Erasure Retry Decoding - The present invention is related to processing data sets, and more specifically to recovering problematic portions of a data set. | 01-16-2014 |
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