Patent application number | Description | Published |
20090051391 | ADJUSTABLE INPUT RECEIVER FOR LOW POWER HIGH SPEED INTERFACE - A pseudo-differential input receiver is disclosed which is configured to support a wide-range of reference voltage Vref and a wide-range frequency interface with no parallel termination are described herein. The pseudo-differential receiver implementations described herein are very efficient in terms of area, power, and performance. A wide-frequency-range Vref-adjustable input receiver is described herein. The receiver can be configured with a Vref-monitoring PMOS helper FET or an enabled stacked PMOS helper FET to enable the receiver to work at Vref=0V like a conventional CMOS receiver. The receiver can also be configured with a Vref-monitoring NMOS helper FET to enable a Vref-based input receiver to work with programmability on bias currents & trip-point at Vref=(0.5˜0.7)Vdd, depending on the ratio of output driver's impedance and parallel on/off-die termination impedance. | 02-26-2009 |
20090116602 | High speed, wide frequency-range, digital phase mixer and methods of operation - The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims. | 05-07-2009 |
20090219769 | I/O CIRCUIT WITH PHASE MIXER FOR SLEW RATE CONTROL - An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal. | 09-03-2009 |
20100194200 | Multiple Supply-Voltage Power-Up/Down Detectors - A multiple supply voltage device includes an input/output (I/O) network operative at a first supply voltage, a core network coupled to the I/O network and operative at a second supply voltage, and a power-on-control (POC) network coupled to the I/O network and the core network. The POC network is configured to transmit a POC signal to the I/O network and includes an adjustable current power up/down detector configured to detect a power state of the core network. The POC network also includes processing circuitry coupled to the adjustable current power up/down detector and configured to process the power state into the POC signal, and one or more feedback circuits. For reducing the leakage current while also improving the power-up/down detection speed, the feedback circuit(s) are coupled to the adjustable current power up/down detector and configured to provide feedback signals to adjust a current capacity of the adjustable current power up/down detector. | 08-05-2010 |
20100271070 | I/O CIRCUIT WITH PHASE MIXER FOR SLEW RATE CONTROL - An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal. | 10-28-2010 |
20110156788 | HIGH SPEED, WIDE FREQUENCY-RANGE, DIGITAL PHASE MIXER AND METHODS OF OPERATION - The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims. | 06-30-2011 |
20120153994 | Methods and Implementation of Low-Power Power-On Control Circuits - Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, an apparatus includes a power detector circuit powered by a first voltage supply. At least one voltage level-shifting device is coupled to a second voltage supply and a test input is provided to the power detector circuit. An optional leakage self-control device may reduce unwanted leakage currents associated with the first supply and the second supply. | 06-21-2012 |
20130021063 | I/O CIRCUIT WITH PHASE MIXER FOR SLEW RATE CONTROL - An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal. | 01-24-2013 |
20130082769 | DIFFERENTIAL PVT/TIMING-SKEW-TOLERANT SELF-CORRECTING CIRCUITS - Systems and methods for circuits that self-correct errors due to variations in fabrication processes, voltages, and temperature (PVT), as well as input timing errors. In an exemplary embodiment, a method for improving output signal quality in a complementary logic circuit is provided. An n-type transistor in the complementary logic circuit is digitally enabled or biased with a first variable power supply. A p-type transistor in the complementary logic circuit is digitally enabled or biased with a second variable power supply, providing a voltage different from that of the first variable power supply, to mitigate a difference in the switching times between the p-type transistor and the n-type transistor. | 04-04-2013 |
20130241608 | HIGH SPEED, WIDE FREQUENCY-RANGE, DIGITAL PHASE MIXER AND METHODS OF OPERATION - The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims. | 09-19-2013 |
20130241613 | I/O CIRCUIT WITH PHASE MIXER FOR SLEW RATE CONTROL - An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal. | 09-19-2013 |
20140025325 | Voltage Level-Shifting - Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, a computer readable tangible medium stores instructions executable by a computer. The instructions may be executable by the computer to determine whether a power detector circuit powered by a first voltage supply has received a test input from at least one voltage level-shifting device coupled to a second voltage supply. | 01-23-2014 |
20140266382 | LOW-POWER INTERFACE AND METHOD OF OPERATION - In a particular embodiment, a method includes modifying an output impedance associated with the input receiver. In response to modifying the output impedance, the method restricts an output voltage at an output node of the input receiver. Particular embodiments of an input receiver circuit are also disclosed. | 09-18-2014 |
20140321227 | FREQUENCY POWER MANAGER - A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode. | 10-30-2014 |
20140334239 | I/O CIRCUIT WITH PHASE MIXER FOR SLEW RATE CONTROL - An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal. | 11-13-2014 |
Patent application number | Description | Published |
20120292688 | HIGHLY INTEGRATED MOS DEVICE AND THE MANUFACTURING METHOD THEREOF - A MOS semiconductor device and the manufacturing method thereof relates to a highly integrated MOS device having a three-dimensional structure. The method of manufacturing the highly integrated MOS device compromises the steps of forming a layer of gate insulator on the semiconductor substrate, planarizing surface after filling a trench with an insulating material, forming a plurality of MOS transistors on the horizontal planes of a semiconductor substrate, forming vertical planes from the semiconductor substrate, and forming a plurality of MOS transistors on the vertical planes. | 11-22-2012 |
20130051113 | PROGRAMMABLE NON-VOLATILE MEMORY - A programmable non-volatile memory including a memory cell includes a transistor acting as an anti-fuse and two diodes for access. The memory cell that can store two bits and includes a transistor acting as an anti-fuse and two diodes for access, wherein the cell transistor includes: the source electrode formed by a metal; the first diode as the source region contact structure; the drain electrode formed by a metal; and the second diode as the drain region contact structure wherein the cell transistor, the oxide layer between the source area and the gate is the first anti-fuse the first storage; the oxide layer between the drain area and the gate is the second anti-fuse the second storage; the two diodes are connected in series to access the two anti-fuses. | 02-28-2013 |
20130077381 | HIGHLY INTEGRATED PROGRAMMABLE NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A highly integrated programmable non-volatile memory and a manufacturing method thereof are provided. More particularly, a memory device including an antifuse and a diode, or a variable resistor and a diode, an operation method thereof, and a manufacturing method of a plurality of memory cells capable of increasing the integration density by utilizing a vertical space are provided. The highly integrated programmable non-volatile memory includes first stepped cells and second stepped cells formed to have different heights. The first stepped cells are formed on a horizontal plane with a high height, and the second stepped cells are formed on a horizontal plane with a low height. | 03-28-2013 |
20130240823 | NON-VOLATILE MEMORY INCLUDING MULTILAYER MEMORY CELLS AND METHOD OF FABRICATING THE SAME - A non-volatile memory and a method of fabricating the same, more particularly, a non-volatile memory in which memory cells each includes an anti-fuse and a diode or a variable resistor and a diode are stacked in a multilayer laminate structure without increasing a horizontal area, to effectively utilize a vertical space and thereby significantly increase a degree of integration so that the memory cells are able to be highly integrated and perform high-speed operation, and a method of fabricating the non-volatile memory. | 09-19-2013 |
20130249017 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - The nonvolatile memory device includes a memory cell having a transistor in which an insulating isolation layer is formed in a channel region. The nonvolatile memory device includes a metal-oxide-semiconductor (MOS) transistor as a basic component. An insulating isolation layer is formed in at least a channel region, and a gate insulating layer includes an insulating layer or a variable resistor and serves as a data storage. A gate includes a metal layer formed in a lower portion thereof. First source and drain regions are lightly doped with a dopant, and second source and drain regions are heavily doped with a dopant. | 09-26-2013 |
Patent application number | Description | Published |
20080278849 | Flow balancer for track misregistration improvement - Disclosed is a hard disk drive that includes at least one disk enclosed by a cover and a disk. A damper is separated from the disk by an air gap about 1.0 mm. The damper and air gap reduce the velocity of the air flow and any vibration associated with the flow of air. | 11-13-2008 |
20080304178 | High-flow rate filter wall design - A hard disk drive that includes a disk, a head, and a filter enclosed by a base plate and a cover plate. The base plate has a filter wall with a fore end and an aft end. The fore end of the filter wall has a tapered surface that extends to an apex. The distal end of the filter wall has a first filter attachment portion separated from a second filter attachment portion by a groove. The second filter attachment portion may be longer than the first filter attachment portion. The filter wall induces a flow of air that inhibits particle attachment to a reverse side of the filter. | 12-11-2008 |
20080304183 | Flexure for head gimbal assembly with narrow gimbal width in a hard disk drive - A hard disk drive and head gimbal assembly including a flexure finger with a micro-actuator split of the flexure supporting a micro-actuator control line, leading to minimized gimbal width for the flexure finger about the micro-actuator assembly including the coupled slider and micro-actuators to reduce mechanical vibrations caused by wind off of a rotating disk surface accessed by the slider. | 12-11-2008 |
20090210206 | Method and for wide track erasure in a hard disk drive - A method and its implementation as a program system are disclosed herein for generating an air flow report based upon a cellular model of the air flow of a hard disk drive including a parameterized component approximated by a component parameter list and a map of the partitioned regions of the hard disk drive. The air flow report is generated based upon the cellular model and a partition/region map. The partition/region map lumps the simulation domain into a small number of regions and then calculates the fluxes across boundaries of the regions. These fluxes accumulate the results of many individual cells, averaging out small variations caused by rounding and/or the convergence properties of the specific cellular approach used. A simulation figure of merit is calculated from the air flow report that further refines the accuracy, effectively removing even more noise. | 08-20-2009 |
20100007987 | METHOD AND APPARATUS FOR DAMPENING AND FILTERING AIR FLOW EFFECTS IN A HARD DISK DRIVE - A hard disk drive is disclosed including at least one air filter mounted on a shroud wall of the base and at least two disk dampers where at least one disk damper covers a fraction of the maximal covering angle configured with the air filter to optimize both the air filter and disk dampening. Methods of manufacturing the hard disk drive are also disclosed. | 01-14-2010 |
20100067147 | METHOD AND APPARATUS FOR A HARD DISK DRIVE INCLUDING A BALANCED MICRO-ACTUATOR - This application discloses a hard disk drive, a head stack assembly, and a head gimbal assembly, each including a micro-actuator hinge configured to position a slider over a rotating disk surface with greater stroke sensitivity while reducing bending perpendicular to the disk surface. The micro-actuator hinge includes at least one micro-actuator, a hinge plate and at least one hinge plate cover, with the micro-actuator including a first region and a second region, each coupled between the hinge plate and the hinge plate cover. | 03-18-2010 |
20100188777 | METHOD AND APPARATUS FOR A DISK DAMPER INCLUDING AN ENCLOSING FLOW CHAMBER WALL FOR A HARD DISK DRIVE - A hard disk drive with a disk base including a disk wall with a first intake, a second intake off of the first intake, an outlet and an air filter configured to receive a first airflow from the first intake and suction from a second airflow from the second intake creating negative pressure at a trapping surface of the air filter away from the outlet. At least one disk rotates to create a rotating disk surface generating airflow configured to enter the first intake to create the first airflow. A disk damper includes an enclosing wall neighboring the air filter to create a flow chamber providing a third airflow through the outlet formed of the first air flow crossing the trapping surface and the second air flow. A disk cover mounts on the disk base to encapsulate the air chamber. The disk base and disk damper are disclosed. | 07-29-2010 |
20120087038 | PARTIAL RIBS IN DISK BASE TO STIFFEN A HARD DISK DRIVE - A hard disk drive and a disk base are disclosed with the disk base including a first face configured to form a disk cavity for the spindle motor, disk(s) and a voice coil motor and a second face configured to couple with a controller Printed Circuit Board (PCB) including at least one integrated circuit. Both faces are include a hub for mounting the spindle motor and surrounded by an outer wall. The first face and/or the second face include at least one partial rib extending from the hub or the outer wall partway to the other. The partial ribs are configured to position the integrated circuit and stiffen the disk base and hard disk drive from mechanical shocks, such as dropping the unit including the hard disk drive. A handheld device is disclosed including at least one of the disclosed hard disk drives with improved reliability to mechanical shocks. | 04-12-2012 |
20120257302 | HARD DISK DRIVE SYSTEM WITH ADSORBENT BREATHER ASSEMBLY PILLAR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base having sidewalls; mounting a magnetic medium for storing data within the sidewalls; mounting an adsorbent breather assembly in direct contact with the base and mounted within the sidewalls without contact therewith; and mounting a cover having an airhole over the base and the sidewalls, in direct contact with the adsorbent breather assembly. | 10-11-2012 |
Patent application number | Description | Published |
20120039406 | CHANNEL DESCRIPTION FEEDBACK IN A COMMUNICATION SYSTEM - In a method for estimating a channel between a transmitter and a receiver in a communication network, a plurality of training signal fields are received at the receiver. Each training signal field includes a plurality of orthogonal frequency division multiplexing (OFDM) tones, and the OFDM tones include at least a plurality of training data tones and one or more pilot tones. Channel estimate data corresponding to the plurality of training data tones and the one or more pilot tones is determined. Channel estimate data corresponding to only a subset of the OFDM tones or data generated using the channel estimate data corresponding to the subset of OFDM tones is transmitted to the transmitter, wherein the subset excludes pilot tones. | 02-16-2012 |
20120087426 | COMPRESSED FEEDBACK FORMAT FOR WLAN - In a method for transmitting channel feedback data from a receiver to a transmitter, channel data for a plurality of orthogonal frequency division multiplexing (OFDM) tones for one or more spatial streams corresponding to a communication channel is determined. A plurality of angle values associated with the one or more spatial streams and one or more OFDM tones is determined. For each of the one or more spatial streams, a per-tone signal to noise ratio (PT-SNR) associated with one or more OFDM tones is determined, and an average signal to noise ratio (avg-SNR) is determined by averaging the signal to noise ratio (SNR) values. A feedback report is generated to include at least i) the plurality of angle values, ii) the PT-SNRs, and iii) the avg-SNR. The feedback report is included in a data unit to be transmitted from the receiver to the transmitter. | 04-12-2012 |
20120201315 | Control Mode PHY for WLAN - A first preamble for a first data unit includes a first long training field and a first signal field modulated according to a first technique. The first data unit is generated according to a first data unit format and includes the first preamble. A second preamble, generated for a second data unit, includes a second signal field and a second long training field. Information in the second signal field is repeated and/or the second long training field is generated so that a duration of the second long training field is longer than a duration of the first long training field. A portion of the second signal field is modulated according to a second technique or a portion of the second long training field is modulated according to the second technique to signal to a receiver that the second data unit is formatted according to a second data unit format. | 08-09-2012 |
20120201316 | Control Mode PHY for WLAN - In a method for generating a physical layer (PHY) data unit for transmission via a communication channel, information bits to be included in the PHY data unit are encoded using a forward error correction (FEC) encoder. The information bits are mapped to a constellation symbols. Additionally, either the information bits are encoded according to a block coding scheme, or the constellation symbols are encoded according to the block coding scheme. Orthogonal frequency division multiplexing (OFDM) symbols are generated to include the constellation symbols and the PHY data unit is generated to include the OFDM symbols. | 08-09-2012 |
20130155967 | WIRELESS COMMUNICATION SYSTEM WITH INTERFERENCE PROVISIONING AND METHOD OF OPERATION THEREOF - A method of operation of a wireless communication system includes: transmitting from a serving eNodeB for conveying a desired input signal to a first user electronics; transmitting from a neighbor eNodeB for conveying the desired input signal to a second user electronics and broadcasting an interference input signal toward the first user electronics; | 06-20-2013 |
20130156139 | WIRELESS COMMUNICATION SYSTEM WITH INTERFERENCE FILTERING AND METHOD OF OPERATION THEREOF - A method of operation of a wireless communication system includes: receiving a desired input signal and an interference input signal; activating a first symbol detector for generating a desired log-likelihood ratio from the desired input signal; activating a second symbol detector for generating an interference log-likelihood ratio from the interference input signal; and jointly decoding a decoded bit by iteratively refining the interference log-likelihood ratio for negating the interference input signal and iteratively refining the desired log-likelihood ratio for enhancing the desired input signal. | 06-20-2013 |
20130287148 | COMMUNICATION SYSTEM WITH ITERATIVE DETECTOR AND DECODER AND METHOD OF OPERATION THEREOF - A method of operation of a communication system includes: receiving an input signal having an input primary codeword and an input parallel codeword; calculating a primary codeword signal by removing a parallel soft information average of the input parallel codeword from the input signal; filtering a residual parallel interference of the input parallel codeword from the primary codeword signal with a primary whitening filter to generate a primary codeword estimation of the input primary codeword; and calculating a primary detected soft information for the primary codeword estimation for communicating with a device. | 10-31-2013 |
20130336372 | COMMUNICATION SYSTEM WITH COMMUNICATION-LAYER MAXIMIZATION MECHANISM AND METHOD OF OPERATION THEREOF - A communication system includes: a receiver resource module configured to determine a receiver-antenna count for characterizing a device; an adjustment module, coupled to the receiver resource module, configured to generate a receiver-capacity profile exceeding a capability associated with the receiver-antenna count with a control unit; and a report module, coupled to the adjustment module, configured to transmit the receiver-capacity profile for communicating a communication content for communicating with the device. | 12-19-2013 |
20140029681 | CONTROL MODE PHY FOR WLAN - In a method for generating a physical layer (PHY) data unit for transmission via a communication channel, information bits to be included in the PHY data unit are encoded using a forward error correction (FEC) encoder. Also, the information bits are encoded according to a block coding scheme, where m copies of each bit are included in the information bits, and one or more bits in the m copies of each bit are flipped. The information bits are mapped to a plurality of constellation symbols, and a plurality of orthogonal frequency division multiplexing (OFDM) symbols are generated to include the plurality of constellation symbols. The PHY data unit is generated to include the plurality of OFDM symbols. | 01-30-2014 |
20140066114 | COMMUNICATION SYSTEM WITH REPEAT-RESPONSE PROCESSING MECHANISM AND METHOD OF OPERATION THEREOF - A communication system includes: a signal identification module configured to receive a repeat response for receiving the repeat response associated with a receiver signal; a signal analysis module, coupled to the signal identification module, configured to determine a serving data, a serving channel estimate, an interference channel estimate, or a combination thereof an interference data from the repeat response with an interference-aware processing mechanism; a combining module, coupled to the signal analysis module, configured to combine the repeat response and the receiver signal based on the serving data, the serving channel estimate, the interference channel estimate, the interference data, or a combination thereof; and a decoding module, coupled to the combining module, configured to generate a replication data based on combining the repeat response and the receiver signal based on the serving data, the serving channel estimate, the interference channel estimate, the interference data, or a combination thereof for communicating with a device. | 03-06-2014 |
20140364064 | COMPUTING SYSTEM WITH COORDINATION MECHANISM AND METHOD OF OPERATION THEREOF - A computing system includes: an inter-device interface configured to communicate a coordination report for representing a receiver signal associated with an interference-aware receiver capable of recognizing an interference signal from an interference node device and included in the receiver signal; a communication unit, coupled to the inter-device interface, configured to: generate a rate coordination profile based on the coordination report for coordinating the interference signal with the interference node device, and generate a beam-forming mechanism based on the rate coordination profile for communicating a serving signal coordinated with the interference signal | 12-11-2014 |
20140369446 | COMPUTING SYSTEM WITH DECODING SEQUENCE MECHANISM AND METHOD OF OPERATION THEREOF - A computing system includes: an inter-device interface configured to receive a receiver signal for representing a serving signal and an interference signal; a communication unit, coupled to the inter-device interface, configured to: dynamically generate a decoding target for decoding of the receiver signal, and decode the receiver signal based on the decoding target for decoding the receiver signal for the serving signal or the interference signal with an interference-aware receiver according to the decoding target. | 12-18-2014 |
20140372835 | COMPUTING SYSTEM WITH DECODING ADJUSTMENT MECHANISM AND METHOD OF OPERATION THEREOF - A computing system includes: an inter-device interface configured to receive a receiver signal for representing a serving signal; a communication unit, coupled to the inter-device interface, configured to: calculate a decoding result based on decoding the receiver signal, generate a parity portion adjustment for adjusting the decoding result, generate a systematic portion adjustment for adjusting the decoding result, and apply the parity portion adjustment and the systematic portion adjustment to the decoding result for determining the serving signal from the receiver signal. | 12-18-2014 |
20150049827 | COMPUTING SYSTEM WITH PRE-CODING MECHANISM AND METHOD OF OPERATION THEREOF - A computing system includes: an inter-device interface configured to determine receiver description for representing a receiver signal corresponding to serving signal contemporaneous with an interference signal from an interference source at an interference-aware receiver; a communication unit, coupled to the inter-device interface, configured to: generate a pre-coding candidate set based on the receiver description for adjusting the serving signal or a subsequent instance thereof, determine a sum-rate condition for representing the serving signal along with the interference signal, and generate a pre-coding adjustment maximizing the sum-rate condition from the pre-coding candidate set for communicating the serving signal or a subsequent instance thereof. | 02-19-2015 |
20150079918 | COMPUTING SYSTEM WITH INTERFERENCE CANCELLATION MECHANISM AND METHOD OF OPERATION THEREOF - A computing system includes: a communication unit configured to determine an interfering interface based on a device location for locating an interference-aware receiver for processing a receiver signal including an interference signal described by the interfering interface; and an inter-device interface, coupled with the communication unit, configured to communicate the interfering interface for communicating the interfering interface to the interference-aware receiver for processing the interference signal or a further instance thereof. | 03-19-2015 |
Patent application number | Description | Published |
20140055891 | INTEGRATED CIRCUIT - An integrated circuit includes an internal power line, a no-connection (NC) pad, and a switch configured to electrically connect the internal power line with the NC pad to supply a first external voltage to the internal power line through the NC pad in response to a control signal. | 02-27-2014 |
20140056084 | INTEGRATED CIRCUIT AND MEMORY DEVICE - An integrated circuit includes a plurality of internal circuits, an e-fuse array circuit configured to store a data used by the internal circuits, and a fuse circuit configured to store a trimming data to set the e-fuse array circuit. | 02-27-2014 |
20140126317 | E-FUSE ARRAY CIRCUIT - An e-fuse array circuit includes a high voltage pumping unit configured to generate a high voltage by pumping a power source voltage, a negative voltage pumping unit configured to generate a negative voltage by pumping a ground voltage, a program/read line supplied with the high voltage when a program operation is activated, a read voltage, which is lower than the high voltage, when a read operation is activated, or the negative voltage when deactivated, a row line supplied with the ground voltage when the row line is activated or the negative voltage when the row line is deactivated, an e-fuse device supplied with voltage of the program/read line, a switch device controlled by the row line and configured to electrically connect the e-fuse device with a column line, and a column circuit configured to supply the negative voltage to the column line when the column line is activated. | 05-08-2014 |
20140126318 | INTEGRATED CIRCUIT INCLUDING E-FUSE ARRAY CIRCUIT - An integrated circuit includes a high voltage generator generating a high voltage, a negative voltage generator generating a negative voltage, a divided voltage generator generating a divided voltage by dividing the power source voltage and supplying it to a read voltage terminal, a first power gate supplying the high voltage or the divided voltage to a program voltage terminal, a second power gate supplying the negative voltage or the ground voltage to a deactivation voltage terminal, a third power gate supplying the ground voltage or the divided voltage to an activation voltage terminal, and an e-fuse array circuit operating using voltage of the program voltage terminal as a program voltage, voltage of the divided voltage terminal as a read voltage, voltage of the activation voltage terminal as an activation voltage, and voltage of the deactivation voltage terminal as a deactivation voltage. | 05-08-2014 |
Patent application number | Description | Published |
20110243142 | INGRESS AND EGRESS SWITCH WHICH DETERMINES SERVICES RELATED TO AN INCOMING PACKET - Virtual machine environments are provided in the switches that form a network, with the virtual machines executing network services previously performed by dedicated appliances. The virtual machines can be executed on a single multi-core processor in combination with normal switch functions or on dedicated services processor boards. Packet processors analyze incoming packets and add a services tag containing services entries to any packets. Each switch reviews the services tag and performs any network services resident on that switch. This allows services to be deployed at the optimal locations in the network. The network services may be deployed by use of drag and drop operations. A topology view is presented, along with network services that may be deployed. Services may be selected and dragged to a single switch or multiple switches. The management tool deploys the network services software, with virtual machines being instantiated on the switches as needed. | 10-06-2011 |
20110243143 | SWITCH WITH PACKET SERVICES PROCESSING - Virtual machine environments are provided in the switches that form a network, with the virtual machines executing network services previously performed by dedicated appliances. The virtual machines can be executed on a single multi-core processor in combination with normal switch functions or on dedicated services processor boards. Packet processors analyze incoming packets and add a services tag containing services entries to any packets. Each switch reviews the services tag and performs any network services resident on that switch. This allows services to be deployed at the optimal locations in the network. The network services may be deployed by use of drag and drop operations. A topology view is presented, along with network services that may be deployed. Services may be selected and dragged to a single switch or multiple switches. The management tool deploys the network services software, with virtual machines being instantiated on the switches as needed. | 10-06-2011 |
20110243144 | NETWORK ARCHITECTURE WITH DISTRIBUTION OF PACKET SERVICES TO VARIOUS SWITCHES - Virtual machine environments are provided in the switches that form a network, with the virtual machines executing network services previously performed by dedicated appliances. The virtual machines can be executed on a single multi-core processor in combination with normal switch functions or on dedicated services processor boards. Packet processors analyze incoming packets and add a services tag containing services entries to any packets. Each switch reviews the services tag and performs any network services resident on that switch. This allows services to be deployed at the optimal locations in the network. The network services may be deployed by use of drag and drop operations. A topology view is presented, along with network services that may be deployed. Services may be selected and dragged to a single switch or multiple switches. The management tool deploys the network services software, with virtual machines being instantiated on the switches as needed. | 10-06-2011 |
20110246899 | SIMPLIFIED DISTRIBUTION OF SOFTWARE TO NETWORKED DEVICES - Virtual machine environments are provided in the switches that form a network, with the virtual machines executing network services previously performed by dedicated appliances. The virtual machines can be executed on a single multi-core processor in combination with normal switch functions or on dedicated services processor boards. Packet processors analyze incoming packets and add a services tag containing services entries to any packets. Each switch reviews the services tag and performs any network services resident on that switch. This allows services to be deployed at the optimal locations in the network. The network services may be deployed by use of drag and drop operations. A topology view is presented, along with network services that may be deployed. Services may be selected and dragged to a single switch or multiple switches. The management tool deploys the network services software, with virtual machines being instantiated on the switches as needed. | 10-06-2011 |
20140056310 | Switch With Network Services Packet Processing - Virtual machine environments are provided in the switches that form a network, with the virtual machines executing network services previously performed by dedicated appliances. The virtual machines can be executed on a single multi-core processor in combination with normal switch functions or on dedicated services processor boards. Packet processors analyze incoming packets and add a services tag containing services entries to any packets. Each switch reviews the services tag and performs any network services resident on that switch. This allows services to be deployed at the optimal locations in the network. The network services may be deployed by use of drag and drop operations. A topology view is presented, along with network services that may be deployed. Services may be selected and dragged to a single switch or multiple switches. The management tool deploys the network services software, with virtual machines being instantiated on the switches as needed. | 02-27-2014 |
Patent application number | Description | Published |
20090145645 | Interconnection element with posts formed by plating - An interconnection element is provided for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon. The interconnection element includes a dielectric element having a major surface. A plated metal layer including a plurality of exposed metal posts can project outwardly beyond the major surface of the dielectric element. Some of the metal posts can be electrically insulated from each other by the dielectric element. The interconnection element typically includes a plurality of terminals in conductive communication with the metal posts. The terminals can be connected through the dielectric element to the metal posts. The posts may be defined by plating a metal onto exposed co-planar surfaces of a mandrel and interior surfaces of openings in a mandrel, after which the mandrel can be removed. | 06-11-2009 |
20090146303 | Flip Chip Interconnection with double post - A packaged microelectronic assembly includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. Each of the first posts has a width in a direction of the front surface and a height extending from the front surface, wherein the height is at least half of the width. There is also a substrate having a top surface and a plurality of second solid metal posts extending from the top surface and joined to the first solid metal posts. | 06-11-2009 |
20090148594 | Interconnection element with plated posts formed on mandrel - An interconnection element can be formed by plating a metal layer within holes in an essentially non-metallic layer of a mandrel, wherein posts can be plated onto a metal layer exposed within the holes, e.g., a metal layer covering the holes in the non-metallic layer. The tips of the posts can be formed adjacent to ends or bottoms of the blind holes. Terminals can be formed in conductive communication with the conductive posts. The terminals can be connected through a dielectric layer to the conductive posts. At least a portion of the mandrel can then be removed from at least ends of the holes. In this way, the tips of the conductive posts can become raised above a major surface of the interconnection element such that at least the tips of the posts project beyond the major surface. | 06-11-2009 |
20110074027 | FLIP CHIP INTERCONNECTION WITH DOUBLE POST - A microelectronic assembly includes a substrate having a first surface, a plurality of first conductive pads exposed thereon, and a plurality of first metal posts. Each metal post defines a base having an outer periphery and is connected to one of the conductive pads. Each metal post extends along a side wall from the base to ends remote from the conductive pad. The assembly further includes a dielectric material layer having a plurality of openings and extending along the first surface of the substrate. The first metal posts project through the openings such that the dielectric material layer contacts at least the outside peripheries thereof. Fusible metal masses contact the ends of some of first metal posts and extend along side walls towards the outer surface of the dielectric material layer. A microelectronic element is carried on the substrate and is electronically can be connected the conductive pads. | 03-31-2011 |
20130286619 | INTERCONNECTION ELEMENT WITH POSTS FORMED BY PLATING - An interconnection element is provided for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon. The interconnection element includes a dielectric element having a major surface. A plated metal layer including a plurality of exposed metal posts can project outwardly beyond the major surface of the dielectric element. Some of the metal posts can be electrically insulated from each other by the dielectric element. The interconnection element typically includes a plurality of terminals in conductive communication with the metal posts. The terminals can be connected through the dielectric element to the metal posts. The posts may be defined by plating a metal onto exposed co-planar surfaces of a mandrel and interior surfaces of openings in a mandrel, after which the mandrel can be removed. | 10-31-2013 |
20150054153 | FLIP CHIP INTERCONNECTION WITH DOUBLE POST - A method of assembling a packaged microelectronic element is disclosed that includes the steps of providing a microelectronic element having a plurality of conductive posts extending away from a first surface of a microelectronic element, the posts having top surfaces and edge surfaces extending abruptly away from the top surfaces, and a fusible metal cap attached to an end of each of the plurality of posts; at least substantially aligning the posts of the microelectronic element with a plurality of conductive posts extending from a first surface of a substrate, the posts of the substrate having top surfaces and edge surfaces extending abruptly away from the top surfaces; and joining the posts of the microelectronic element with the posts of the substrate. | 02-26-2015 |
Patent application number | Description | Published |
20100259964 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells. | 10-14-2010 |
20110122687 | TECHNIQUES FOR REDUCING DISTURBANCE IN A SEMICONDUCTOR DEVICE - Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment. | 05-26-2011 |
20120218847 | TECHNIQUES FOR REDUCING DISTURBANCE IN A SEMICONDUCTOR MEMORY DEVICE - Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment. | 08-30-2012 |
20140056090 | TECHNIQUES FOR REDUCING DISTURBANCE IN A SEMICONDUCTOR MEMORY DEVICE - Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment. | 02-27-2014 |
20140291763 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells. | 10-02-2014 |
20140307512 | TECHNIQUES FOR REDUCING DISTURBANCE IN A SEMICONDUCTOR MEMORY DEVICE - Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment. | 10-16-2014 |
20150085586 | MEMORY DEVICE AND METHOD OF OPERATION OF SUCH A MEMORY DEVICE - A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells. | 03-26-2015 |
Patent application number | Description | Published |
20120187430 | Packaging Photon Building Blocks Having Only Top Side Connections in a Molded Interconnect Structure - Standardized photon building blocks are packaged in molded interconnect structures to form a variety of LED array products. No electrical conductors pass between the top and bottom surfaces of the substrate upon which LED dies are mounted. Microdots of highly reflective material are jetted onto the top surface. Landing pads on the top surface of the substrate are attached to contact pads disposed on the underside of a lip of the interconnect structure. In a solder reflow process, the photon building blocks self-align within the interconnect structure. Conductors in the interconnect structure are electrically coupled to the LED dies in the photon building blocks through the contact pads and landing pads. Compression molding is used to form lenses over the LED dies and leaves a flash layer of silicone covering the landing pads. The flash layer laterally above the landing pads is removed by blasting particles at the flash layer. | 07-26-2012 |
20130134459 | Micro-Bead Blasting Process for Removing a Silicone Flash Layer - Using compression molding to form lenses over LED arrays on a metal core printed circuit board leaves a flash layer of silicone covering the contact pads that are later required to connect the arrays to power. A method for removing the flash layer involves blasting particles of sodium bicarbonate at the flash layer. A nozzle is positioned within thirty millimeters of the top surface of the flash layer. The stream of air that exits from the nozzle is directed towards the top surface at an angle between five and thirty degrees away from normal to the top surface. The particles of sodium bicarbonate are added to the stream of air and then collide into the top surface of the silicone flash layer until the flash layer laterally above the contact pads is removed. The edge of silicone around the cleaned contact pad thereafter contains a trace amount of sodium bicarbonate. | 05-30-2013 |
20130337592 | MICRO-BEAD BLASTING PROCESS FOR REMOVING A SILICONE FLASH LAYER - Using compression molding to form lenses over LED arrays on a metal core printed circuit board leaves a flash layer of silicone covering the contact pads that are later required to connect the arrays to power. A method for removing the flash layer involves blasting particles of sodium bicarbonate at the flash layer. A nozzle is positioned within thirty millimeters of the top surface of the flash layer. The stream of air that exits from the nozzle is directed towards the top surface at an angle between five and thirty degrees away from normal to the top surface. The particles of sodium bicarbonate are added to the stream of air and then collide into the top surface of the silicone flash layer until the flash layer laterally above the contact pads is removed. The edge of silicone around the cleaned contact pad thereafter contains a trace amount of sodium bicarbonate. | 12-19-2013 |
20140048832 | Micro-Bead Blasting Process for Removing a Silicone Flash Layer - Using compression molding to form lenses over LED arrays on a metal core printed circuit board leaves a flash layer of silicone covering the contact pads that are later required to connect the arrays to power. A method for removing the flash layer involves blasting particles of sodium bicarbonate at the flash layer. A nozzle is positioned within thirty millimeters of the top surface of the flash layer. The stream of air that exits from the nozzle is directed towards the top surface at an angle between five and thirty degrees away from normal to the top surface. The particles of sodium bicarbonate are added to the stream of air and then collide into the top surface of the silicone flash layer until the flash layer laterally above the contact pads is removed. The edge of silicone around the cleaned contact pad thereafter contains a trace amount of sodium bicarbonate. | 02-20-2014 |
20140077235 | Substrate Free LED Package - A method of fabricating a substrate free light emitting diode (LED), includes arranging LED dies on a tape to form an LED wafer assembly, molding an encapsulation structure over at least one of the LED dies on a first side of the LED wafer assembly, removing the tape, forming a dielectric layer on a second side of the LED wafer assembly, forming an oversized contact region on the dielectric layer to form a virtual LED wafer assembly, and singulating the virtual LED wafer assembly into predetermined regions including at least one LED. The tape can be a carrier tape or a saw tape. Several LED dies can also be electrically coupled before the virtual LED wafer assembly is singulated into predetermined regions including at the electrically coupled LED dies. | 03-20-2014 |
20140131747 | Packaging Photon Building Blocks Having Only Top Side Connections In A Molded Interconnect Structure - Standardized photon building blocks are packaged in molded interconnect structures to form a variety of LED array products. No electrical conductors pass between the top and bottom surfaces of the substrate upon which LED dies are mounted. Microdots of highly reflective material are jetted onto the top surface. Landing pads on the top surface of the substrate are attached to contact pads disposed on the underside of a lip of the interconnect structure. In a solder reflow process, the photon building blocks self-align within the interconnect structure. Conductors in the interconnect structure are electrically coupled to the LED dies in the photon building blocks through the contact pads and landing pads. Compression molding is used to form lenses over the LED dies and leaves a flash layer of silicone covering the landing pads. The flash layer laterally above the landing pads is removed by blasting particles at the flash layer. | 05-15-2014 |
20140197430 | SUBSTRATE FREE LED PACKAGE - A method of fabricating a substrate free light emitting diode (LED), includes arranging LED dies on a tape to form an LED wafer assembly, molding an encapsulation structure over at least one of the LED dies on a first side of the LED wafer assembly, removing the tape, forming a dielectric layer on a second side of the LED wafer assembly, forming an oversized contact region on the dielectric layer to form a virtual LED wafer assembly, and singulating the virtual LED wafer assembly into predetermined regions including at least one LED. The tape can be a carrier tape or a saw tape. Several LED dies can also be electrically coupled before the virtual LED wafer assembly is singulated into predetermined regions including at the electrically coupled LED dies. | 07-17-2014 |
Patent application number | Description | Published |
20100063114 | INHIBITORS OF PROTEIN PRENYLTRANSFERASES - The present invention is directed to novel compounds. These compounds can be useful in inhibiting the activity of GGTase I. The compounds can also be used as anti-cancer therapeutics including as part of methods for treating cancer, in assays, and in kits. | 03-11-2010 |
20110178138 | INHIBITORS OF PROTEIN PRENYLTRANSFERASES - The present invention is directed to novel compounds. These compounds can be useful in inhibiting the activity of protein prenyltransferases including GGTase I and/or RabGGTase. The compounds can also be used as anti-cancer therapeutics including as part of methods for treating cancer, in assays, and in kits. | 07-21-2011 |
20130102639 | INHIBITORS OF PROTEIN PRENYLTRANSFERASES - The present invention is directed to novel compounds. These compounds can be useful in inhibiting the activity of protein prenyltransferases including GGTase I and/or RabGGTase. The compounds can also be used as anti-cancer therapeutics including as part of methods for treating cancer, in assays, and in kits. | 04-25-2013 |
20130143916 | COMPOUND LIBRARIES MADE THROUGH PHOSPHINE-CATALYZED ANNULATION/TEBBE/DIELS-ALDER REACTIONS - A method for producing libraries of structurally and stereochemically diverse molecules that can be screened for biological or chemical activity. A library of 91 heterocyclic compounds composed of 16 distinct scaffolds was synthesized through a sequence of phosphine-catalyzed ring-forming reactions, Tebbe reactions, Diels-Alder reactions, and, in some cases, hydrolysis to illustrate the methods. Three compounds inhibiting migration of human breast cancer cells are identified from the library. | 06-06-2013 |
20130289073 | CHEMICAL INHIBITORS OF CHOLESTEROL BIOSYNTHESIS AND VENOUS ANGIOGENESIS - This invention relates, e.g., to a compound, aplexone, and pharmaceutically acceptable salts and solvates, and functional variants, thereof. Methods of using the compounds and pharmaceutical compositions comprising them, e.g. to inhibit angiogenesis and to reduce cellular cholesterol levels, are also included. | 10-31-2013 |
20130310417 | Small Molecules For Endothelial Cell Activation - The present invention provides small molecules for endothelial cell activation and compositions thereof and methods of making and using the same. | 11-21-2013 |
20140341979 | NANODRUG TARGETING PROTEIN GERANYLGERANYLATION - The present invention relates, for example, to a liposome, which can be a basic liposome, a transferrin-conjugated liposome, or a pH-sensitive liposome, which encapsulates a compound that specifically inhibits the activity of a protein prenyltransferase, such as a RabGGTase and/or a GGTase I. The liposomes can be used as anti-cancer therapeutics including as part of methods for treating cancer, in assays, and in kits. | 11-20-2014 |
Patent application number | Description | Published |
20090035446 | Solid Solution Perforator Containing Drug Particle and/or Drug-Adsorbed Particles - A solid drug solution perforator containing drug particles and/or drug-adsorbed or loaded particles with an associated drug reservoir (SSPP system) are provided for delivering therapeutic, prophylactic and/or cosmetic compounds, diagnostics, and for nutrient delivery and drug targeting. For drug delivery, the SSPP system includes an active drug ingredient in particulate form or drug adsorbed on the particle surface in a matrix material that dissolves upon contact with a patient's body. In a preferred method of transdermal drug delivery, an SSPP system containing a drug-adsorbed microparticle penetrates into the epidermis or dermis, and the drug is released from the (dissolving) SSPP system perforator and desorbed from the particles. An additional drug is optionally delivered from a patch reservoir through skin pores created by insertion of the perforator Formulation and fabrication procedures for the SSPP and associated reservoir are also provided. An SSPP system can be fabricated with variety of shapes and dimensions. | 02-05-2009 |
20090060986 | Transdermal delivery systems - Disclosed are bupivacaine transdermal delivery systems, and related methods. | 03-05-2009 |
20100010031 | TRANSORAL DOSAGE FORMS COMPRISING SUFENTANIL AND NALOXONE - The invention pertains to methods that include administering to a subject a transoral dosage form comprising a pharmaceutical carrier and sufentanil, and maintaining a mean pH ranging from about 3.5 to about 5.5 during a dosing period after administration of the transoral dosage form as determined using an in vitro donor media test. Related dosage forms are also disclosed. Also disclosed are transoral dosage forms and related methods, wherein a transoral dosage form may comprise: (1) about 5 to about 1000 micrograms of sufentanil; (2) about 50 micrograms to about 100 milligrams of naloxone; and (3) acidifying material in an amount sufficient to provide a mean pH ranging from about 3.5 to about 5.5 during a dosing period after administration of the transoral dosage form as determined using an in vitro donor media test; wherein the dosing period begins no earlier than about 1 minute after administration of the transoral dosage form, and ends no later than about 120 minutes after administration of the transoral dosage form. | 01-14-2010 |
20110121486 | METHOD OF MANUFACTURING SOLID SOLUTION PEFORATOR PATCHES AND USES THEREOF - Methods for fabricating and manufacturing solid solution perforators (SSPs) using sharp metal or glass needles and/or subsequent molding and use are described. The methods entail making microneedles by various precision machining techniques and micromold structures from curable materials. Various designs of patch, cartridge and applicator are described. Also described are methods for adjusting the microneedle mechanical strength using formulation and/or post-drying processes. | 05-26-2011 |
20120193840 | METHOD OF MANUFACTURING SOLID SOLUTION PERFORATOR PATCHES - Provided are methods for fabricating and manufacturing solid solution perforators (SSPs) using sharp metal and subsequent molding and use. The methods entail making microneedles by precision machining techniques and micromold structures from plastic materials. Various designs of patch are described. | 08-02-2012 |
20130273139 | TRANSDERMAL DELIVERY SYSTEMS - Disclosed are bupivacaine transdermal delivery systems, and related methods. | 10-17-2013 |
20130317456 | Transdermal Delivery Systems - Disclosed are bupivacaine transdermal delivery systems, and related methods. | 11-28-2013 |
20140316333 | DISSOLVING SOLID SOLUTION PERFORATOR PATCH FOR MIGRAINE TREATMENT - A dissolving solid solution perforator (SSP) patch for oral cavity administration may include at least one perforator. The at least one perforator may contain a first drug and be configured to pierce an outside layer of an oral cavity for promptly delivering the first drug. The at least one perforator may penetrate an epithelium layer of the oral cavity and to deliver the antimigraine drug into blood vessels in a submucosa layer. | 10-23-2014 |
Patent application number | Description | Published |
20120223621 | MULTIPURPOSE PORTABLE POWER GENERATING SYSTEM - Provided is a system for producing electricity, the system having an object configured to move in at least one of, an upward direction, a downward direction, a left direction, a right direction, an eccentric motion, a straight line, or a circular motion; and at least one piezoelectric element attached to the object, wherein, when the object is moving, the object is configured to apply a pressing force to the at least one piezoelectric element to produce the electricity. | 09-06-2012 |
20120223791 | WEIGHT CONTROL SYSTEM - Provided is a weight control system that can include: an upper plate positioned in a lower portion of the system; at least one of, a first magnet or a first electromagnet, configured to be concentrically engaged with the upper plate; an upper internal core; a coil; and an upper plate housing configured to receive the upper internal core and the coil, the upper plate housing being coupled to at least one of, the first magnet or the first electromagnet, wherein, when power is supplied to the system, an induced current is generated in the upper internal core and the coil to create a first centrifugal magnetic field configured to rotate the upper plate and at least one of, the first magnet or the first electromagnet. | 09-06-2012 |
Patent application number | Description | Published |
20140017852 | METHODS FOR FLIP CHIP STACKING - A method for flip chip stacking includes forming a cavity wafer comprising a plurality of cavities and a pair of corner guides, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit, removing the stacked interposer unit from the cavity wafer, and bonding the solder bumps of the stacked interposer unit to an organic substrate such that the stacked interposer unit and the organic substrate form a flip chip. | 01-16-2014 |
20140252599 | SUBSTRATE-LESS INTERPOSER TECHNOLOGY FOR A STACKED SILICON INTERCONNECT TECHNOLOGY (SSIT) PRODUCT - A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, includes: a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer; and a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to the plurality of metal segments in the bottom most layer. | 09-11-2014 |
20140262440 | MULTI-LAYER CORE ORGANIC PACKAGE SUBSTRATE - A multi-layer core organic package substrate includes: a multi-layer core comprising at least two organic core layers, wherein two of the at least two organic core layers are separated by a core metal layer; a first plurality of build-up layers formed on top of the multi-core layer; and a second plurality of build-up layers formed below the multi-core layer. | 09-18-2014 |
Patent application number | Description | Published |
20110189964 | METHOD AND APPARATUS FOR PROVIDING IMPEDANCE MATCHING FOR HIGH-FREQUENCY SIGNAL TRANSMITTER - In accordance with another representative embodiment, a high-frequency signal transmitter a power amplifier configured to supply a high-frequency signal; an antenna configured to transmit the high-frequency signal; a transmission line configured to transfer the high-frequency signal from the power amplifier to the antenna; and an impedance matching circuit connected to the transmission line. The high-frequency signal transmitter also comprises a mismatch detector. The mismatch detector is configured to designate a comparatively poor linearity region and a comparatively good linearity region by dividing a Smith chart into the two regions based on Adjacent Channel Power Ratio (ACPR) contours drawn on the Smith chart at a point on the transmission line where the impedance matching circuit is connected, to measure a time-dependent reflection coefficient of the high-frequency signal transmitter in terms of a phase and a magnitude, to determine whether the reflection coefficient is located in the comparatively poor linearity region or the comparatively good linearity region, and based on a result of the determination, to improve the linearity of the high-frequency signal transmitter. | 08-04-2011 |
20110234316 | IMPEDANCE MATCHING CIRCUIT CAPABLE OF EFFICIENTLY ISOLATING PATHS FOR MULTI-BAND POWER AMPLIFIER - In accordance with a representative embodiment, an impedance matching circuit for use at an output stage of a power amplifier is disclosed. The impedance matching circuit comprises: an input port for receiving a frequency band signal; and a plurality of paths, each path being allocated with a principal band signal to be transmitted therethrough and including a path on-off network and a fixed-value impedance matching network. Depending on a type of the received frequency band signal, the path on-off network is configured to activate a selected one of the plurality of paths by rendering an input impedance of the selected path to have a lower absolute magnitude so that the signal is transmitted therethrough, and to deactivate the remaining paths of the plurality of paths by rendering the input impedance thereof to have a higher absolute magnitude so that the signal is not transmitted therethrough. The fixed-value impedance matching network matches a load impedance of the output port of each path to the input impedance thereof, thereby rendering the input impedance thereof to have a prescribed reference value with respect to the principal band signal when said path is activated by the path on-off network. | 09-29-2011 |
20130257545 | POWER AMPLIFIER INCLUDING VARIABLE CAPACITOR CIRCUIT - A power amplifier includes first and second amplification stages. The first amplification stage is configured to amplify a radio frequency (RF) input signal. The second amplification stage includes at least one transistor configured to amplify an output of the first amplification stage, the second amplification stage being configured to have a capacitance between a gate of the at least one transistor and a first power supply voltage. The capacitance automatically varies with amplitude of the output of the first amplification stage. | 10-03-2013 |
20140049322 | POWER AMPLIFIER - A power amplifier comprises a common source amplification stage and a first common gate amplification stage. The common source amplification stage includes a common source transistor for receiving a radio frequency (RF) input signal via a gate. The first common gate amplification stage is connected in cascode between a variable supply voltage source and the common source amplification stage, and amplifies an output of the common source amplification stage. The first common gate amplification stage includes a first common gate transistor, and a first gate bias controller configured to generate a first divided voltage based on a variable supply voltage of the variable supply voltage source, and to supply a first gate bias voltage generated by buffering the first divided voltage to a gate of the first common gate transistor. | 02-20-2014 |
Patent application number | Description | Published |
20080277017 | Degreasing Cloth - A degreasing cloth includes a ground thread woven on a first surface, that forms a plurality of closely-spaced holes, and a plurality of pile threads of a predetermined length extending from the first surface. Each of the pile threads is inserted and bound to the ground thread and comprises a loop. The thickness of the ground thread is substantially thicker than the thickness of the pile thread. The ground thread forms a mesh. The mesh comprises a pattern of hexagonal lattice. The greasing cloth may be formed into various applications including a pot cleaner and a laundry bag. The degreasing cloth goes under tenter process to give strength and roughness. | 11-13-2008 |
20090277059 | Bi-color Illuminated Emblem - A bi-color illuminated emblem includes a metal-look portion having a metal look layer, a substrate layer that supports the metal look layer, and a plurality of illuminating elements. The metal look layer and the substrate layer pass light from the illuminating elements. The illuminating elements emit light within a predetermined emission angle, which is 120 degree. The substrate layer is made of semi-transparent ABS. The substrate layer comprises an outer surface which supports the metal look layer, and an inner surface that faces the illuminating elements and has coarse texture that causes scattering of light. The distance between the inner surface of the substrate layer and the illuminating elements is in a range from 7˜10 mm. The illuminating element comprises an LED and a light guiding element that guides the light from the LED emits throughout and within the predetermined angle. | 11-12-2009 |
20100073946 | Bi-color Illuminated Wheel Emblem - A bi-color illuminated wheel emblem includes a rotating part that rotates together with the wheel, a stationary part that remains stationary when the automobile is moving, a bi-color illuminated display that is attached to the stationary part and an electric power supply. The rotating part comprises a mounting device that mounts the emblem to the wheel and a shaft that holds the stationary part rotatably. The stationary part comprises a hollow shell that is held by the shaft and a weight that is attached to the shell. The bi-color illuminated display comprises a metal look layer, illuminating elements and a light diffusion layer that diffuses light from the illuminating elements. The electric power supply comprises a stator that is attached to the stationary part and a rotor that is attached to the rotating part. | 03-25-2010 |
20110084610 | Bi-color License Plate Frame - A bi-color license plate frame, for surrounding a license plate of a vehicle, comprises a rectangular body comprising an aperture that is adapted to show a license plate, and a wall defining a hollow frame space inside the wall, a plurality of light-emitting elements contained in the frame space, and a controller that is electrically connected to the light-emitting elements and that controls the light intensity of the light-emitting elements according to the braking status of the vehicle. The wall of the rectangular body is translucent to the light of the light-emitting elements, and comprises a light diffusion layer, whereby surface illumination is provided when the light-emitting elements are turned on. Bi-color may include metal look and color emitted by the light-emitting elements, or red or black color of the light-diffusion layer and color emitted by the light-emitting elements. | 04-14-2011 |