Patent application number | Description | Published |
20120236521 | ELECTRONIC DEVICE AND CONNECTION STRUCTURE FOR CIRCUIT BOARD - There is provided an electronic device that includes a housing including six sides at right angles to each other, a first side of the six sides including an opening, a first backplane arranged on a second side so as to oppose to the opening, a second backplane arranged on a third side adjacent to the second side, a circuit board which is inserted toward the first backplane through the opening to be coupled with both of the first backplane and the second backplane with use of a plurality of connectors, the circuit board including a specified corner, and a guide. The guide is configured to shift the circuit board toward the second backplane while the specified corner slides with contacting a portion of the guide which is arranged on a fourth side of the six sides opposed to the third side. | 09-20-2012 |
20130256005 | MOUNTING ADAPTER, PRINTED BOARD, AND MANUFACTURING METHOD THEREOF - There is provided a mounting adapter to be disposed between a socket and an electronic component when the electronic component is mounted with the socket. The mounting adapter includes a base having insulating property, a first electrode provided on a first surface of the base, the first surface facing the electronic component, the first electrode being to be in contact with an electric pad of the electronic component, a second electrode provided on a second surface of the base, the second electrode facing the socket, the second electrode being to be in contact with a conductor of the socket, and a through via that penetrates through the base and electrically connects the first electrode and the second electrode. | 10-03-2013 |
20140154925 | SOCKET AND ELECTRONIC COMPONENT MOUNTING STRUCTURE - A socket includes a plurality of coupling members that each include a first end portion and a second end portion, the coupling members being made of electrically conductive material, wherein a terminal of an electronic component and a terminal of a board are electrically coupled with the first end portion and the second end portion, respectively, so to electrically connect the terminal of the electronic component and the terminal of the board, a holding member that holds the plurality of coupling members in such a manner that the plurality of coupling members are not in contact with each other, the holding member being made form an electrical insulating material, and a sheet member that is in contact with the electronic component and the board in parts between the plurality of coupling members, the sheet member being made from a material which is electrical insulating and thermal diffusive. | 06-05-2014 |
20140349495 | CONNECTOR - A connector includes: a casing; a pair of signal terminals that have respective tip end portions, the pair of signal terminals projecting from the casing, the tip end portions being perpendicularly bent; a ground terminal arranged such that the ground terminal and the pair of signal terminals are arranged in a row, the ground terminal projecting at a position adjacent to the pair of signal terminals; and a shield disposed between the casing and the tip end portions of the pair of signal terminals. | 11-27-2014 |
20150359122 | SOCKET FOR SEMICONDUCTOR COMPONENT, PRINTED CIRCUIT BOARD UNIT, AND INFORMATION PROCESSING APPARATUS - A disclosed socket for a semiconductor component includes a plate-shaped insulator having a first main surface and a second main surface, where a through hole being formed in the insulator, a terminal inserted in the through hole, the terminal having one end configured to be connected to a signal electrode of the semiconductor component and having another end configured to be connected to a signal electrode of a printed circuit board, and a shield buried in the insulator to surround the terminal from sides of the terminal, the shield including a first contact protruding from the first main surface and configured to be connected to a ground electrode of the semiconductor component, and a second contact protruding from the second main surface and configured to be connected to a ground electrode of the printed circuit board. | 12-10-2015 |
Patent application number | Description | Published |
20130044830 | TRANSMISSION SYSTEM - A transmission system has a receiver receiving data and a request signal from a transmitter, and a monitor circuit transmitting a valid acknowledge signal to the transmitter when a received data accumulation amount in the FIFO memory is smaller than a threshold, or transmitting an invalid acknowledge signal to the transmitter when the received data accumulation amount in the FIFO memory is larger than the threshold. The transmitter transmits the request signal which is valid and the data when the acknowledge signal is valid, or stops transmission processing of the data and transmits the request signal which is invalid when the acknowledge signal is invalid, and the receiver performs reception processing of the data when the request signal is valid or stops reception processing of the data when the request signal is invalid. | 02-21-2013 |
20130162309 | RECEIVING CIRCUIT - Disclosed is a receiving circuit which includes: a data selection circuit selecting two input data located while placing in between the center phase of one unit interval of a binary input data; a correction circuit correcting the two input data selected by the data selection circuit; a phase detection circuit detecting a phase at which the level of input data changes as a boundary phase in the one unit interval, based on the two input data corrected by the correction circuit; an arithmetic unit calculating the center phase, based on the boundary phase detected by the phase detection circuit; and data decision circuit determining and outputting the level of one of the two input data, based on the center phase and the boundary phase, the correction circuit implements the correction based on a correction value corresponded to the past data level output by the data decision circuit. | 06-27-2013 |
20130266055 | TRANSMISSION SYSTEM - A transmission system includes: a transmitter configured to transmit a first signal; a receiver configured to receiver a second signal from the transmitter; and a bias circuit configured to regulate a direct current bias level of an input terminal of the receiver, wherein the transmitter includes a first amplitude converter configured to convert the first signal to the second signal having a smaller amplitude than an amplitude of the first signal, wherein the receiver includes a second amplitude converter configured to convert the second signal to a third signal having a larger amplitude than the amplitude of the second signal, and wherein the first amplitude converter includes a first capacitance that restricts an amount of charge to be supplied to the receiver. | 10-10-2013 |
20130328632 | CLOCK DISTRIBUTOR AND ELECTRONIC APPARATUS - A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator. | 12-12-2013 |
20130343471 | SIGNAL TRANSMISSION CIRCUIT, SIGNAL TRANSMISSION SYSTEM, AND SIGNAL TRANSMISSION METHOD - A signal transmission circuit includes a driver circuit that includes complementary inverters, each of the complementary inverters including a plurality of transistor switches, each of the plurality of transistor switches including a pair of transistors, one of the pair of transistors operating in a saturation region and another of the pair of transistors operating in a triode region to cause a certain impedance, and that drives each of the plurality of transistor switches in accordance with complementary signals so as to output complementary voltages to a transmission line; and first voltage sources that supply operating voltages to the driver circuit so as to adjust amplitudes of the complementary voltages output from the driver circuit to the transmission line. | 12-26-2013 |
20140169442 | CLOCK DATA RECOVERY METHOD AND CLOCK DATA RECOVERY CIRCUIT - A clock data recovery method includes: integrating an input data signal over a number of cycles of a sample clock to generate an integrated signal; performing a digital process on the integrated signal to output a first digital signal; interpolating the first digital signal in accordance with phase information to generate interpolation data; outputting phase difference data indicating a difference in phase of the interpolation data from the sample clock; performing a filtering process on the phase difference data to generate the phase information; performing an equalization process on the interpolation data in accordance with output data; and performing a binary decision on results of the equalization process to generate the output data. | 06-19-2014 |
20140192938 | SIGNAL PROCESSING CIRCUIT AND SIGNAL PROCESSING METHOD - A signal processing circuit includes: a delay line configured to output, to a plurality of taps, signals with different delay times obtained by delaying an input signal, respectively; and a plurality of synchronization circuits configured to sample the signals from the plurality of taps in a phase in synchronization with a clock signal, wherein each of the plurality of synchronization circuits samples a sample signal from one of the plurality of taps in different phases and outputs a plurality of output signals. | 07-10-2014 |
20140203852 | JITTER MONITOR - A jitter monitor includes: a voltage generating circuit configured to generate a first voltage that is varied with time at a predetermined inclination; a voltage reducing circuit configured to reduce the first voltage by a predetermined voltage in synchronization with a first clock signal so as to generate a second voltage that is varied with time at the predetermined inclination in synchronization with the first clock signal; and a sampling circuit configured to sample a portion having the predetermined inclination of the second voltage. | 07-24-2014 |
20140210530 | CLOCK RECOVERY CIRCUIT AND CLOCK AND DATA RECOVERY CIRCUIT - A clock recovery circuit includes: a phase comparison circuit to compare a data signal and a recovered clock; a charge pump circuit to output a current based on a phase difference signal; a loop filter to convert the current into a control voltage; an oscillation circuit to generate a first sine-wave clock having a frequency corresponding to the control voltage and a second sine-wave clock having a phase obtained by shifting a phase of the first sine-wave clock by 90 degrees; and a clock selector to select, as the recovered clock, the first sine-wave clock or the second sine-wave clock, a selected clock having a voltage difference between a voltage at a transition of the data signal and a center of an amplitude is larger than a voltage difference between a voltage of a non-selected clock at the time and a center of an amplitude of the non-selected clock. | 07-31-2014 |
20140286469 | RECEPTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A burst mode CDR detects an edge from a data signal superimposed with a clock, and generates a recovered clock by means of a voltage controlled oscillator whose oscillation operation is reset based on a timing when the edge is detected. A phase adjustment unit adjusts the phase of a data signal so as to coincide with the phase of a recovered clock. A PLL-based CDR adjusts the oscillation frequency of the recovered clock by means of the voltage controlled oscillator, based on a phase difference between a data signal whose phase has been adjusted by the phase adjustment unit and a feedback clock from the voltage controlled oscillator. A determination unit determines the value of the data signal at a timing when the signal level of the recovered clock transitions. | 09-25-2014 |
20140376675 | RECEIVER CIRCUIT AND RECEIVING METHOD - A receiver circuit includes: an input ADC configured to convert an input data signal to sample data in accordance with a clock; a boundary phase computation circuit configured to determine the boundary phase of the input data signal based on the sample data; an eye pattern computation circuit configured to compute a maximum amplitude phase of an eye pattern of the input data signal based on the sample data and the boundary phase; and a determination circuit configured to determine a value of the input data signal in the maximum amplitude phase based on the sample data and the maximum amplitude phase. | 12-25-2014 |
20150043695 | RECEPTION CIRCUIT - A reception circuit has: a phase detector that detects a phase code based on a phase of data in relation to a first clock signal; a calibration signal generator that, in a calibration mode, adjusts a frequency of the first clock signal or the data so that the phase code detected by the phase detector changes; a calibrator that, in the calibration mode, stores a difference between the phase code and an ideal value of the detected phase, and that, in a normal operation mode, outputs the ideal value in correspondence with the phase code detected by the phase detector; and a phase adjustor that, in the normal operation mode, adjusts a phase of the first clock signal based on the phase code detected by the phase detector and the ideal value, and that outputs to the phase detector. | 02-12-2015 |
20150061410 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a first wire through which a signal is transmitted; a second wire that is not used for signal transmission; a switch that creates or breaks an electric connection between the first wire and the second wire; and a control circuit that controls the switch according to an potential of the signal, which is transmitted through the first wire, so that part of charge stored in a first wire capacitor of the first wire moves to a second wire capacitor of the second wire and is stored in the second wire capacitor and the charge stored in the second wire capacitor are drawn to the first wire capacitor to charge the first wire capacitor. | 03-05-2015 |
20150067630 | METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT AND PROGRAM - A method for designing a semiconductor integrated circuit includes: determining, by a designing device, a first wiring over which a signal is propagated and a second wiring which is not used for a propagation of the signal among a plurality of wirings of a semiconductor integrated circuit; and determining, by the designing device, the second wiring to be used as a wiring for storing electrical charge for an electrical charge recycling of the first wiring using the most number of the first wiring in a range that satisfies a timing constraint based on an operation rate of the signal propagated over the first wiring and a delay time of the first wiring. | 03-05-2015 |
Patent application number | Description | Published |
20130124913 | MANAGEMENT DEVICE AND MANAGEMENT METHOD - A management device includes a memory and a processor coupled to the memory. The processor executes a process including monitoring an operating state of a target device to be managed as a node of a network to be managed, moving a process executed by the target device to another node on the network, when a sign of failure is detected, as a result of the monitoring, and determining, at activation of the target device, whether there is a process having been moved from the target device to another node, and recalling the moved process from a destination node when there is the process having been moved to the another node. | 05-16-2013 |
20130170397 | MANAGEMENT DEVICE AND MANAGEMENT METHOD - A management device includes a memory and a processor coupled to the memory. The processor executes a process including, searching a network for a node that belongs to a management area to which the management device belongs, and creating management information in which the node searched for at the searching is used as a node that is targeted for management. | 07-04-2013 |
20130262670 | MANAGEMENT SYSTEM, MANAGEMENT APPARATUS AND MANAGEMENT METHOD - A management system includes an application source node that applies for subscription of alive and dead state information to a node to be monitored, a node to be monitored that interconnects with the application source node and makes a request to a node whose routing table includes the node to be monitored for monitoring the node to be monitored and notifying the application source node of a monitoring result when receiving the subscription application, and a monitoring node that monitors the node to be monitored when receiving the request from the node to be monitored and makes a notification to the application source node when a response from the node to be monitored stops. The application source node determines that the node to be monitored stops when communication with the node to be monitored is disconnected and the notification is received from the monitoring node. | 10-03-2013 |
20130262700 | INFORMATION PROCESSING SYSTEM AND VIRTUAL ADDRESS SETTING METHOD - An information processing system includes an information processing apparatus, which includes an arithmetic processing unit and a control device that is connected to the arithmetic processing unit, and includes a management device that manages a virtual address. When a communication abnormality occurs between the management device and the control device, the management device instructs the control device to perform a start via the arithmetic processing unit. When the control device is instructed by the arithmetic processing unit to perform a start, the control device transfers the virtual address stored in a storing unit to the arithmetic processing unit. When the arithmetic processing unit receives the virtual address from the control device, the arithmetic processing unit sets a port included in the arithmetic processing unit to the virtual address. | 10-03-2013 |
20130308442 | MANAGEMENT DEVICE AND MANAGEMENT METHOD - A management device includes a node selecting unit, a replicating unit, and a switching unit. The node selecting unit selects a backup node for a management node, from a plurality of nodes in a network formed from a plurality of networks by a specific rule based on multiple indexes that include at least one of the management range to which the node belongs to, the volume of data, and an operation time. The replicating unit replicates management information to the backup node. The switching unit switches, when the management node stops, the backup node to the management node. | 11-21-2013 |
20140019608 | NETWORK MANAGEMENT APPARATUS AND NETWORK MANAGEMENT METHOD - A network management apparatus includes a first storage unit, a second storage unit, and a controller. The first storage unit stores therein communication groups included in the same subnet and information about communication devices belonging to the respective communication groups in association with each other. The second storage unit stores therein for each of the communication devices a port of a relaying device connected to the communication device as a connection destination port. The controller allows the relaying devices to perform communication between the connection destination ports on the basis of the first storage unit and the second storage unit to allow communication only between the communication devices belonging to the same communication group. | 01-16-2014 |
20140019974 | MIGRATION MANAGEMENT APPARATUS AND MIGRATION MANAGEMENT METHOD - A migration management apparatus includes a first decision unit, a second decision unit, and a migration processing unit. The first decision unit simulates the migration of each virtual machine being a migration target to decide a migration destination. The second decision unit decides a migration mode of the virtual machine whose migration destination has been decided by the first decision unit based on the power status of the virtual machine. The migration processing unit, upon the migration destinations and migration modes of the virtual machines being the migration targets having been decided, migrates the virtual machines to the respective migration destinations decided by the first decision unit in the respective migration modes decided by the second decision unit. | 01-16-2014 |
20140189441 | INFORMATION PROCESSING APPARATUS AND SERVER MANAGEMENT METHOD - An information processing apparatus includes an instruction unit and a calculation unit, and instructs a plurality of physical servers to start to provide or stop providing service. The calculation unit monitors the operating status of equipment that is installed in each of a plurality of chassis each housing one or a plurality of physical servers and that is used for operations of the physical servers. Then, the calculation unit calculates an equipment error probability indicating how likely the physical servers housed in a chassis are to fail to provide service due to an error in the equipment of the chassis. The instruction unit instructs physical servers to start to provide or stop providing the service, based on the equipment error probabilities of the plurality of chassis. | 07-03-2014 |
20140196042 | SERVER DEVICE, LOG TRANSFERRING METHOD, AND LOG TRANSFERRING SYSTEM - A server device includes a virtualization control unit, a storing unit, and a transferring unit. The virtualization control unit operates a virtual machine that is a virtualized computer to control a migration of the virtual machine with another server device. The storing unit stores therein a log, in an associated manner with the virtual machine, that is created by the virtual machine. When the virtual machine is migrated to the other server device, the transferring unit transfers, to the other server device, the log of the virtual machine targeted for a migration stored in the storing unit. | 07-10-2014 |
20140201554 | POWER SOURCE MANAGEMENT DEVICE, POWER SOURCE MANAGEMENT METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - A management server includes a storage unit that stores therein destination physical machine information capable of identifying a physical machine serving as a destination candidate of a certain virtual machine that operates on any one of a plurality of physical machines. The management server includes a control unit that performs the following control. To stop power supply to a first physical machine group performed by a first control unit, the control unit detects. The control unit changes the destination physical machine information such that the destination candidate of the certain virtual machine includes at least a physical machine belonging to a second physical machine group when information capable of identifying the physical machine serving as the destination candidate and stored in the storage unit includes no other physical machine than a physical machine belonging to the first physical machine group. | 07-17-2014 |
20140298113 | STORAGE MEDIUM AND INFORMATION PROCESSING APPARATUS AND METHOD WITH FAILURE PREDICTION - A management computer performs a process comprising: a first step and a second step. The first step collects failure-predictive information including information on a plurality of kinds of phenomena related to occurrence of a failure from each of a plurality of computers including an active first computer in a redundant system that are managed by said management computer. The second step calculates, for each individual second computer of one or more second computers of a plurality of second computers associated with said first computer in said redundant system, an evaluation value that indicates the probability of occurrence of a future failure in the individual second computer using said failure-predictive information collected from the individual second computer and said failure-predictive information collected from one or more predetermined computers other than the individual second computer of said plurality of computers. | 10-02-2014 |
20140380079 | OPERATION MANAGEMENT DEVICE, OPERATION MANAGEMENT METHOD, AND RECORDING MEDIUM - An operation management device that comprises: a memory configured to store, for a plurality of nodes that each operate on one computer out of a plurality of computers included in a computer system and for a plurality of nodes capable of moving between the plurality of computers, operation suspension sequence data of the plurality of nodes, and data of operation suspension times needed for operation suspension of each of the plurality of nodes; and a processor configured to execute a procedure, the procedure comprising: from a timing earlier than suspending operation of the computer system and a timing earlier than a total sum of the operation suspension times of the plurality of nodes or greater, suspending operation of the plurality of nodes in an operation suspension sequence indicated by the operation suspension sequence data. | 12-25-2014 |
20150154040 | CONTROLLING APPARATUS, AND CONTROLLING METHOD - A controlling method realized by a computer connected to a plurality of physical devices in which respective virtual machines (VMs) are operated and a process device which is connected to the plurality of physical devices with a plurality of routes and in which a plurality of duplication process VMs for executing a duplication process of duplicating data used by the plurality of VMs to a memory device, the method includes: acquiring loads of the plurality of routes and percentages of completion of the duplication process executed by the plurality of duplication process VMs; and, when incompletion of the duplication process using the selected route within a regulated time is detected, moving any of the duplication process VMs using the selected route to any of the plurality of physical devices from the process device. | 06-04-2015 |
20150163092 | OPERATION MAGNAGEMENT DEVICE AND METHOD - An operation management device includes a processor that executes a procedure including: for plural nodes that includes plural nodes operating as virtual computers on one or more computers and that plural nodes that have a dependency relationship, deriving group information indicating the plural nodes having the dependency relationship on a basis of communication information from when the inter-node communication; and based on location information of the respective plural nodes included in the derived group information, determining operation information indicating that plural nodes included in the group information operate on a single computer, or operation information indicating that the plural nodes included in the group information respectively operate on plural computers, for the plural nodes included in the group information. | 06-11-2015 |
20150381449 | APPARATUS AND METHOD FOR SUPPRESSING A DELAY IN MONITORING COMMUNICATION - A management apparatus acquires state information indicating a state of a monitoring target by communicating with the monitoring target through a first monitoring path at a monitoring timing for monitoring the monitoring target, and detects a use state of the first monitoring path. Upon determining, based on the use state, that a delay is expected to occur in at a next monitoring timing, the management apparatus changes the first monitoring path to a second monitoring path different from the first monitoring path, and communicates with the monitoring target through the changed second monitoring path. | 12-31-2015 |
Patent application number | Description | Published |
20100320546 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration. | 12-23-2010 |
20120171834 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration. | 07-05-2012 |
20130196482 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including performing a first thermal processing a silicon substrate in a first atmosphere and at a first temperature to remove an oxide film above a surface of the silicon substrate, and after the first thermal processing, performing a second thermal processing the silicon substrate in a second atmosphere containing hydrogen and at a second temperature lower than the first temperature to terminate the surface of the silicon substrate with hydrogen. | 08-01-2013 |
20130280897 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration. | 10-24-2013 |
Patent application number | Description | Published |
20080225882 | MULTIPLEXED OPTICAL SIGNAL TRANSMISSION APPARATUS - A transmission apparatus for multiplexing optical signals has a multi-rate signal processing unit that has a plurality of signal processing circuits in advance according to various signal speeds and frame formats and selects a necessary signal processing circuit as necessary. In addition, the transmission apparatus acquires a type code, used to identify the type of the signal of a removable optical module, from the optical module and, from the acquired information, automatically determines the operation mode of the multi-rate signal processing unit, bandwidth allocations according to the signal speeds, and monitoring item contents for different frame formats to eliminate the need for maintenance engineer's work that is otherwise required when a low-speed signal is added. | 09-18-2008 |
20080232818 | INTERFACE BOARD AND OPTICAL TRANSMISSION EQUIPMENT - A circuit capable of processing signals of different signal types is provided for identifying the signal type by the signal type setting from an administrator or by the implementation of the optical module, thereby selecting a signal processor to be used. An OTN frame standardized by ITU is used in a fixed manner independent of the signal type to be accommodated, while a corresponding SDH/SONET frame standardized by ITU is used for signal accommodation. | 09-25-2008 |
20090028548 | Operation and construction method of network using multi-rate interface panel - The present invention provides a network at a low cost with a reduced number of components and simple management among networks anticipated to become more and more complicated, the network being capable of quick pass change upon service addition/change and failure occurrence. Namely, the present invention realizes a network configuration unnecessary for replacement of interface panels upon pass change, by using a multi-rate compatible interface panel capable of freely changing a signal type to be processed, under control of an upper level operation. | 01-29-2009 |
20100226370 | NETWORK SYSTEM - When label switching is performed on a conventional MPLS packet, a bit error may occur in an MPLS label header of the MPLS packet and user data may misdelivered. To avoid such misdelivery of the user data, an HEC function is attached to the MPLS label header. | 09-09-2010 |
20110164622 | OPERATION AND CONSTRUCTION METHOD OF NETWORK USING MULTI-RATE INTERFACE PANEL - An interface unit for processing a first signal and a second signal, the second signal set to different transmission rate from the first signal and/or a different signal type from the first signal, including a plurality of interface panels, each of the plurality of interface panels including: a storage device which stores a first logic circuit data corresponding to the first signal and a second logic circuit data corresponding to the second signal, a configuration function unit which controls to select the first logic circuit data or the second logic circuit data, and a programmable logic circuit which reconfigures the first logic circuit data or the second logic circuit data based on a selection by the configuration function unit. | 07-07-2011 |
20110214008 | NETWORK SYSTEM - A network system having duplicate lines of a primary system and a backup system between a transmitter apparatus and a receiver apparatus is provided. Each of the transmitter apparatus and the receiver apparatus includes an arithmetic operator for conducting a BIP-8 arithmetic operation and a CRC arithmetic operation on an input signal and thereby detecting a bit error. The transmitter apparatus transmits data to both lines. The receiver apparatus includes a switcher. When a bit error is detected in received data of the primary system. the switcher switches control of the primary system and the backup system. Hitless protection switching of a VC path is executed, | 09-01-2011 |
20110216782 | DATA TRANSFER DEVICE AND DATA TRANSFER SYSTEM - A transfer device according to an embodiment transfers blocks generated by dividing a frame into pieces of data and adding a synchronization header each of the pieces of data. The blocks comprise a first, second and third blocks in this order. The transfer device is configured to acquire a first synchronization header in the first block, a second synchronization header in the second block and a third synchronization header in the third block, judge, in a case where a value of the second synchronization header is incorrect, as to whether or not the value of the second synchronization header can be estimated based on the first and the third synchronization headers so that the second block is consistent with the first and third blocks, and correct the second synchronization header into the estimated value. | 09-08-2011 |