Patent application number | Description | Published |
20080197463 | Electronic Component And Method For Manufacturing An Electronic Component - An electronic component has at least two semiconductor devices, a contact clip and a leadframe with a device carrier portion and a plurality of leads. The contact clip extends between the first side of at least two semiconductor devices and at least one lead of the leadframe to electrically connect a load electrode of the at least two semiconductor devices to at least one lead. | 08-21-2008 |
20080224300 | Semiconductor Module With Semiconductor Chips And Method For Producing It - A semiconductor module has at least two semiconductor chips ( | 09-18-2008 |
20080224323 | Semiconductor Module With Semiconductor Chips And Method For Producing It - A semiconductor module ( | 09-18-2008 |
20080230928 | Module comprising a semiconductor chip - A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element. | 09-25-2008 |
20080251859 | Semiconductor Module - A component includes a first semiconductor chip attached to a first carrier and second semiconductor chip attached to a second carrier. The first carrier has a first extension, which forms a first external contact element. The second carrier has a second extension, which forms a second external contact element. The first and the second carriers are arranged in such a way that the first and the second extension point in different directions. | 10-16-2008 |
20080251903 | SEMICONDUCTOR MODULE - A module having a semiconductor chip with a first contact element on a first main surface and a second contact element on a second main surface is disclosed. The semiconductor chip is arranged on a carrier. An insulating layer and a wiring layer cover the second main surface and the carrier. | 10-16-2008 |
20080251912 | Multi-Chip Module - A multi-chip module includes at least one integrated circuit chip that is electrically connected to first external terminals of the multi-chip module and at least one power semiconductor chip that is electrically connected to second external terminals of the multi-chip module. All first external terminals of the multi-chip module are arranged in a contiguous region of an terminal area of the multi-chip module. | 10-16-2008 |
20080296782 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer applied onto the carrier, an adhesive layer applied to the electrically insulating layer. A first semiconductor chip applied to the adhesive layer. | 12-04-2008 |
20090001535 | Semiconductor Module for a Switched-Mode Power Supply and Method for Its Assembly - Semiconductor module for a Switched-Mode Power Supply comprises at least one semiconductor power switch, a control semiconductor chip and a leadframe comprising a die pad and a plurality of leads disposed on one side of the die pad. The die pad comprises at least two mechanically isolated regions wherein the semiconductor power switch is mounted on a first region of the die pad and the control semiconductor chip is mounted on a second region of the die pad. Plastic housing material electrically isolates the first region and the second region of the die pad and electrically isolates the semiconductor power switch from the control semiconductor chip. | 01-01-2009 |
20090001554 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer arranged over the carrier and a first semiconductor chip arranged over the electrically insulating layer, wherein the first semiconductor chip has a first contact element on a first surface and a second contact element on a second surface. | 01-01-2009 |
20090001562 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides a module including a first carrier having a first mounting surface and a second mounting surface, a first semiconductor chip mounted onto the first mounting surface of the first carrier and having a first surface facing away from the first carrier, a first connection element connected to the first surface of the first semiconductor chip, a second semiconductor chip having a first surface facing away from the first carrier, a second connection element connected to the first surface of the second semiconductor chip, and a mold material covering the first connection element and the second connection element only partially. | 01-01-2009 |
20090020861 | SEMICONDUCTOR DEVICE - A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier. | 01-22-2009 |
20090026601 | SEMICONDUCTOR MODULE - A semiconductor module is disclosed. One embodiment provides a first semiconductor chip having a first contact pad on a first main surface and a second contact pad on a second main surface, a first electrically conductive layer applied to the first main surface, a second electrically conductive layer applied to the second main surface, and an electrically insulating material covering the first electrically conductive layer, wherein a surface of the second electrically conductive layer forms an external contact pad and the second electrically conductive layer has a thickness of less than 200 μm. | 01-29-2009 |
20090045446 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device having a first active semiconductor component and a second active semiconductor component, the electrical connections of which are routed out of the semiconductor components in the form of connecting legs is disclosed. In one embodiment, the first semiconductor component is at least partially electrically connected to the second semiconductor component by means of a plug-in connection. The plug-in connection is realized by virtue of the connecting legs of the second semiconductor component engaging in the electrical connections of the first semiconductor component. | 02-19-2009 |
20090108460 | DEVICE INCLUDING A SEMICONDUCTOR CHIP HAVING A PLURALITY OF ELECTRODES - A device, including a semiconductor chip having a plurality of first electrodes is disclosed. A plurality of second electrodes is arranged on a first surface of the semiconductor chip. A first electrically conductive layer is applied over a first section of the first surface and electrically coupled to the first electrodes arranged within the first section. A second electrically conductive layer is applied over the first electrically conductive layer and electrically coupled to the second electrodes arranged within the first section. | 04-30-2009 |
20090108467 | DEVICE WITH A PLURALITY OF SEMICONDUCTOR CHIPS - A device with a plurality of semiconductor chips is disclosed. One embodiment provides a substrate. A first semiconductor chip is mounted over the substrate. A second semiconductor chip is mounted over the first semiconductor chip. A first electrically conducting element electrically couples the second semiconductor chip to the substrate and a mold material covers the first electrically conducting element only partially. | 04-30-2009 |
20090137086 | METHOD FOR MAKING A DEVICE INCLUDING PLACING A SEMICONDUCTOR CHIP ON A SUBSTRATE - A method for making a device is disclosed. One embodiment provides a substrate having a first element protruding from the substrate. A semiconductor chip has a first electrode on a first surface and a second electrode on a second surface opposite to the first surface. The semiconductor chip is placed over the first element of the substrate with the first surface of the semiconductor chip facing the substrate. The second electrode of the semiconductor chip is electrically coupled to the substrate, and the substrate is at least partially removed. | 05-28-2009 |
20090160046 | ELECTRONIC DEVICE AND METHOD - An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer. | 06-25-2009 |
20090174056 | SEMICONDUCTOR MODULE - A semiconductor module is disclosed. One embodiment provides a first semiconductor chip having a first contact pad on a first main surface and a second contact pad on a second main surface, a first electrically conductive layer applied to the first main surface, a second electrically conductive layer applied to the second main surface, and an electrically insulating material covering the first electrically conductive layer, wherein a surface of the second electrically conductive layer forms an external contact pad and the second electrically conductive layer has a thickness of less than 200 μm. | 07-09-2009 |
20090179311 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING THE SAME - A semiconductor component of semiconductor chip size includes a semiconductor chip. The semiconductor chip has a metallic coating that completely covers the side edges, the rear side and the top side, on which surface-mountable external contacts are arranged. One embodiment includes power semiconductor components, wherein the metallic coating connects a rear side electrode to one of the surface-mountable external contacts on the top side of a power semiconductor chip. | 07-16-2009 |
20090189259 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING - An electronic device and method of manufacturing. One embodiment includes attaching a first semiconductor chip to a first metallic clip. The first semiconductor chip is placed over a leadframe after the attachment of the first semiconductor chip to the first metallic clip. | 07-30-2009 |
20090212284 | ELECTRONIC DEVICE AND MANUFACTURING THEREOF - An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads. | 08-27-2009 |
20090230519 | Semiconductor Device - This application relates to a semiconductor device comprising: a carrier comprising a chip island and at least one first external contact element; only one semiconductor chip, wherein the semiconductor chip comprises a first electrode on a first surface and a second electrode on a second surface opposite to the first surface and wherein the first electrode is attached to the chip island; and a metal structure comprising a plate region attached to the second electrode and a connection region attached to the at least one first external contact element, wherein the plate region extends laterally beyond the edges of at least two sides of the second surface of the semiconductor chip. | 09-17-2009 |
20090230535 | SEMICONDUCTOR MODULE - A semiconductor module. In one embodiment, at least two semiconductor chips are placed on a carrier. The at least two semiconductor chips are then covered with a molding material. An exposed portion of the at least two semiconductor chips is provided. A first layer of conductive material is applied over the exposed portion of the at least two semiconductor chips to electrically connect to a contact pad on the exposed portion of the at least two semiconductor chips. The at least two semiconductor chips are singulated. | 09-17-2009 |
20090236749 | ELECTRONIC DEVICE AND MANUFACTURING THEREOF - One aspect is a method including providing a carrier having a first conducting layer, a first insulating layer over the first conducting layer, and at least one through-connection from a first face of the first insulating layer to a second face of the first insulating layer; attaching at least two semiconductor chips to the carrier; applying a second insulating layer over the carrier; opening the second insulating layer until the carrier is exposed; depositing a metal layer over the opened second insulating layer; and separating the at least two semiconductor chips after depositing the metal layer. | 09-24-2009 |
20090261468 | SEMICONDUCTOR MODULE - A semiconductor module. One embodiment provides at least two semiconductor chips placed on a carrier. The at least two semiconductor chips are then covered with a molding material to form a molded body. The molded body is thinned until the at least two semiconductor chips are exposed. Then, the carrier is removed from the at least two semiconductor chips. The at least two semiconductor chips are singulated. | 10-22-2009 |
20090273913 | CIRCUIT ARRANGEMENT HAVING TWO SEMICONDUCTOR SWITCHING ELEMENTS AND ONE FREEWHEELING ELEMENT - One aspect is a circuit arrangement including a first semiconductor switching element, a second semiconductor switching element connected in series with the first semiconductor switching element and a freewheeling element connected in parallel with the second semiconductor switching element. | 11-05-2009 |
20100001291 | ELECTRONIC DEVICE AND MANUFACTURING THEREOF - An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane. | 01-07-2010 |
20100013106 | STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane. | 01-21-2010 |
20100032816 | Electronic Device and Method of Manufacturing Same - This application relates to a semiconductor device, the semiconductor device comprising a metal carrier, an insulating foil partially covering the metal carrier, a first chip attached to the metal carrier over the insulating foil, and a second chip attached to the metal carrier over a region not covered by the insulating foil. | 02-11-2010 |
20100051963 | POWER TRANSISTOR - A power transistor. One embodiment provides a power transistor having a first terminal, a second terminal and a control terminal. A support layer is formed of a first material having a first bandgap. An active region is formed of a second material having a second bandgap wider than the first bandgap, and is disposed on the support layer. The active region is arranged to form part of a current path between the first and second terminal in a forward mode of operation. The active region includes at least one pn-junction. | 03-04-2010 |
20100078783 | DEVICE INCLUDING TWO MOUNTING SURFACES - A device including two mounting surfaces. One embodiment provides a power semiconductor chip and having a first electrode on a first surface and a second electrode on a second surface opposite to the first surface. A first external contact element and a second external contact element, are both electrically coupled to the first electrode of the semiconductor chip. A third external contact element and a fourth external contact element, both electrically coupled to the second electrode of the semiconductor chip. A first mounting surface is provided on which the first and third external contact elements are disposed. A second mounting surface is provided on which the second and fourth external contact elements are disposed. | 04-01-2010 |
20100078784 | DEVICE INCLUDING A POWER SEMICONDUCTOR CHIP - A device including a power semiconductor chip. One embodiment provides a power semiconductor chip having a first electrode on a first surface and a second and a third electrode on a second surface opposite to the first surface. A leadframe includes a carrier and a first lead, the power semiconductor chip placed over the carrier with the first surface of the power semiconductor chip facing the carrier. A metallic layer includes a first surface and a second surface opposite to the first surface. The metallic layer is placed over the second surface of the power semiconductor chip with the first surface of the metallic layer facing the power semiconductor chip. The second surface of the metallic layer and a surface of the first lead lie within a common mounting plane. | 04-01-2010 |
20100264523 | Panel, Semiconductor Device and Method for the Production Thereof - A panel has a baseplate with an upper first metallic layer and a multiplicity of a vertical semiconductor components. The vertical semiconductor components in each case have a first side with a first load electrode and a control electrode and an opposite second side with a second load electrode. The second side of the semiconductor components is in each case mounted on the metallic layer of the baseplate. The semiconductor components are arranged in such a way that edge sides of adjacent semiconductor components are separated from one another. A second metallic layer is arranged in separating regions between the semiconductor components. | 10-21-2010 |
20100276797 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a chip island, a chip attached to the chip island, and encapsulation material deposited on the chip and part of the chip island. The chip island includes a first main face to which the chip is attached opposite a second main face, with the second main face of the chip island defining at least one cavity. | 11-04-2010 |
20100289135 | SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package is disclosed. One embodiment provides at least one semiconductor chip including contact elements on a first surface of the chip. An encapsulation layer covers the semiconductor chip. A metallization layer is applied above the first surface of the chip and the encapsulation layer. The metallization layer includes contact areas connected with the contact elements of the chip. External pins are connected with the contact areas. | 11-18-2010 |
20100295171 | ELECTRONIC DEVICE AND METHOD - An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer. | 11-25-2010 |
20100297810 | Power Semiconductor Device and Method for Its Production - A power semiconductor device and a method for its production. The power semiconductor device has at least one power semiconductor chip, which has on its top side and on its back side large-area electrodes. The electrodes are electrically in connection with external contacts by means of connecting elements, the power semiconductor chip and the connecting elements being embedded in a plastic package. This plastic package has a number of layers of plastic, which are pressed one on top of the other and have plane-parallel upper sides. The connecting elements are arranged on at least one of the plane-parallel upper sides, between the layers of plastic pressed one on top of the other, as a patterned metal layer and are electrically in connection with the external contacts by means of contact vias through at least one of the layers of plastic. | 11-25-2010 |
20110096519 | SEMICONDUCTOR DEVICE - A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier. | 04-28-2011 |
20110097855 | SEMICONDUCTOR DEVICE - A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier. | 04-28-2011 |
20110189821 | SEMICONDUCTOR DEVICE - A semiconductor device and method is disclosed. One embodiment provides a method comprising placing a first semiconductor chip on a carrier. After placing the first semiconductor chip on the carrier, an electrically insulating layer is deposited on the carrier. A second semiconductor chip is placed on the electrically insulating layer. | 08-04-2011 |
20110215460 | STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane. | 09-08-2011 |
20120027928 | ELECTRONIC DEVICE - An electronic device is disclosed. One embodiment provides a metallic body. A first electrically insulating layer is applied over the metallic body and having a thickness of less than 100 μm. A first thermally conductive layer is applied over the first electrically insulating layer and having a thermal conductivity of more than 50 W/(m·K). A second electrically insulating layer is applied over the first thermally conductive layer and having a thickness of less than 100 μm. | 02-02-2012 |
20120061812 | Power Semiconductor Chip Package - A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad. | 03-15-2012 |
20120061835 | DIE STRUCTURE, DIE ARRANGEMENT AND METHOD OF PROCESSING A DIE - A die structure includes a die and a metallization layer disposed over the front side of the die. The metallization layer includes copper. At least a part of the metallization layer has a rough surface profile. The part with the rough surface profile includes a wire bonding region, to which a wire bonding structure is to be bonded. | 03-15-2012 |
20120068186 | Electronic Device - An electronic device includes a carrier, a plurality of pins, and an electronic circuit that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is attached to the carrier and the second semiconductor chip is attached to one of the plurality of pins. | 03-22-2012 |
20120070941 | MODULE WITH SILICON-BASED LAYER - The invention concerns a module comprising a carrier element, a semiconductor device mounted on said carrier element and a silicon-based insulating layer. The silicon-based insulating layer is arranged on the side of the carrier element opposite to the semiconductor device. The invention further concerns a module comprising a semiconductor device, a mold compound at least partly covering the semiconductor device and a silicon-based passivation layer. The silicon-based passivation layer covers at least partly the periphery of the mold compound. | 03-22-2012 |
20120178216 | DEVICE INCLUDING TWO MOUNTING SURFACES - A device including two mounting surfaces. One embodiment provides a power semiconductor chip and having a first electrode on a first surface and a second electrode on a second surface opposite to the first surface. A first external contact element and a second external contact element, are both electrically coupled to the first electrode of the semiconductor chip. A third external contact element and a fourth external contact element, both electrically coupled to the second electrode of the semiconductor chip. A first mounting surface is provided on which the first and third external contact elements are disposed. A second mounting surface is provided on which the second and fourth external contact elements are disposed. | 07-12-2012 |
20120276693 | Module Comprising a Semiconductor Chip - A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element. | 11-01-2012 |
20120286293 | ELECTRONIC DEVICE AND MANUFACTURING THEREOF - An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane. | 11-15-2012 |
20120319109 | ELECTRONIC DEVICE AND MANUFACTURING THEREOF - An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads. | 12-20-2012 |
20130009295 | Semiconductor Device Including a Contact Clip Having Protrusions and Manufacturing Thereof - A semiconductor device includes a leadframe with a die pad and a first lead, a semiconductor chip with a first electrode, and a contact clip with a first contact area and a second contact area. The semiconductor chip is placed over the die pad. The first contact area is placed over the first lead and the second contact area is placed over the first electrode of the semiconductor chip. A plurality of protrusions extends from each of the first and second contact areas and each of the protrusions has a height of at least 5 μm. | 01-10-2013 |
20130027113 | Power Semiconductor Chip Having Two Metal Layers on One Face - A semiconductor chip includes a power transistor circuit with a plurality of active transistor cells. A first load electrode and a control electrode are arranged on a first face of the semiconductor chip, wherein the first load electrode includes a first metal layer. A second load electrode is arranged on a second face of the semiconductor chip. A second metal layer is arranged over the first metal layer, wherein the second metal layer is electrically insulated from the power transistor circuit and the second metal layer is arranged over an area of the power transistor circuit that comprises at least one of the plurality of active transistor cells. | 01-31-2013 |
20130056877 | CHIP-HOUSING MODULE AND A METHOD FOR FORMING A CHIP-HOUSING MODULE - A chip-housing module including a carrier configured to carry one or more chips; the carrier including: a first plurality of openings, wherein each opening of the first plurality of openings is separated by a first pre-determined distance, and is configured to receive a chip connection for providing a voltage lying within a first range of voltage values to a chip; a second plurality of openings, wherein each opening of the second plurality of openings is separated by a second pre-determined distance, and configured to receive a chip connection for providing a voltage lying within a second range of voltage values to a chip; and wherein a pair of openings consisting of one opening of the first plurality of openings and one opening of the second plurality of openings is separated by a distance different from at least one of the first pre-determined distance and the second pre-determined distance, is provided. | 03-07-2013 |
20130062722 | CHIP MODULE AND A METHOD FOR MANUFACTURING A CHIP MODULE - In various embodiments, a chip module may include a first chip; and a leadframe with a first leadframe area and a second leadframe area, wherein the first leadframe area is electrically insulated from the second leadframe area; wherein the first chip is arranged at least partially on the first leadframe area and at least partially on the second leadframe area. | 03-14-2013 |
20130069243 | Chip Module and Method for Fabricating a Chip Module - The chip module includes a semiconductor chip having a first contact element on a first main face and a second contact element on a second main face. The semiconductor chip is arranged on a corner in such a way that the first main face of the semiconductor chip faces the carrier. One or more electrical connectors are connected to the carrier and include end faces located in a plane above a plane of the second main face of the semiconductor chip. | 03-21-2013 |
20130143368 | SEMICONDUCTOR DEVICE - A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier. | 06-06-2013 |
20130146991 | Device Including Two Power Semiconductor Chips and Manufacturing Thereof - A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip. | 06-13-2013 |
20130154123 | Semiconductor Device and Fabrication Method - In various embodiments, a semiconductor device may include: a carrier; a semiconductor chip disposed over a first side of the carrier; a layer stack disposed between the carrier and the semiconductor chip or over a second side of the carrier opposite the semiconductor chip, or both, the layer stack including at least a first electrically insulating layer, the first electrically insulating layer having a laminate having a first electrically insulating matrix material and a first mechanically stabilizing material embedded in the first electrically insulating matrix material. | 06-20-2013 |
20130161801 | Module Including a Discrete Device Mounted on a DCB Substrate - A module includes a DCB substrate and a discrete device mounted on the DCB substrate, wherein the discrete device comprises a leadframe, a semiconductor chip mounted on the leadframe and an encapsulation material covering the semiconductor chip. | 06-27-2013 |
20130200532 | Semiconductor Device Using Diffusion Soldering - A method includes providing a semiconductor chip having a first main surface and a second main surface. A semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. A first layer of solder material is provided between the first main surface and the carrier. A contact clip including a first contact area is placed on the semiconductor chip with the first contact area facing the second main surface of the semiconductor chip. A second layer of solder material is provided between the first contact area and the second main surface. Thereafter, heat is applied to the first and second layers of solder material to form diffusion solder bonds between the carrier, the semiconductor chip and the contact clip. | 08-08-2013 |
20130229777 | CHIP ARRANGEMENTS AND METHODS FOR FORMING A CHIP ARRANGEMENT - A chip arrangement is provided: the chip arrangement including: a carrier; a chip disposed over the carrier; a ceramic layer formed over the chip and on at least a portion of the carrier; wherein the chip is surrounded by the carrier and the ceramic layer. | 09-05-2013 |
20130285132 | Semiconductor Module With a Semiconductor Chip and a Passive Component and Method for Producing the Same - A semiconductor module includes a semiconductor chip and a passive discrete component. The semiconductor chip includes on its top side and/or on the back side one or more contacts, which in its two-dimensional extent takes up the top side and/or the back side of the semiconductor chip virtually completely. The passive component, arranged in a package, is stacked on one of the contacts. The electrode of the passive component is electrically connected with one of the contacts. The counter electrode of the passive component is operatively connected with a control or signal electrode of the semiconductor chip or an electrode of a further semiconductor chip. | 10-31-2013 |
20130285197 | Semiconductor Devices and Methods of Manufacturing and Using Thereof - A semiconductor device includes at least one first semiconductor element and two interconnectors for electrically coupling the at least one first semiconductor element to external. A spacing between the two interconnectors corresponds to a size of a second semiconductor element. The second semiconductor element can be affixed between the two interconnectors. | 10-31-2013 |
20130295724 | Power Semiconductor Chip Package - A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad. | 11-07-2013 |
20130313712 | Multi-Chip Package and Method of Manufacturing Thereof - A multi-chip package comprises a first chip accommodated in a first housing and a second chip accommodated in a second housing. The first housing and the second housing are arranged in a laterally spaced-apart relationship defining a gap between the first housing and the second housing. An interconnecting structure is configured to span the gap and to electrically couple the first chip and the second chip. | 11-28-2013 |
20130328213 | ELECTRONIC DEVICE INCLUDING A CARRIER AND A SEMICONDUCTOR CHIP ATTACHED TO THE CARRIER AND MANUFACTURING THEREOF - One aspect is a device including a carrier comprising a first conducting layer, a first insulating layer over the first conducting layer, and at least one first through-connection from a first face of the first insulating layer to a second face of the first insulating layer. A semiconductor chip is attached to the carrier and a second insulating layer is over the carrier and the semiconductor chip. A metal layer is over the second insulating layer. A second through-connection is through the second insulating layer electrically coupling the semiconductor chip to the metal layer. A third through-connection is through the second insulating layer electrically coupling the carrier to the metal layer. | 12-12-2013 |
20130334677 | Semiconductor Modules and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor device having a first plurality of leads including a first gate/base lead, a first drain/collector lead, and a first source/emitter lead. The module further includes a second semiconductor device and a circuit board. The second semiconductor device has a second plurality of leads including a second gate/base lead, a second drain/collector lead, and a second source/emitter lead. The circuit board has a plurality of mounting holes, wherein each of the first plurality of leads and the second plurality of leads is mounted into a respective one of the plurality of mounting holes. At the plurality of mounting holes, a first distance from the first gate/base lead to the second gate/base lead is different from a second distance from the first source/emitter lead to the second source/emitter lead. | 12-19-2013 |
20130341777 | Electro-Thermal Cooling Devices and Methods of Fabrication Thereof - In one embodiment, a semiconductor module includes a leadframe having a first side and an opposite second side. A semiconductor chip is disposed over the first side of the leadframe. A switching element is disposed under the second side of the leadframe. In another embodiment, a method of forming a semiconductor module includes providing a semiconductor device having a leadframe. A semiconductor chip is disposed over a first side of the leadframe. A switching element is attached at an opposite second side of the leadframe. | 12-26-2013 |
20140001480 | Lead Frame Packages and Methods of Formation Thereof | 01-02-2014 |
20140001615 | Package-In-Packages and Methods of Formation Thereof | 01-02-2014 |
20140008702 | Semiconductor Packages Having Multiple Lead Frames and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads. | 01-09-2014 |
20140061669 | CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE - A chip package is provided, the chip package including: a carrier including at least one cavity; a chip disposed at least partially within the at least one cavity; at least one intermediate layer disposed over at least one side wall of the chip; wherein the at least one intermediate layer is configured to thermally conduct heat from the chip to the carrier. | 03-06-2014 |
20140063766 | LATERAL ELEMENT ISOLATION DEVICE - Representative implementations of devices and techniques provide isolation between a carrier and a component mounted to the carrier. A multi-layer device having lateral elements provides electrical isolation at a preset isolation voltage while maintaining a preselected thermal conductivity between the component and the carrier. | 03-06-2014 |
20140084433 | Semiconductor Device Having a Clip Contact - A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device. | 03-27-2014 |
20140084449 | Semiconductor Housing with Rear-Side Structuring - A semiconductor housing includes a fixing mechanism and at least one side having structurings. A method for producing a semiconductor device is provided in which a thermally conductive paste is applied on the at least one side of the semiconductor housing and/or of a heat sink. The semiconductor housing is fixed to the heat sink by means of the fixing mechanism. A pressure is exerted on the thermally conductive paste by means of the fixing mechanism and the thermally conductive paste is diverted by means of diversion channels depending on the pressure exerted. | 03-27-2014 |
20140091401 | POWER SEMICONDUCTOR HOUSING WITH REDUNDANT FUNCTIONALITY - In various embodiments, a power semiconductor housing having an integrated circuit is provided. The integrated circuit may include: a first gate pad and a second gate pad; and a first gate contact and a second gate contact; wherein the first gate pad is electrically connected to the first gate contact; wherein the second gate pad is electrically connected to the second gate contact. The integrated circuit may further include a drain-contact surface, wherein the drain-contact surface is connected to a drain contact; and a second drain contact, which is electrically connected to the drain-contact surface of the integrated circuit. | 04-03-2014 |
20140097528 | CHIP ARRANGEMENTS, A CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT - A chip package is provided. The chip package includes a chip carrier, a voltage supply lead, a sensing terminal and a chip disposed over the chip carrier. The chip includes a first terminal and a second terminal, wherein the first terminal electrically contacts the chip carrier. The chip package also includes an electrically conductive element formed over the second terminal, the electrically conductive element electrically coupling the second terminal to the voltage supply lead and the sensing terminal. | 04-10-2014 |
20140103902 | Semiconductor Device Having Sensing Functionality - A semiconductor package includes a power semiconductor chip having a control electrode, a first load electrode and a second load electrode. The package also includes a first terminal conductor electrically coupled to the control electrode, a second terminal conductor electrically coupled to the first load electrode and a third terminal conductor electrically coupled to the second load electrode. Further, the package includes a temperature sensor electrically coupled to at least two of the first, second and third terminal conductor. | 04-17-2014 |
20140110828 | Semiconductor Packages and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor device includes a lead frame having a die paddle and a lead. A chip is disposed over the die paddle of the lead frame. The semiconductor device further includes a clip, which is disposed over the chip. The clip couples a pad on the chip to the lead of the lead frame. The clip also includes a heat sink. | 04-24-2014 |
20140110829 | Module Comprising a Semiconductor Chip - A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element. | 04-24-2014 |
20140118959 | CHIP-HOUSING MODULE AND A METHOD FOR FORMING A CHIP-HOUSING MODULE - A chip-housing module is provided, the chip-housing module including a carrier configured to carry one or more chips; the carrier including a first plurality of openings, wherein each opening of the first plurality of openings is separated by a first pre-determined distance, and is configured to receive a chip connection for providing a voltage lying within a first range of voltage values to a chip; the carrier including a second plurality of openings, wherein each opening of the second plurality of openings is separated by a second pre-determined distance, and is configured to receive a chip connection for providing a voltage lying within a second range of voltage values to a chip; and wherein a pair of openings consisting of one opening of the first plurality of openings and one opening of the second plurality of openings is separated by a distance different from at least one of the first pre-determined distance and the second pre-determined distance. | 05-01-2014 |
20140123454 | Adjustable Pick-up Head and Method for Manufacturing a Device - An adjustable pick-up head, a collet head, a method to adjust a pick-up head and a method of manufacturing a device are disclosed. In one embodiment a pick-up head includes a shank having a holder and an intermediate body connected to the holder by a first joint. The pick-up head further includes a collet head connected to the intermediate body by a second joint. | 05-08-2014 |
20140138803 | CHIP ARRANGEMENTS AND METHODS FOR MANUFACTURING A CHIP ARRANGEMENT - A chip arrangement is provided, the chip arrangement including: a carrier; a chip disposed over the carrier, the chip including one or more contact pads, wherein a first contact pad of the one or more contact pads is electrically contacted to the carrier; a first encapsulation material at least partially surrounding the chip; and a second encapsulation material at least partially surrounding the first encapsulation material. | 05-22-2014 |
20140145318 | Semiconductor Packages and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor package includes a die paddle, and an encapsulant disposed around the die paddle. The semiconductor package has a first sidewall and a second sidewall. The second sidewall is perpendicular to the first sidewall. The first sidewall and the second sidewall define a corner region. A tie bar is disposed within the encapsulant. The tie bar couples the die paddle and extends away from the die paddle. A dummy lead is disposed in the corner region. The dummy lead is not electrically coupled to another electrically conductive component within the semiconductor package. The distance between the dummy lead and the tie bar is less than a shortest distance between the tie bar and other leads or other tie bars in the semiconductor package. | 05-29-2014 |
20140151717 | Packaged Vertical Power Device Comprising Compressive Stress and Method of Making a Packaged Vertical Power Device - A packaged vertical semiconductive device including a compressive stress and a method of making such a packaged vertical semiconductive device are disclosed. In one embodiment an assembled device includes a carrier, a connection layer disposed on the carrier, the connection layer having a first height, and a chip disposed on the connection layer, the chip having a second height, wherein the second height is smaller than the first height. | 06-05-2014 |
20140151856 | Chip Module, an Insulation Material and a Method for Fabricating a Chip Module - The chip module includes a carrier, a semiconductor chip arranged on or embedded inside the carrier, and an insulation layer that at least partly covers a face of the carrier. The dielectric constant ∈ | 06-05-2014 |
20140151866 | Packaged Semiconductor Device with Tensile Stress and Method of Making a Packaged Semiconductor Device with Tensile Stress - An assembled semiconductor device and a method of making an assembled semiconductor device are disclosed. In one embodiment the assembled device includes a carrier having a first thickness, a connection layer disposed on the carrier and a chip disposed on the connection layer, the chip having a second thickness, wherein the second thickness is larger than the first thickness. | 06-05-2014 |
20140197523 | CHIP ARRANGEMENT AND A METHOD FOR FORMING A CHIP ARRANGEMENT - A chip arrangement is provided, the chip arrangement, including: a carrier; at least one chip including at least one contact pad disposed over the carrier; an encapsulation material at least partially surrounding the at least one chip and the carrier; and at least one low temperature co-fired ceramic sheet disposed over a side of the carrier. | 07-17-2014 |
20140197552 | CHIP ARRANGEMENT, A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT, INTEGRATED CIRCUITS AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material. | 07-17-2014 |
20140210061 | CHIP ARRANGEMENT AND CHIP PACKAGE - Various embodiments provide a chip arrangement. The chip arrangement may include a first chip including a first contact and a second contact; a second chip; a leadframe including a first leadframe portion and a second leadframe portion electrically insulated from the first leadframe portion; and a plurality of pins coupled to the leadframe. At least one first pin is coupled to the first leadframe portion and at least one second pin is coupled to the second leadframe portion. The first contact of the first chip is electrically coupled to the first leadframe portion and the second contact of the first chip is coupled to the second leadframe portion. A contact of the second chip is electrically coupled to the second leadframe portion. | 07-31-2014 |
20140217596 | POWER TRANSISTOR ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME - Various embodiments provide a power transistor arrangement. The power transistor arrangement may include a carrier; a first power transistor having a control electrode and a first power electrode and a second power electrode; and a second power transistor having a control electrode and a first power electrode and a second power electrode. The first power transistor and the second power transistor may be arranged next to each other on the carrier such that the control electrode of the first power transistor and the control electrode of the second power transistor are facing the carrier. | 08-07-2014 |
20140232015 | Semiconductor Modules and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor package having a first semiconductor die, which is disposed in a first encapsulant. An opening is disposed in the first encapsulant. A second semiconductor package including a second semiconductor die is disposed in a second encapsulant. The second semiconductor package is disposed at least partially within the opening in the first encapsulant. | 08-21-2014 |
20140252373 | Semiconductor Device and Method for Producing the Same - A method for producing a semiconductor device is provided. The method includes providing a semiconductor substrate, providing at least one semiconductor device on the substrate, having a back face opposite the semiconductor substrate and a front face towards the semiconductor substrate, providing a contact layer on the back face of the semiconductor device, bonding the contact layer to an auxiliary carrier, and separating the at least one semiconductor device from the substrate. Further, a semiconductor device produced according to the method and an intermediate product are provided. | 09-11-2014 |
20140252537 | PACKAGE ARRANGEMENT AND A METHOD OF MANUFACTURING A PACKAGE ARRANGEMENT - In various embodiments, a package arrangement is provided. The package arrangement may include a first package. The package arrangement may further include a through hole package including at least one contact terminal. The first package may include at least one hole in an encapsulant to receive the at least one contact terminal of the through hole package. The received at least one contact terminal may provide a solder contact. | 09-11-2014 |
20140252577 | CHIP CARRIER STRUCTURE, CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - Various embodiments provide a chip carrier structure. The chip carrier structure may include a structured metallic chip carrier; encapsulating material at least partially filling the structure; wherein the main surfaces of the metallic chip carrier are free from the encapsulating material. | 09-11-2014 |
20140264798 | Packaged Device Comprising Non-Integer Lead Pitches and Method of Manufacturing the Same - Packaged chips comprising non-integer lead pitches, systems and methods for manufacturing packaged chips are disclosed. In one embodiment a packaged device includes a first chip, a package encapsulating the first chip and a plurality of leads protruding from the package, wherein the plurality of leads comprises differing non-integer multiple lead pitches. | 09-18-2014 |
20140264944 | Semiconductor Package with Top-Side Insulation Layer - A semiconductor package includes a base, a die attached to the base, a lead and a connector electrically connecting the lead to the die. A mold compound encapsulates the die, the connector, at least part of the base, and part of the lead, so that the lead extends outward from the mold compound. An electrical insulation layer separate from the mold compound is attached to a surface of the mold compound over the connector. The electrical insulation layer has a fixed, defined thickness so that the package has a guaranteed minimum spacing between an apex of the connector and a surface of the electrical insulation layer facing away from the connector. | 09-18-2014 |
20140284615 | METHOD FOR MANUFACTURING A SILICON CARBIDE DEVICE AND A SILICON CARBIDE DEVICE - A method for manufacturing a silicon carbide device includes providing a silicon carbide wafer and manufacturing a mask layer on top of the silicon carbide wafer. Further, the method includes structuring the mask layer at an edge of a silicon carbide device to be manufactured, so that the mask layer includes a bevel at the edge of the silicon carbide device to be manufactured. Additionally, the method includes etching the mask layer and the silicon carbide wafer by a mutual etching process, so that the bevel of the mask layer is reproduced at the edge of the silicon carbide device. | 09-25-2014 |
20140284777 | Multi-Chip Semiconductor Power Device - A semiconductor device includes a first semiconductor power chip mounted over a first carrier and a second semiconductor power chip mounted over a second carrier. The semiconductor device further includes a contact clip mounted over the first semiconductor power chip and on the second semiconductor power chip. A semiconductor logic chip is mounted over the contact clip. | 09-25-2014 |
20140291849 | Multi-Level Semiconductor Package - A semiconductor package includes a semiconductor die having a first electrode at a first side and a second electrode at a second side opposing the first side, a first lead under the semiconductor die and connected to the first electrode at a first level of the package, and a second lead having a height greater than the first lead and terminating at a second level in the package above the first level, the second level corresponding to a height of the semiconductor die. A connector of a single continuous planar construction over the semiconductor die and the second lead is connected to both the second electrode and the second lead at the same second level of the package. | 10-02-2014 |
20140301039 | PACKAGE AND A METHOD OF MANUFACTURING THE SAME - In various embodiments, a package may be provided. The package may include a chip carrier. The package may further include a chip arranged over the chip carrier. The package may also include encapsulation material encapsulating the chip and partially the chip carrier. A coolant receiving recess may be provided over the chip in the encapsulation material, wherein the coolant receiving recess is configured to receive coolant. | 10-09-2014 |
20140306331 | CHIP AND CHIP ARRANGEMENT - Various embodiments provide a chip. The chip may include a body having two main surfaces and a plurality of side surfaces; a first power electrode extending over at least one main surface and at least one side surface of the body; and a second power electrode extending over at least one main surface and at least one side surface of the body. | 10-16-2014 |
20140312360 | Semiconductor Power Device Having a Heat Sink - A semiconductor device includes an electrically conducting carrier having a mounting surface. The semiconductor device further includes a metal block having a first surface facing the electrically conducting carrier and a second surface facing away from the electrically conducting carrier. A semiconductor power chip is disposed over the second surface of the metal block. | 10-23-2014 |
20140312394 | Semiconductor Device Including a Material to Absorb Thermal Energy - A semiconductor device includes a semiconductor chip and a first material including molecules that are configured to absorb thermal energy by reversibly changing a spatial molecular structure of the molecules. | 10-23-2014 |
20140374913 | CIRCUIT ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME - Various embodiments may provide a circuit arrangement. The circuit arrangement may include a carrier having at least one electrically conductive line; a plurality of discrete encapsulated integrated circuits arranged on the carrier; wherein a first integrated circuit of the plurality of integrated circuits is in electrical contact with a second integrated circuit of the plurality of integrated circuits to form a first current path bypassing the carrier; and wherein the first integrated circuit of the plurality of integrated circuits is in electrical contact with the second integrated circuit of the plurality of integrated circuits to form a second current path via the at least one electrically conductive line. | 12-25-2014 |
20150014858 | SEMICONDUCTOR DIE AND PACKAGE WITH SOURCE DOWN AND SENSING CONFIGURATION - A semiconductor die includes a semiconductor body, a transistor device disposed in the semiconductor body and having a gate, a source and a drain, and a sense device disposed in the semiconductor body and operable to sense a parameter associated with the transistor device. The die further includes a source pad at a first side of the semiconductor body and electrically connected to the source of the transistor device, a drain pad at a second side of the semiconductor body opposing the first side and electrically connected to the drain of the transistor device, and a sense pad at the second side of the semiconductor body and spaced apart from the drain pad. The sense pad is electrically connected to the sense device. A corresponding package and method of manufacturing are also disclosed. | 01-15-2015 |
20150041859 | Redistribution Board, Electronic Component and Module - A redistribution board includes a first conductive layer including a redistribution structure for low voltage signals, a second conductive layer including a redistribution structure for high voltage signals, and a non-conductive layer. The second conductive layer is spaced apart from the first conductive layer by the non-conductive layer. The redistribution board further includes a conductive connector extending from a mounting surface of the redistribution board to the second conductive layer. The conductive connector is surrounded by a low voltage trace of the first conductive layer. | 02-12-2015 |
20150041967 | Molded Semiconductor Package with Backside Die Metallization - A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame. | 02-12-2015 |
20150041984 | Electronic Component and Method - An electronic component includes a high-voltage depletion-mode transistor, a low-voltage enhancement-mode transistor arranged adjacent and spaced apart from the high-voltage depletion-mode transistor, and an electrically conductive member electrically coupling a first current electrode of the high-voltage depletion-mode transistor to a first current electrode of the low-voltage enhancement-mode transistor. The electrically conductive member has a sheet-like form. | 02-12-2015 |
20150060878 | Semiconductor Packages Having Multiple Lead Frames and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads. | 03-05-2015 |