Patent application number | Description | Published |
20090230463 | INTEGRATED CIRCUIT LONG AND SHORT CHANNEL METAL GATE DEVICES AND METHOD OF MANUFACTURE - A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench. | 09-17-2009 |
20100012975 | TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS AND RELATED MANUFACTURING METHOD - Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect. | 01-21-2010 |
20100012988 | METAL OXIDE SEMICONDUCTOR DEVICES HAVING IMPLANTED CARBON DIFFUSION RETARDATION LAYERS AND METHODS FOR FABRICATING THE SAME - Semiconductor devices and methods for fabricating semiconductor devices are provided. One exemplary method comprises providing a silicon-comprising substrate having a first surface, etching a recess into the first surface, the recess having a side surface and a bottom surface, implanting carbon ions into the side surface and the bottom surface, and forming an impurity-doped, silicon-comprising region overlying the side surface and the bottom surface. | 01-21-2010 |
20100044782 | INTEGRATED CIRCUIT HAVING LONG AND SHORT CHANNEL METAL GATE DEVICES AND METHOD OF MANUFACTURE - Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate, a short channel (SC) device, and a long channel (LC) device. The short channel device includes an SC gate insulator overlying a first portion of the substrate, an SC metal gate overlying the SC gate insulator, a polycrystalline silicon layer overlying the metal gate, and a silicide layer formed on the polycrystalline silicon layer. The long channel (LC) device includes an LC gate insulator overlying a second portion of the substrate and an LC metal gate overlying the LC gate insulator. An etch stop layer overlies an upper surface of the substrate, and an interlayer dielectric overlies an upper surface of the etch stop layer. An SC cap is disposed in the interlayer dielectric, overlies the device, and is formed substantially from the same metal as is the LC metal gate. | 02-25-2010 |
20100052094 | SEMICONDUCTOR DEVICE WITH ISOLATION TRENCH LINER, AND RELATED FABRICATION METHODS - A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material. | 03-04-2010 |
20100081245 | METHODS FOR FABRICATING MOS DEVICES HAVING HIGHLY STRESSED CHANNELS - Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, etching recesses into the substrate using the gate electrode as an etch mask, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses. | 04-01-2010 |
20100090289 | SEMICONDUCTOR DEVICES HAVING FACETED SILICIDE CONTACTS, AND RELATED FABRICATION METHODS - The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions. | 04-15-2010 |
20100210084 | METHODS FOR FABRICATING MOS DEVICES HAVING HIGHLY STRESSED CHANNELS - Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, etching recesses into the substrate using the gate electrode as an etch mask, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses. | 08-19-2010 |
20100308381 | FINFET STRUCTURES WITH STRESS-INDUCING SOURCE/DRAIN-FORMING SPACERS AND METHODS FOR FABRICATING THE SAME - Methods for fabricating FinFET structures with stress-inducing source/drain-forming spacers and FinFET structures having such spacers are provided herein. In one embodiment, a method for fabricating a FinFET structure comprises fabricating a plurality of parallel fins overlying a semiconductor substrate. Each of the fins has sidewalls. A gate structure is fabricated overlying a portion of each of the fins. The gate structure has sidewalls and overlies channels within the fins. Stress-inducing sidewall spacers are formed about the sidewalls of the fins and the sidewalls of the gate structure. The stress-inducing sidewall spacers induce a stress within the channels. First conductivity-determining ions are implanted into the fins using the stress-inducing sidewall spacers and the gate structure as an implantation mask to form source and drain regions within the fins. | 12-09-2010 |
20100308409 | FINFET STRUCTURES WITH FINS HAVING STRESS-INDUCING CAPS AND METHODS FOR FABRICATING THE SAME - FinFET structures with fins having stress-inducing caps and methods for fabricating such FinFET structures are provided. In an exemplary embodiment, a method for forming stressed structures comprises forming a first stress-inducing material overlying a semiconductor material and forming spacers overlying the first stress-inducing material. The first stress-inducing material is etched using the spacers as an etch mask to form a plurality of first stress-inducing caps. The semiconductor material is etched using the plurality of first stress-inducing caps as an etch mask. | 12-09-2010 |
20110027978 | METHODS FOR FABRICATING NON-PLANAR SEMICONDUCTOR DEVICES HAVING STRESS MEMORY - Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer. | 02-03-2011 |
20110169073 | TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS AND RELATED MANUFACTURING METHOD - Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect. | 07-14-2011 |
20110260263 | SEMICONDUCTOR DEVICE WITH ISOLATION TRENCH LINER - A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material. | 10-27-2011 |
20120129311 | METHOD OF MANUFACTURING A TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS - Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect. | 05-24-2012 |
20120223399 | SEMICONDUCTOR DEVICE WITH ISOLATION TRENCH LINER - A semiconductor device includes a layer of semiconductor material having an active transistor region defined therein, an isolation trench formed in the semiconductor material adjacent the active transistor region, and a trench liner lining the isolation trench, wherein the trench liner is formed from a material that substantially inhibits formation of high-k material thereon, and wherein the isolation trench and the trench liner together form a lined trench. The device has an insulating material in the lined trench, and high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, such that the trench liner divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region. | 09-06-2012 |
20150037945 | EPITAXIALLY FORMING A SET OF FINS IN A SEMICONDUCTOR DEVICE - Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins. | 02-05-2015 |