Patent application number | Description | Published |
20100072622 | Method for forming Barrier Layer and the Related Damascene Structure - A method for forming barrier layers comprises steps of forming a first metal barrier layer covering a first dielectric layer and contacting a conductive layer through a via of the first dielectric layer, forming a barrier layer of metalized materials on the first metal layer, optionally forming a second metal barrier layer on the barrier layer of metalized materials, removing portions of the barrier layer of metalized materials above the via bottom in the first dielectric layer, and leaving the barrier layer of metalized materials remaining on the via sidewall in the first dielectric layer; and forming a second metal layer covering the barrier layer of metalized materials. The accomplished barrier layers will have lower resistivity on the via bottom in the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer. | 03-25-2010 |
20100254148 | Lamp holder structure having heat dissipation fins - A lamp holder structure having heat dissipation fins comprises a base having a recess with threaded holes for install a luminous lamp set and at least one power line-in for connecting a power line. A plurality of heat dissipation fins arranged in parallel is extended and integrated from a corresponding exterior of the recess and a plurality of heat dissipation diverging fins is extended and integrated from an extreme exterior of the heat dissipation fins. Symmetric protruding plates are connected to predetermined places of the exterior of the base to pivotally connect a positioning plate capable of adjusting angles. A light-transmissive plate further seals the base and symmetric side strips are used to respectively lock symmetric frame borders of the base to position the light-transmissive plate. The corresponding sides of the recess of the base have locking holes for locking symmetric side covers. | 10-07-2010 |
20120146225 | DAMASCENE STRUCTURE - A damascene structure includes a conductive layer, a first dielectric layer, a first barrier metal layer, a barrier layer, and a second barrier metal layer sequentially formed on the conductive layer. The first dielectric layer having a via therein. The barrier layer is comprised of a material different with that of the first barrier metal layer. A bottom of the barrier layer disposed on the via bottom is not punched through. The accomplished barrier layers will have lower resistivity on the via bottom in the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer. | 06-14-2012 |
Patent application number | Description | Published |
20090104773 | METHOD OF FORMING CONTACT - A substrate having at least two metal oxide semiconductor devices of a same conductive type and a gap formed between the two devices is provided. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate, filling the gap. An etching back process is then performed to remove a portion of the stress material layer inside the gap. A second stress layer and a dielectric layer are sequentially formed on the first stress layer. The first stress layer and the second stress layer provide a same type of stress. A portion of the second stress layer is removed to form a contact opening. A second conductive layer is filled into the contact opening to form a contact. | 04-23-2009 |
20110127589 | SEMICONDUCTOR STRUCTURE HAIVNG A METAL GATE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening. | 06-02-2011 |
20110147948 | FORMING METHOD AND STRUCTURE OF POROUS LOW-K LAYER, INTERCONNECT PROCESS AND INTERCONNECT STRUCTURE - A structure of a porous low-k layer is described, comprising a bottom portion and a body portion of the same atomic composition, wherein the body portion is located on the bottom portion, and the bottom portion has a density higher than the density of the body portion. An interconnect structure is also described, including the above porous low-k layer, and a conductive layer filling up a damascene opening in the porous low-k layer. | 06-23-2011 |
20110266596 | Semiconductor device and method of making the same - In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a Ni | 11-03-2011 |
20120088345 | METHOD OF FORMING SILICIDE FOR CONTACT PLUGS - A method for forming silicide is provided. First, a substrate is provided. Second, a gate structure is formed on the substrate which includes a silicon layer, a gate dielectric layer and at least one spacer. Then, a pair of source and drain is formed in the substrate and adjacent to the gate structure. Later, an interlayer dielectric layer is formed to cover the gate structure, the source and the drain. Afterwards, the interlayer dielectric layer is selectively removed to expose the gate structure. Next, multiple contact holes are formed in the interlayer dielectric layer to expose part of the substrate. Afterwards, the exposed substrate is converted to form silicide. | 04-12-2012 |
Patent application number | Description | Published |
20080225525 | LIGHT SOURCE MODULE - A light source module for a projection apparatus including a light source unit, a fan, a temperature sensor and a temperature controller is provided. The fan is disposed towards the light source unit and is capable of cooling the light source unit. The temperature sensor is disposed adjacent to the light source unit and is capable of sensing an operating temperature of the light source unit. The temperature controller is electrically coupled to the fan and the temperature sensor, and is capable of adjusting a rotation speed of the fan according to the operating temperature of the light source unit. The invention is capable of keeping the operating temperature of the light source unit at or close to the predetermined operating temperature thereof by adjusting the rotation speed of the fan. | 09-18-2008 |
20140063758 | DUAL SCREEN ELECTRONIC DEVICE AND DETACHABLE DISPLAY MODULE THEREOF - A dual screen electronic device includes a main device having a first casing and a display screen, and a detachable display module. The first casing has a first opening. The display screen is located on the first casing and exposed from the first opening. The detachable display module includes a second casing, a power supply module, an electrophoretic display (EPD) module, and a control module. The second casing is detachably positioned on the first casing, and has a second opening. The power supply module is arranged on the second casing. The EPD module is fixed to the second casing, or is detachably positioned on the second casing, and has a display region exposed from the second opening. The control module is selectively located on the second casing or on the EPD module, and is electrically connected to the EPD module and the power supply module. | 03-06-2014 |
20150205562 | MOBILE DISPLAY SYSTEM AND MOBILE DISPLAY DEVICE - A mobile display system includes a first mobile display device and a second mobile display device. The first mobile display device includes a first power storage module, a first screen, and a wireless power transmitter. The first screen is configured to display a first image by using the power stored in the first power storage module. The second mobile display device includes a second power storage module, a second screen, and a wireless power receiver. The second screen is configured to display a second image by using the power stored in the second power storage module. During a period when the first power storage module is charged, the wireless power transmitter provides a first wireless power signal to the wireless power receiver, so as to charge the second power storage module by the first wireless power signal. | 07-23-2015 |
20160054635 | BOTTOM ELECTRODE SUBSTRATE FOR SEGMENT-TYPE ELECTRO-PHORETIC DISPLAY AND METHOD FOR MANUFACTURING THEREOF - The present disclosure provides a bottom electrode substrate for a segment-type electrophoretic display. The bottom electrode substrate includes a flexible substrate, a first conductive layer, an insulating layer, a second conductive layer and a segment-type electrode. The first conductive layer is disposed on the flexible substrate. The insulating layer covers the first conductive layer and the flexible substrate, wherein the insulating layer has at least one opening exposing a part of the first conductive layer. The second conductive layer is filled in the opening and in contact with the exposed first conductive layer. The segment-type electrode covers the second conductive layer and the insulating layer, and is in contact with the second conductive layer. A method for manufacturing the bottom electrode substrate is also provided herein. | 02-25-2016 |
Patent application number | Description | Published |
20120181635 | Semiconductor device - In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a Ni | 07-19-2012 |
20120220134 | METHOD FOR CLEARING NATIVE OXIDE - A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF | 08-30-2012 |
20130071981 | FABRICATING METHOD OF SEMICONDUCTOR ELEMENTS - A fabricating method of a semiconductor element includes the following steps. First, a substrate is provided. A metal gate structure and source/drain electrodes are already formed on the substrate. An amorphization process is performed in the source/drain electrodes to form an amorphous portion. An interlayer dielectric layer is formed on surfaces of the source/drain electrodes and a through hole contact is formed within the interlayer dielectric layer. A silicidation process is performed with the through hole contact and the amorphous portion of the source/drain electrodes to form a metal silicide layer. The fabricating method is capable of finishing the formation of the metal silicide layer in the condition that diameters of the through hole contact is becoming smaller and smaller. | 03-21-2013 |
20130149820 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes providing a substrate having a first transistor device and a second transistor device formed thereon; forming a patterned stress film covering the second transistor device and exposing the first transistor device on the substrate; performing a pre-amorphous implantation (PAI) process to form an amorphous layer respectively at two sides of the first transistor device, and removing the patterned stress film. | 06-13-2013 |
20130316540 | METHOD FOR REMOVING OXIDE - A method for removing oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A removing oxide process is performed to the substrate using nitrogen trifluoride (NF | 11-28-2013 |
20140038374 | METHOD FOR MANUFACTURING CMOS TRANSISTOR - A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion. | 02-06-2014 |
20140191298 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a semiconductor substrate, a metal gate structure, at least an epitaxial layer, an interlayer dielectric, at least a contact hole, at least a metal silicide layer and a fluorine-containing layer. The semiconductor substrate has at least a gate region and at least a source/drain region adjoining the gate region. The gate structure is disposed on the semiconductor substrate within the gate region. The epitaxial layer is disposed on the semiconductor substrate within the source/drain region. The interlayer dielectric covers the semiconductor substrate, the gate structure and the epitaxial layer. The contact hole penetrates the interlayer dielectric to reach the epitaxial layer. The metal silicide layer is formed in the epitaxial layer and is located on the bottom of the contact hole. The fluorine-containing layer is disposed on or in the epitaxial layer and is around sides of the metal silicide layer. | 07-10-2014 |
20150249142 | SEMICONDUCTOR STRUCTURE HAVING A METAL GATE WITH SIDE WALL SPACERS - A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening. | 09-03-2015 |
20150263137 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming an epitaxial layer within a source/drain region of a semiconductor substrate, forming a fluorine-containing layer on the surface of the epitaxial layer, forming a metal gate structure within the gate region after the step of forming the fluorine-containing layer, forming an interlayer dielectric to cover the semiconductor substrate, the epitaxial layer and the metal gate structure, forming a contact hole penetrating the interlayer dielectric to expose a portion of the epitaxial layer, forming a metal silicide layer on or in the epitaxial layer on a bottom of the contact hole so that the fluorine-containing layer is disposed on the periphery of the metal silicide layer. | 09-17-2015 |
Patent application number | Description | Published |
20130329383 | MOUNTING APPARATUS FOR CIRCUIT BOARD - A mounting apparatus includes a chassis, two mounting members, and two screws. The chassis includes a sidewall defining two spaced holes. The mounting members are fixed to a front end of a circuit board. A fixing hole parallel to the circuit board is defined in a front end of each mounting member. The screws extend through the holes of the sidewall and engage in the fixing holes of the mounting members, to perpendicularly fix the circuit board to the sidewall. | 12-12-2013 |
20130329387 | CIRCUIT BOARD MOUNTING APPARATUS - A circuit board mounting apparatus includes a circuit board, a chassis, and two mounting members. Two slots are defined in a front side of the circuit board. The chassis includes a side plate. The mounting members are fixed to the side plate and respectively connected to the slots of the circuit board. Each of the mounting members includes a hook locked to the circuit board, to perpendicularly fix the circuit board to the side plate. | 12-12-2013 |
20140003020 | CIRCUIT BOARD MOUNTING APPARATUS | 01-02-2014 |
20140140024 | CIRCUIT BOARD MOUNTING APPARATUS - A circuit board mounting apparatus includes a circuit board, a chassis, a first mounting member, a second mounting member, and a fastener. The chassis includes a side plate defining a through hole, a first hole, and a second hole communicating with the first hole. Each of the first and second mounting members includes two latching legs detachably mounted to a front end of the circuit board. A neck protrudes from a front end of the first mounting member, and a head is formed on a front end of the neck. The neck extends through the first hole and engages in the second hole. The head abuts a front side of the side plate. A fixing hole is defined in a front end of the second mounting member. The fastener extends through the through hole and engages in the fixing hole, to mount the circuit board to the side plate. | 05-22-2014 |
20140153202 | CIRCUIT BOARD MOUNTING APPARATUS - A circuit board mounting apparatus includes a side plate, a circuit board, and a mounting member. The side plate defines a slide slot and a latching hole. A latch protrudes forward from the circuit board, and includes a neck and a latching portion extending leftward from a front end of the neck. The mounting member is mounted to the circuit board, and includes a resilient arm and a hook protruding forward from the resilient arm. The latch extends through the slide slot to allow the neck to abut against a portion of the side plate bounding a left end of the slide slot, and to allow the latching portion to engage with a front side of the side plate. The resilient arm biases the hook to engage in the latching hole and abut against a portion of the side plate bounding a right end of the latching hole. | 06-05-2014 |
20140153207 | CIRCUIT BOARD MOUNTING APPARATUS - A circuit board mounting apparatus includes a chassis and a circuit board. The chassis includes a side plate defining a slide slot and a latching hole. A latch protrudes forward from the circuit board, and includes a neck and a latching portion extending left from a front end of the neck. A cutout is defined in a front side of the circuit board. A cantilever extends into the cutout. A hook protrudes forward from the cantilever. The latch extends through the slide slot to allow the neck to abut against a portion of the side plate bounding a left end of the slide slot, and to allow the latching portion to engage with a front side of the side plate. The cantilever resists the hook to engage in the latching hole and abut against a portion of the side plate bounding a right end of the latching hole. | 06-05-2014 |
20140157589 | CIRCUIT BOARD MOUNTING APPARATUS - A circuit board mounting apparatus includes a circuit board, a first mounting member, a second mounting member, and a third mounting member. The first and second mounting members are mounted to a front side of the circuit board. The third mounting member is mounted to a rear side of the circuit board. The circuit board is capable of being mounted to a first side plate of a first chassis in a perpendicular manner by the first and second mounting members, or is capable of being mounted to a second side plate of a second chassis in a parallel manner by the first, second, and third mounting members. | 06-12-2014 |