Yasufuku, JP
Akira Yasufuku, Kariya-Shi JP
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20100186404 | CONTROL DEVICE FOR INDUSTRIAL VEHICLE - A control device for an industrial vehicle including an electric storage device, a load device, a hydraulic pump, and a load motor is disclosed. The electric storage device stores regenerative power generated through regenerative braking performed by the travel motor. The hydraulic pump supplies a hydraulic circuit with hydraulic oil to operate the load device. The load motor drives the hydraulic pump. The control device includes a power control unit and a resistance flow passage. The power control unit executes control for supplying the load motor with the regenerative power when the electric storage device is in a fully charged state during regenerative braking performed by the travel motor. The resistance flow passage is arranged in the hydraulic circuit and enables passage of hydraulic oil while applying flow resistance to the hydraulic oil. When the electric storage device is in the fully charged state during regenerative braking performed by the travel motor and, at the same time, the load device is not performing a load handling operation, the hydraulic oil supplied from the hydraulic pump is guided to the resistance flow passage. | 07-29-2010 |
Hideyuki Yasufuku, Kanagawa JP
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20090197117 | WORM OPTICAL RECORDING MEDIUM - A write-once-read-many optical recording medium is disclosed that includes a support substrate; a recording layer on the support substrate, the recording layer containing an oxide of one of a metal and a metalloid as a principal component; and a layer adjacent to the recording layer. The recording layer includes a region where a constituent element of the adjacent layer is dispersed. Recording and reproduction are performable with laser light of a blue wavelength region. | 08-06-2009 |
Hideyuki Yasufuku, Tokyo JP
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20140348496 | HEATER LAMP FOR FIXATION, FIXING DEVICE, AND IMAGE FORMING APPARATUS - A heater lamp for fixation and a method of producing the heater lamp are provided. The heater lamp includes a heat generator and a protective casing to cover the heat generator, in which an amount of carbon in an external surface of the protective casing as detected by an X-ray photoelectron spectroscopic method is equal to or less than 12 atomic %. The method of producing a heater lamp for fixation includes preparing a heat generator; preparing a protective casing to cover the heat generator; and heating the heat generator in an atmosphere containing oxygen gas. | 11-27-2014 |
Kaori Yasufuku, Kawasaki-Shi JP
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20160108192 | POLYMER NANOFIBER SHEET AND METHOD FOR PRODUCING THE SAME - A polymer nanofiber sheet including polymer nanofibers having a polymer, the polymer nanofibers being accumulated and three dimensionally entangled. The polymer nanofiber sheet has a low molecular weight organic compound containing at least one 4- or higher-membered ring structure with an ether linkage. The difference between the average solubility parameter of the polymer and the average solubility parameter of the low molecular weight organic compound is less than 8 (J/cm | 04-21-2016 |
Kazuki Yasufuku, Tokyo JP
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20130124571 | KEYWORD ACQUIRING DEVICE, CONTENT PROVIDING SYSTEM, KEYWORD ACQUIRING METHOD, A COMPUTER-READABLE RECORDING MEDIUM AND CONTENT PROVIDING METHOD - A keyword related to a user's interest is acquired. A keyword acquiring device including a tree storage unit that stores a keyword tree obtained by performing hierarchization according to the number of appearances and relevance in advance using a keyword associated with content as a node records a keyword associated with content previously selected by a user as a log, extracts a plurality of keywords based on a predetermined condition from a log corresponding to a certain user recorded in the log, extracts a partial tree including the extracted keywords from the keyword tree, and acquires a keyword in a node having no other lower node as a keyword related to the user's interest. | 05-16-2013 |
Kenji Yasufuku, Fukui JP
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20080217156 | SWITCH DEVICE - A switch device includes a wiring board having a cutout provided therein, a land provided on an upper surface of the wiring board around the cutout, and a switch. The switch includes a lever, a switch contact activated upon the lever being moved in a predetermined direction, and a case including a step portion protruding from a surface thereof and positioned in the cutout of the wiring board, and a terminal protruding from the case and mounted on the land of the wiring board. The switch device securely holds the switch on the wiring board with a simple structure, and allows the switch to be activated reliably. | 09-11-2008 |
20090014307 | SWITCH - A spring member is provided in a switch having a lever to receive a pushing force from outside, by bringing an arch-part formed at the left end of the spring member into resilient contact with the bottom surface of the lever, in addition to the movable contact, the spring member also can return the lever. In the case of developing a compact and low-profile switch, the returning force of the lever can be increased to perform electrical connection or disconnection reliably. | 01-15-2009 |
20090065334 | SWITCH - A plurality of vertical bends are provided in a terminal projecting from a switch contact outwardly of a case. With this structure, when the terminal is soldered to a land on a wiring board, a plurality of solder layers are formed between the plurality of bends and the land. The plurality of solder layers can enhance the terminal strength, thereby preventing the switch from coming or floating off from the wiring board. Thus, a switch capable of ensuring reliable operation can be provided. | 03-12-2009 |
Kenta Yasufuku, Kanagawa JP
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20090216937 | MEMORY CONTROLLER, MEMORY SYSTEM, AND ACCESS CONTROL METHOD OF FLASH MEMORY - A memory controller adds dummy data to write data by referring to instruction information about a descriptor transfer of the write data if a size of the write data to be written according to a data-write request information does not match a page size unit, thereby adjusting the size of the write data to the page size unit and then outputs the write data. | 08-27-2009 |
20110055647 | PROCESSOR - A processor has an ALU, a load/store unit, a timer, an ECC calculator, and a plurality of ECC registers. When the load/store unit writes data in a main memory, the load/store unit writes written data and a count value of a timer in the main memory, and sets ECC status flag which indicates that an ECC about the written data is not correct in the main memory, and causes the ECC calculator to calculate the ECC about the written data after setting the ECC status flag, and writes the calculated ECC in the main memory and resets the ECC status flag after the ECC is calculated. | 03-03-2011 |
20110099336 | CACHE MEMORY CONTROL CIRCUIT AND CACHE MEMORY CONTROL METHOD - A cache memory control circuit has a plurality of counters, each of which is provided per set and per memory space and configured to count how many pieces of data of a corresponding memory space is stored in a corresponding set. The cache memory control circuit controls activation of a tag memory and a data memory of each of a plurality of sets according to a count value of each of the plurality of counters. | 04-28-2011 |
20110231593 | VIRTUAL ADDRESS CACHE MEMORY, PROCESSOR AND MULTIPROCESSOR - An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address. | 09-22-2011 |
20140068376 | MEMORY CONTROLLER AND SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a decoder of a memory controller includes: a syndrome calculating unit configured to calculate a syndrome based upon a code word read from the memory; an error locator polynomial generating unit configured to generate an error locator polynomial based upon the syndrome, and to obtain a number of errors based upon the generated error locator polynomial; and an error location calculating unit configured to calculate an error location based upon the error locator polynomial, wherein the process of the error location calculating unit is not executed, when the number of errors is not less than the maximum number of bits that can be corrected by the error locator polynomial generating unit. | 03-06-2014 |
20140068378 | SEMICONDUCTOR STORAGE DEVICE AND MEMORY CONTROLLER - According to an embodiment, a semiconductor storage device includes a memory, an encoding unit that generates a parity, and a decoding unit that includes a syndrome calculating unit, an error position polynomial calculating unit, and an error searching and correcting unit, and performs an error correcting process based on data and the parity read from the memory. At the time of performing a compaction process, a process of the error searching and correcting unit is not performed, when the number of error bits acquired by an error position polynomial is equal to or less than a first threshold value based on valid data. | 03-06-2014 |
20140164702 | VIRTUAL ADDRESS CACHE MEMORY, PROCESSOR AND MULTIPROCESSOR - An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address. | 06-12-2014 |
Kenta Yasufuku, Kawasaki-Shi JP
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20090063822 | MICROPROCESSOR - A microprocessor includes: a processor core that performs pipeline processing; an instruction analyzing section that analyzes an instruction to be processed by the processor core and outputs analysis information indicating whether the instruction matches with a specific instruction; and a memory that temporary stores the instruction with the analysis information, wherein the processor core includes: an instruction fetch unit that fetches the instruction stored in the memory; an instruction decode unit that decodes the instruction fetched by the instruction fetch unit; an instruction execute unit that executes the instruction decoded by the instruction decode unit; and a specific instruction execute controller that reads out the analysis information stored in the memory and controls operation of at least one of the instruction fetch unit and the instruction decode unit when the analysis instruction indicates that the instruction matches with the specific instruction. | 03-05-2009 |
20090259813 | MULTI-PROCESSOR SYSTEM AND METHOD OF CONTROLLING THE MULTI-PROCESSOR SYSTEM - A multi-processor system has a plurality of processor cores, a plurality of level-one caches, and a level-two cache. The level-two cache has a level-two cache memory which stores data, a level-two cache tag memory which stores a line bit indicative of whether an instruction code included in data stored in the level-two cache memory is stored in the plurality of level-one cache memories or not line by line, and a level-two cache controller which refers to the line bit stored in the level-two cache tag memory and releases a line in which data including the same instruction code as that stored in the level-one cache memory is stored, in lines in the level-two cache memory. | 10-15-2009 |
20120030428 | INFORMATION PROCESSING DEVICE, MEMORY MANAGEMENT DEVICE AND MEMORY MANAGEMENT METHOD - According to one embodiment, an information processing device includes a first determination section and a setting section. The first determination section determines inconsistency between first data and second data. The first data is stored in a nonvolatile semiconductor memory. The second data is corresponding to the first data and stored in a semiconductor memory. The setting section sets execution timing of write back based on access frequency information associated with the second data. | 02-02-2012 |
20130013975 | SYSTEM AND DEVICE - According to one embodiment, a system includes a plurality of ring-connected devices. The system includes a first device and a second device. The second device is connected to receive a signal from the first device. When the first device is a data relay station and receives the data containing an error, the first device replaces a part of the data with internally generated data and transmits the resultant data to the second device. | 01-10-2013 |
Kenta Yasufuku, Tokyo JP
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20140129901 | MEMORY SYSTEM - A memory system includes a first nonvolatile memory, a second nonvolatile memory with a longer access latency than the first nonvolatile memory, a first error correction unit, a second error correction unit, and an interface. The first nonvolatile memory stores first data and a first error correction code generated for the first data. The second nonvolatile memory stores a second error correction code which is generated for the first data with a higher correction ability than that of the first error correction code. The first error correction unit performs error correction on the first data by using the first error correction code. The second error correction unit performs error correction on the first data by using the second error correction code. The interface transmits the first data after the error correction to a host. | 05-08-2014 |
20140241096 | STORAGE DEVICE - A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token. | 08-28-2014 |
Noboru Yasufuku, Ichinomiya-Shi JP
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20110250755 | METHOD OF POLISHING WAFER SURFACE ON WHICH COPPER AND SILICON ARE EXPOSED - A method of the present invention includes polishing a wafer having an exposed copper or copper alloy surface and an exposed silicon surface by using a polishing composition containing 0.02 to 0.6% by mass of hydrogen peroxide, preferably 0.05 to 0.2% by mass thereof. The polishing composition preferably further contains at least one of a complexing agent, an inorganic electrolyte, and abrasive grains such as colloidal silica. The polishing composition has a pH of preferably 9 or more, more preferably 10 or more. | 10-13-2011 |
Noboru Yasufuku, Kiyosu-Shi JP
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20130181159 | SURFACE TREATMENT COMPOSITION AND SURFACE TREATMENT METHOD USING SAME - A surface treatment composition of the present invention contains a first surfactant, a second surfactant, a basic compound, and water. The surface treatment composition has a pH of 8 or more. The second surfactant has a weight-average molecular weight one-half or less that of the first surfactant. The sum of the content of the first surfactant and the content of the second surfactant is 0.00001 to 0.1% by mass. | 07-18-2013 |
Noriyuki Yasufuku, Fukuoka JP
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20100129163 | FOUNDATION-UNIT STRUCTURE OF STRUCTURAL OBJECT SUCH AS RETAINING WALL, STRUCTURE OF UPPER AND LOWER BOUNDARIES OF RETAINING WALL, AND RETAINING WALL - The present invention provides a foundation-unit structure of a structural object such as a retaining wall installed fixedly on a foundation ground, in which the foundation ground is formed therein with a concavity, a sliding resistive element is placed within the concavity, and at least the front surface side of the sliding resistive element is filled with a grain-sized material so as to form a layer thereof, and an internal frictional angle of the grain-sized material forming the grain-sized material layer is equal to or greater than that of a grain-sized material comprising the ground and supporting the grain-sized material layer, and the grain-sized material layer exerts a reaction force (passive) via the sliding resistive element so as to reinforce a sliding resistance of the structural object mounted on the grain-sized material layer. In this way, a retaining wall excellent in a sliding preventive function is provided. | 05-27-2010 |
Shoji Yasufuku, Otsu-Shi JP
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20100016263 | 9, 10-SECOPREGNANE DERIVATIVE AND PHARMACEUTICAL - A main object of the invention is to provide a novel useful vitamin D | 01-21-2010 |
Shoji Yasufuku, Shiga JP
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20100130454 | 9,10-SECOPREGNANE DERIVATIVES AND MEDICINE - A novel useful vitamin D3 derivative which is reduced in influence on systemic calcium metabolism while retaining excellent vitamin D3 activity. The derivative is a 9,10-secopregnane derivative represented by the following general formula [1]. Also provided is a medicinal composition containing the derivative as an active ingredient. In the general formula [1], Y represents (1) a single bond, (2) alkylene (3) alkenylene, or (4) phenylene; R | 05-27-2010 |
Tadashi Yasufuku, Tokyo JP
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20110260781 | INTEGRATED CIRCUIT DEVICE - The interposer is disposed on an upper surface of the stacked structure formed by stacking a plurality of a DRAM chip and a plurality of a flash memory chip. Thus down-size of an entire device is accomplished. A boost converter having an inductor is used as a voltage boost circuit. Thus down-size of the entire device is accomplished in comparison to a voltage boost circuit using a charge pump connected in parallel with a plurality of a capacitance. | 10-27-2011 |
20110298534 | INTEGRATED CIRCUIT DEVICE - The channel number detecting circuit | 12-08-2011 |
20140104952 | INTEGRATED CIRCUIT DEVICE - A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor. | 04-17-2014 |
Tadashi Yasufuku, Kanagawa JP
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20150078102 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DATA TRANSMISSION METHOD - A nonvolatile semiconductor memory device includes a first data latch, a second data latch, and a data bus between the first and second data latches. A first transistor is electrically connected between the first data latch and the data bus and a second transistor is electrically connected between the data bus and the second data latch. A control unit controls charging of the data bus based on an output of the first data latch. | 03-19-2015 |
Tomohiro Yasufuku, Matsumoto-Shi JP
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20140362133 | RECORDING APPARATUS - There is provided a recording apparatus including a recording head that can eject an ink onto a sheet, a transport unit that transports the sheet to the recording head, a housing that contains the recording head and the transport unit, a case that is arranged on an outer surface of the housing so that the bottom portion thereof is positioned higher than a bottom surface of the housing, and that serves as a holder which holds an ink container containing an ink, and a supply unit that supplies the ink from the ink container to the recording head. | 12-11-2014 |
20150258800 | RECORDING APPARATUS - There is provided a recording apparatus including a recording head that can eject an ink onto a sheet, a transport unit that transports the sheet to the recording head, a housing that contains the recording head and the transport unit, a case that is arranged on an outer surface of the housing so that the bottom portion thereof is positioned higher than a bottom surface of the housing, and that serves as a holder which holds an ink container containing an ink, and a supply unit that supplies the ink from the ink container to the recording head. | 09-17-2015 |
Tomohiro Yasufuku, Matsumoto JP
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20150174923 | RECORDING DEVICE - A printer includes a device main body, a recording section, and a mounting section. The recording section is provided at the device main body and configured to record on a first recording medium and a second recording medium having lenticular lenses. The mounting section is configured to selectively mount a first conveyance unit configured to convey the first recording medium and a second conveyance unit configured to convey the second recording medium. | 06-25-2015 |
20160059592 | PRINTING APPARATUS - A printing apparatus which includes at least a first tray and a second tray as a tray which accommodates a printing sheet, and can be mounted with a sheet supply unit which supplies the printing sheet by being switched to any one of the first tray and the second tray. | 03-03-2016 |
Yoichi Yasufuku, Machida JP
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20150046394 | STORAGE SYSTEM, STORAGE CONTROL DEVICE, AND STORAGE MEDIUM STORING CONTROL PROGRAM - When a master name node has created a file, the master name node performs meta-information synchronization with only a slave name node, and does not perform the meta-information synchronization with a dummy name node. The master name node performs the meta-information synchronization with the dummy name node asynchronously with file creation. Furthermore, the slave name node stores the same meta-information as that stored in the master name node, and the file is stored in a data node placed in the same node as the slave name node and a data node placed in the same node as the master name node. | 02-12-2015 |
Yusuke Yasufuku, Kawasaki JP
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20150056468 | HIGH STRENGTH STEEL SHEET AND METHOD OF MANUFACTURING THE SAME - The high strength steel sheet has a chemical composition including 0.08% to 0.20% of C, 0.3% or less of Si, 0.1% to 3.0% of Mn, 0.10% or less of P, 0.030% or less of S, 0.10% or less of Al, 0.010% or less of N, 0.20% to 0.80% of V, and the remainder composed of Fe and incidental impurities on a percent by mass basis, and a microstructure which includes 95% or more of ferrite phase on an area percentage basis, in which fine precipitates are dispersed having a distribution in such a way that the number density of precipitates having a particle size of less than 10 nm is 1.0×10 | 02-26-2015 |