Patent application number | Description | Published |
20110143591 | ELECTRICAL CONNECTOR HAVING CONTACT MODULES - A contact module is provided for an electrical connector. The contact module includes a housing having a mating edge, a mounting edge, and a side. An electrical lead is held by the housing. The electrical lead extends from a mating contact to a mounting contact. The mating contact extends outwardly from the mating edge of the housing. The mounting contact extends outwardly from the mounting edge of the housing. An inner ground shield is mounted on the housing. The inner ground shield includes a housing side segment that extends over at least a portion of the side of the housing between the mating and mounting edges thereof. An outer ground shield is mounted on the housing. The outer ground shield extends over at least a portion of the housing side segment of the inner ground shield. | 06-16-2011 |
20120015556 | GROUND SHIELD FOR AN ELECTRICAL CONNECTOR - A ground shield is provided for an electrical connector mounted on a printed circuit. The ground shield includes a body extending from a mating interface to a mounting interface. An electrical ground path is defined through the body between the mating and mounting interfaces. The mating interface includes a mating contact configured to engage a mating connector. The mounting interface includes a mounting contact configured to engage the printed circuit. The body includes two conductive layers separated by a dielectric substance such that a capacitor is provided within the electrical ground path. | 01-19-2012 |
20120184138 | CONNECTOR ASSEMBLY - A connector assembly includes contact modules having dielectric bodies holding contacts having mating portions extending from the dielectric body. The connector assembly includes a conductive shield body holding the contact modules in a stacked configuration. The shield body provides shielding around the contact modules and the shield body has a mating end configured to be mated to a mating connector assembly. The mating end has one or more exposed surfaces between corresponding contacts. The shield body extends between selected contact modules. The connector assembly includes a conductive gasket positioned along the mating end of the shield body. The conductive gasket engages the exposed surfaces of the shield body to define a ground path between the conductive shield body and the mating connector assembly. | 07-19-2012 |
20130122744 | GROUNDING STRUCTURES FOR HEADER AND RECEPTACLE ASSEMBLIES - A receptacle assembly includes a front housing configured for mating with a header assembly and a contact module coupled to the front housing. The contact module includes a conductive holder having a first side wall and an opposite second side wall. The conductive holder has a chamber between the first and second side walls. The conductive holder has a front coupled to the front housing. The contact module includes a frame assembly that is received in the chamber. The frame assembly includes a plurality of contacts and a dielectric frame that supports the contacts. The contacts extend from the conductive holder for electrical termination. A plurality of ground clips are received in the chamber and extend from the front of the conductive holder. The ground clips are mechanically and electrically connected to the conductive holder. | 05-16-2013 |
20130288525 | RECEPTACLE ASSEMBLY FOR A MIDPLANE CONNECTOR SYSTEM - A receptacle assembly includes a contact module having a conductive holder and a frame assembly received in the conductive holder and electrically shielded by the conductive holder. The frame assembly has a plurality of receptacle signal contacts having mating portions extending from the conductive holder. The receptacle signal contacts are arranged in differential pairs carrying differential signals. Ground shields are received in the conductive holder between the frame assembly and the conductive holder. The ground shields have grounding beams extending along the mating portions of the receptacle signal contacts. The grounding beams are arranged on four sides of each differential pair of the receptacle signal contacts. | 10-31-2013 |
20150064968 | RECEPTACLE ASSEMBLY HAVING A PLURALITY OF TERMINATION POINTS - A receptacle assembly includes a contact module having a conductive holder and a frame assembly held by the conductive holder. The conductive holder has a first holder member and second holder member coupled to the first holder member. The conductive holder has a chamber between the first and second holder members divided into a plurality of channels by first tabs of the first holder member and second tabs of the second holder member. The first tabs have posts extending therefrom and the second tabs have holes receiving the posts of the first tabs. Each post has a plurality of termination points with the corresponding tab. The first and second holder members are electrically connected to one another at the termination points. The first and second tabs pass between contacts of the frame assembly to provide electrical shielding therebetween. | 03-05-2015 |
Patent application number | Description | Published |
20090061604 | GERMANIUM SUBSTRATE-TYPE MATERIALS AND APPROACH THEREFOR - Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices. | 03-05-2009 |
20100159678 | GERMANIUM SUBSTRATE-TYPE MATERIALS AND APPROACH THEREFOR - Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices. | 06-24-2010 |
20140264501 | DEPLETION-MODE FIELD-EFFECT TRANSISTOR-BASED PHOTOTRANSITOR - A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon. | 09-18-2014 |
20140308801 | Anything on Glass - Bonding of one or more semiconductor layers to a glass substrate is facilitated by depositing spin-on-glass (SOG) on the top of the semiconductor layers. The SOG is then bonded to the glass substrate, and after that, the original substrate of the semiconductor layers is removed. The resulting structure has the semiconductor layers disposed on the glass substrate with a layer of SOG sandwiched between. Bonding is always between glass and glass, and is independent of the composition of the target layers. Thus, it can provide “anything on glass”. For example, X-on-insulator (XOI), where X can be silicon, germanium, GaAs, GaN, SiC, graphene, etc. The spin-on-glass also helps with the surface roughness requirement. | 10-16-2014 |
20140363917 | DEPLETION-MODE FIELD-EFFECT TRANSISTOR-BASED PHOTOTRANSISTOR - A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon. | 12-11-2014 |
20150136214 | Solar cells having selective contacts and three or more terminals - Junction-less solar cells having three or more terminals are provided. Electron- and hole-selective contacts and interfaces are used in combination with two or more absorber layers having different bandgaps to provide multi-material solar cells that have no requirement for either lattice matching or current matching. | 05-21-2015 |
20150372455 | Crossed Nanobeam Structure for a Low-Threshold Germanium Laser - A crossed nanobeam structure for strain engineering in semiconductor devices is provided. For example, such a structure can be used for a low-threshold germanium laser. While the photonic crystal nanobeam enables light confinement in a subwavelength volume with small optical loss, another crossing nanobeam induces high tensile strain in the small region where the optical mode is tightly confined. As maintaining a small optical loss and a high tensile strain reduces the required pumping for achieving net optical gain beyond cavity losses, this technique can be used to develop an extremely low-threshold Ge laser source. Moreover, the structure can be easily integrated into electronic and photonic circuits. | 12-24-2015 |
Patent application number | Description | Published |
20100149864 | MEMORY CIRCUIT WITH QUANTUM WELL-TYPE CARRIER STORAGE - Data is stored in a quantum-well type structure with double gate control. According to an example embodiment, a transistor-based data storage circuit includes a gate, a back gate and a semiconductor channel between the gate and the back gate. Carriers are stored in a storage pocket structure in the channel, in response to biases applied to the gate and back gate. Current passing through the channel is sensed and used to detect the stored carriers and, correspondingly, a memory state of the storage circuit. | 06-17-2010 |
20120138899 | SEMICONDUCTOR APPARATUSES AND METHOD THEREFOR - In accordance with one or more embodiments, an apparatus and method involves a channel region, barrier layers separated by the channel region and a dielectric on one of the barrier layers. The barrier layers have band gaps that are different than a band gap of the channel region, and confine both electrons and holes in the channel region. A gate electrode applies electric field to the channel region via the dielectric. In various contexts, the apparatus and method are amenable to implementation for both electron-based and hole-based implementations, such as for nmos, pmos, and cmos applications. | 06-07-2012 |
20130307025 | TRANSISTOR-BASED APPARATUSES, SYSTEMS AND METHODS - Various aspects of the invention are directed to memory circuits and their implementation. According to an example embodiment, an apparatus includes a channel region between raised source and drain regions which are configured and arranged with respective bandgap offsets relative to the channel region to confine carriers in the channel region. The apparatus also includes front and back gates respectively separated from the channel region by gate dielectrics. The raised source and drain regions have respective portions laterally adjacent the front gate and adjacent the channel region. Carriers are stored in the channel region via application of voltage(s) to the front and back gates, and relative to bias(es) at the source and drain regions. | 11-21-2013 |
Patent application number | Description | Published |
20110319380 | Compounds for Treating Disorders Mediated by Metabotropic Glutamate Receptor 5, and Methods of Use Thereof - Provided herein are compounds and methods of synthesis thereof. The compounds set forth herein are useful for the treatment, prevention, and/or management of various disorders, such as neurological disorders, neurodegenerative disorders, neuropsychiatric disorders, disorders of cognition, learning or memory, gastrointestinal disorders, lower urinary tract disorder, and cancer. Compounds set forth herein modulate the activity of metabotropic glutamate receptor 5 (mGluR5) in the central nervous system or the periphery. Pharmaceutical formulations containing the compounds and their methods of use are also provided herein. | 12-29-2011 |
20140179682 | METABOTROPHIC GLUTAMATE RECEPTOR 5 MODULATORS AND METHODS OF USE THEREOF - Compounds that modulate GluR5 activity and methods of using the same are disclosed. | 06-26-2014 |
20140221332 | METABOTROPHIC GLUTAMATE RECEPTOR 5 MODULATORS AND METHODS OF USE THEREOF - Compounds that modulate GluR5 activity and methods of using the same are disclosed. | 08-07-2014 |
20140349992 | COMPOUNDS FOR TREATING DISORDERS MEDIATED BY METABOTROPIC GLUTAMATE RECEPTOR 5, AND METHODS OF USE THEREOF - Provided herein are compounds and methods of synthesis thereof. The compounds set forth herein are useful for the treatment, prevention, and/or management of various disorders, such as neurological disorders, neurodegenerative disorders, neuropsychiatric disorders, disorders of cognition, learning or memory, gastrointestinal disorders, lower urinary tract disorder, and cancer. Compounds set forth herein modulate the activity of metabotropic glutamate receptor 5 (mGluR5) in the central nervous system or the periphery. Pharmaceutical formulations containing the compounds and their methods of use are also provided herein. | 11-27-2014 |
Patent application number | Description | Published |
20120210257 | AUTOMATED SYSTEM FOR ANALYZING POWER PLANT OPERATIONS - Systems and methods for analyzing and displaying power plant data are able to access continuous live and/or historical operational data and identify within the data: (a) instances of at least one given type of power plant operation, (b) key events that may occur during an instance of the at least one given type of power plant operation, and (c) one or more time-based segments based on the key events and a physical segmentation of the power plant. Performance aspects for selected identified power plant operation instances can be quantified by comparing the identified instances with metrics that are predefined relative to the key events and segmentation within each type of power plant operation. Selected data associated with the identified instances are provided as electronic output to a user. | 08-16-2012 |
20130031483 | AUTOMATIC DETECTION OF DESIGNATED CONTROLLER IN A DISTRIBUTED CONTROL SYSTEM USING A WEB CLIENT - A control system, in one embodiment, includes a plurality of controllers. Each of the plurality of controllers is configured to provide process data to a human-machine interface (HMI) client when selected as a designated controller. A first controller of the plurality of controllers is a current designated controller and is configured to communicate with the HMI client. The control system also includes designated controller selection logic configured to detect an interruption in communication between the current designated controller and the HMI client, poll each of the plurality of controllers for a response, determine which of the plurality of controllers responds first, and select the controller that responds first as the next designated controller. | 01-31-2013 |
20150066223 | Automatic Switching of HMI Screens Based on Process, Task, and Abnormal Deviation in a Power Plant - Embodiments of the disclosure relate to automatic switching of HMI (human-machine interface) screens based on process, task, and abnormal deviation in a power plant. According to one embodiment, a method is provided. The method can include monitoring one or more processes occurring during the operation of a turbine power plant in a steady state monitoring sequence, in which a plurality of overview screens are monitored, and at least one process state is determined. If the at least one process state indicates a predefined condition has occurred, at least one human interface screen can be presented to a user for troubleshooting, based at least in part on the severity of the predefined condition. If the determined process state does not indicate the predefined condition is present, and the at least one determined process state indicates an automated task sequence, the method present a sequence of preconfigured task screens to a user. | 03-05-2015 |
20150066997 | Systems and Methods for Managing Power Plant Component Information - Certain embodiments herein relate to systems and methods for managing power plant component information. In one embodiment, a system can include at least one memory configured to store computer-executable instructions and at least one control device configured to access the at least one memory and execute the computer-executable instructions. The instructions may be configured to associate an identifier with a component and correlate the identifier with component information stored in a database. The instructions may be configured to output the information to a portable device. In another embodiment of the disclosure, an output of information to a portable device may be specified and updated according to input to the portable device. | 03-05-2015 |
Patent application number | Description | Published |
20110134963 | PHASE-LOCKED LOOP BASED CHAOTIC SPREAD SPECTRUM GENERATOR - Embodiments of the invention relate to apparatus and method for reducing electromagnetic interference (EMI) and radio frequency interference (RFI) in computer systems via a chaotic frequency modulation. In one embodiment, an apparatus comprises a first cell comprising a chaotic signal generator to generate a chaotic signal and a phase-locked loop (PLL) to generate a modulated output signal based at least on an un-modulated reference signal and the chaotic signal. | 06-09-2011 |
20110135027 | CHAOTIC WIDE BAND FREQUENCY MODULATOR FOR NOISE REDUCTION - The embodiments of the invention relate to apparatus and method for reducing electromagnetic interference (EMI) and radio frequency interference (RFI) in computer systems via a chaotic wide band frequency modulation. The chaotic noise modulator, in one embodiment, comprises: a master cell to generate a control voltage corresponding to an un-modulated reference signal; and a slave cell having a chaotic signal generator to generate a random noise signal, the slave cell coupled with the master cell and operable to generate a modulated output signal in response to the control voltage. | 06-09-2011 |
20120250443 | Energy Efficient Power Distribution for 3D INTEGRATED CIRCUIT Stack - Multiple dies can be stacked in what are commonly referred to as three-dimensional modules (or “stacks”) with interconnections between the dies, resulting in an IC module with increased circuit component capacity. Such structures can result in lower parasitics for charge transport to different components throughout the various different layers. | 10-04-2012 |
20130275665 | DYNAMIC OPERATIONS FOR 3D STACKED MEMORY USING THERMAL DATA - Dynamic operations for operations for 3D stacked memory using thermal data. An embodiment of a memory device includes memory having multiple coupled memory elements and multiple thermal sensors, including a first thermal sensor in a first area of the memory stack and a second thermal sensor in a second area of the memory stack. A memory controller is to provide operations to modify thermal conditions of the memory elements based at least in part on thermal information generated by the thermal sensors. | 10-17-2013 |
20130335059 | FULLY INTEGRATED VOLTAGE REGULATORS FOR MULTI-STACK INTEGRATED CIRCUIT ARCHITECTURES - A voltage regulator for one or more dies in a multi-stack integrated circuit includes an inductor located on a die, a voltage controller that is electrically coupled to the inductor and is also located on the die, and a capacitor that is electrically coupled to the inductor and the voltage controller and is also located on the die. The inductor defines an interior space and the voltage controller and the capacitor are located within the interior space of the inductor. The inductor can be a lateral inductor or a through layer via inductor. The multi-stack integrated circuit may have multiple dies. A voltage controller may be electrically coupled to each of the dies, although it may be located on only one of the dies. Alternatively, separate voltage controllers may be electrically coupled to each of the multiple dies and may be located on each of the respective dies. | 12-19-2013 |
20140085959 | 3D MEMORY CONFIGURABLE FOR PERFORMANCE AND POWER - A 3D memory that is configurable for performance and power. An embodiment of a memory device includes a dynamic random-access memory (DRAM) including multiple memory dies, each memory die including multiple memory arrays, each memory array including peripheral logic circuits and a configurable logic. The memory device further includes a system element coupled with the DRAM, the system element including a memory controller. The memory controller is to provide for control of the configurable logic to provide for separate or shared peripheral logic circuits for one or more memory arrays, the configurable logic being configurable to enable or disable one or more of the peripheral logic circuits and to enable or disable one or more I/O connections between the memory arrays. | 03-27-2014 |
20140092574 | INTEGRATED VOLTAGE REGULATORS WITH MAGNETICALLY ENHANCED INDUCTORS - Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate. In further embodiments, integrated circuitry on a same substrate as the magnetically enhanced inductor, or on another substrate stacked thereon, completes the VR and/or is powered by the VR circuitry. | 04-03-2014 |
20140183691 | RESONANT CLOCKING FOR THREE-DIMENSIONAL STACKED DEVICES - Resonant clocking for three-dimensional stacked devices. An embodiment of an apparatus includes a stack including integrated circuit dies; and through silicon vias through at least one of the dies, wherein at least a first through silicon via of the through silicon vias includes a capacitive structure or an inductive structure, the first through silicon via being formed in a first die of the plurality of dies. The apparatus includes a resonant circuit, the first through silicon via used as a first circuit element of the resonant circuit. | 07-03-2014 |
20140198013 | BACKSIDE REDISTRIBUTION LAYER PATCH ANTENNA - A patch antenna system comprising: an integrated circuit die having an active side including an active layer, and a backside; a dielectric layer formed on the backside; and a redistribution layer formed on the dielectric layer wherein the redistribution layer forms an array of patches. The patch antenna further comprises a plurality of through-silicon vias (TSV), wherein the TSVs electrically connect the array of patches to the active layer. | 07-17-2014 |
20150082062 | HETEROGENOUS MEMORY ACCESS - A memory controller operable for selective memory access to areas of memory exhibiting different attributes leverages different memory capabilities that vary access speed, retention time and power consumption, among others. Different areas of memory have different attributes while remaining available to applications as a single contiguous range of addressable memory. The memory controller employs an operating mode that identifies operational priorities for a computing device, such as speed, power conservation, or efficiency. The memory controller identifies an area of memory based on an expected usage of the data stored in the area, for example an access frequency indicating future retrieval. The memory controller therefore selects areas of memory based on the operating mode and the expected usage of data to be stored in the area according to a heuristic that favors areas of memory based on those exhibiting attributes having a high correspondence to the expected usage of the data. | 03-19-2015 |
20150270777 | MASTER-SLAVE DIGITAL VOLTAGE REGULATORS - Described is an apparatus which comprises: a first bridge to be coupled to a first load; a first Pulse Width Modulation (PWM) circuit to drive the first bridge; a second bridge to be coupled to a second load; and a second PWM circuit to drive the second bridge, wherein the first PWM circuit is controlled by a first digital word separate from a second digital word, wherein the second PWM circuit is controlled by the second digital, and wherein the second digital word is derived from the first digital word. | 09-24-2015 |
20160006544 | APPARATUSES, METHODS, AND SYSTEMS FOR JITTER EQUALIZATION AND PHASE ERROR DETECTION - Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments. | 01-07-2016 |
20160066724 | DEVICE AND METHOD FOR MONITORING CONSUMER DINING EXPERIENCE - Embodiments described herein relate generally to monitoring a dining session using smart smallwares. A smart smallware may sense usage or non-usage associated with a dining session of a customer. Based on the sensed non-usage of the smart smallware, the smart smallware may detect a period of inactivity. In response to the detected period of inactivity, the smart smallware may transmit an indication of the detected period of inactivity. This transmitted indication may cause an external monitoring device to notify a waitperson that a customer associated with that smart smallware may require attention. Other embodiments may be described and/or claimed. | 03-10-2016 |
20160066818 | ORTHOTIC SENSOR DEVICE - Embodiments of the present disclosure provide techniques and configurations for an orthotic device. In one instance, the device may include an orthotic device body and at least two sensors spatially disposed inside the orthotic device body. A first sensor may provide a first output responsive to pressure resulting from application of mechanical force to the orthotic device body. A second sensor may provide a second output responsive to flexing resulting from the application of mechanical force to the orthotic device body. The device may also include a control unit communicatively coupled with the sensors to receive and process the outputs provided by the sensors in response to pressure and flexing. Other embodiments may be described and/or claimed. | 03-10-2016 |
20160089075 | BIOFEEDBACK SENSORS IN A BODY AREA NETWORK - Technologies for the sensing of biofeedback signals of a user include a body area network (BAN) system comprising one or more biofeedback sensors and one or more BAN controllers. The biofeedback sensors are configured to sense BAN signals, which may include biofeedback signals and body-coupled communication (BCC) signals. To facilitate communication, the biofeedback sensors may demultiplex the sensed BAN signals into biofeedback signals and incoming BCC signals. Similarly, the biofeedback sensors may multiplex outgoing BCC signals with sensed biofeedback signals. The BAN controller may communicate in a similar manner. Additionally, the BAN controller may process incoming BCC signals and provide feedback to the user based on BCC signals received from the biofeedback sensors. | 03-31-2016 |
20160094121 | POWER SUPPLY TOPOLOGIES WITH CAPACITANCE MANAGEMENT - In at least one embodiment there is provided a method for managing bulk capacitance of a power supply system. The method includes precharging first and second bulk capacitors of the power supply system to approximately a first output voltage level and a second output voltage level, respectively; receiving a first command signal to generate, by the power supply, the first output voltage level; coupling the first bulk capacitance to load circuitry coupled to the power supply; receiving a second command signal to generate, by the power supply, the second output voltage level; and coupling the second bulk capacitance to the load circuitry coupled to the power supply. | 03-31-2016 |
Patent application number | Description | Published |
20120124585 | Increasing Parallel Program Performance for Irregular Memory Access Problems with Virtual Data Partitioning and Hierarchical Collectives - A method for increasing performance of an operation on a distributed memory machine is provided. Asynchronous parallel steps in the operation are transformed into synchronous parallel steps. The synchronous parallel steps of the operation are rearranged to generate an altered operation that schedules memory accesses for increasing locality of reference. The altered operation that schedules memory accesses for increasing locality of reference is mapped onto the distributed memory machine. Then, the altered operation is executed on the distributed memory machine to simulate local memory accesses with virtual threads to check cache performance within each node of the distributed memory machine. | 05-17-2012 |
20140055496 | TRANSPARENT EFFICIENCY FOR IN-MEMORY EXECUTION OF MAP REDUCE JOB SEQUENCES - Executing a map reduce sequence may comprise executing all jobs in the sequence by a collection of a plurality of processes with each process running one or more mappers, combiners, partitioners and reducers for each job, and transparently sharing heap state between the jobs to improve metrics associated with the job. Processes may communicate among themselves to coordinate completion of map, shuffle and reduce phases, and completion of said all jobs in the sequence. | 02-27-2014 |
20140059552 | TRANSPARENT EFFICIENCY FOR IN-MEMORY EXECUTION OF MAP REDUCE JOB SEQUENCES - Executing a map reduce sequence may comprise executing all jobs in the sequence by a collection of a plurality of processes with each process running zero or more mappers, combiners, partitioners and reducers for each job, and transparently sharing heap state between the jobs to improve metrics associated with the job. Processes may communicate among themselves to coordinate completion of map, shuffle and reduce phases, and completion of said all jobs in the sequence. | 02-27-2014 |
20150254558 | GLOBAL PRODUCTION RULES FOR DISTRIBUTED DATA - Running a global production rule on data distributed over a plurality of machines may comprise receiving a local production rule that can run on each of the plurality of machines to jointly accomplish a global computation specified by the global production rule. The local production rule may be deployed to each of the plurality of machines, each of which stores a portion of the data and runs an instance of a rules engine that can run the local production rule. The plurality of machines are enabled to communicate intermediate data produced by the instance of the rules engine running the local production rule on said each of the machines. Coordinating between the plurality of machines is enabled to synchronize one or more local computations performed locally according to the local production rule on said each machine. | 09-10-2015 |
Patent application number | Description | Published |
20100011362 | METHODS FOR SINGLE-OWNER MULTI-CONSUMER WORK QUEUES FOR REPEATABLE TASKS - There are provided methods for single-owner multi-consumer work queues for repeatable tasks. A method includes permitting a single owner thread of a single owner, multi-consumer, work queue to access the work queue using atomic instructions limited to only a single access and using non-atomic operations. The method further includes restricting the single owner thread from accessing the work queue using atomic instructions involving more than one access. The method also includes synchronizing amongst other threads with respect to their respective accesses to the work queue. | 01-14-2010 |
20120131549 | SYSTEMS AND METHODS FOR AUTOMATICALLY OPTIMIZING HIGH PERFORMANCE COMPUTING PROGRAMMING LANGUAGES - Systems and methods for replacing inferior code segments with optimal code segments. Systems and methods for making such replacements for programming languages using Message Passing Interface (MPI) are provided. For example, at the compiler level, point-to-point code segments may be identified and replaced with all-to-all code segments. Programming code may include X10, Chapel and other programming languages that support parallel for loop. | 05-24-2012 |
20120210322 | METHODS FOR SINGLE-OWNER MULTI-CONSUMER WORK QUEUES FOR REPEATABLE TASKS - There are provided methods for single-owner multi-consumer work queues for repeatable tasks. A method includes permitting a single owner thread of a single owner, multi-consumer, work queue to access the work queue using atomic instructions limited to only a single access and using non-atomic operations. The method further includes restricting the single owner thread from accessing the work queue using atomic instructions involving more than one access. The method also includes synchronizing amongst other threads with respect to their respective accesses to the work queue. | 08-16-2012 |
20120304192 | LIFELINE-BASED GLOBAL LOAD BALANCING - Work-stealing is efficiently extended to distributed memory using low degree, low-diameter, fully-connected directed lifeline graphs. These lifeline graphs include k-dimensional hypercubes. When a node is unable to find work after w unsuccessful steals, that node quiesces after informing the outgoing edges in its lifeline graph. Quiescent nodes do not disturb other nodes. Each quiesced node reactivates when work arrives from a lifeline, itself sharing this work with its incoming lifelines that are activated. Termination occurs when computation at all nodes has quiesced. In a language such as X10, such passive distributed termination is detected automatically using the finish construct. | 11-29-2012 |
20160004572 | METHODS FOR SINGLE-OWNER MULTI-CONSUMER WORK QUEUES FOR REPEATABLE TASKS - There are provided methods for single-owner multi-consumer work queues for repeatable tasks. A method includes permitting a single owner thread of a single owner, multi-consumer, work queue to access the work queue using atomic instructions limited to only a single access and using non-atomic operations. The method further includes restricting the single owner thread from accessing the work queue using atomic instructions involving more than one access. The method also includes synchronizing amongst other threads with respect to their respective accesses to the work queue. | 01-07-2016 |